#!

/usr/bin/perl
################################################################################
# This script produces an 'entity' for a given port list.
#
# Usage:
# unix> ./gen_entity.pl <input_port_list_file> <o/p file>(optional)
#
# <input_port_list_file> is in a format such that each line contains
# <port name> <in/out/inout> <width>
# Example input file is
# -------------------
# entity <entity_name>
# port clk in 1
# port dat_in in 7
# port dat_out out 10
# architecture rtl
# -------------------
#
################################################################################
if(@ARGV[0] eq "") {
print "ERROR: Insufficient input fields\n";
print "\n";
print "This script produces an vhdl 'entity' for a given port list.\n";
print "Usage:unix> gen_entity.pl <input_port_list_file> \n";
print "\n";
print "Example port list file \n";
print "-------------------\n";
print "entity my_decoder\n";
print "port clk IN 1\n";
print "port dat_in IN 7\n";
print "port dat_out OUT 10\n";
print "lport ready OUT 10\n";
print "architecture rtl\n";
print "-------------------\n";
print "INFO:lport means it is the last port,and MUST be the last port
in file\n";
print "IMP: NO spaces at start of any line in input file are
allowed\n";
print "IMP: VHDL comments are allowd in file,provided they start as
first ";
print "2 chars of a line\n";
exit;
}
$out_file_given = 0;
print "$#ARGV\n";
if($#ARGV < 1) {
print "INFO:output file not given, defaulting to <entity_name.tb.vhdl>\n";
}##if($#ARGV < 1)
else {
print "INFO:output file given writing file @ARGV[1]\n";
$out_file_given = 1;
}##else

open(infile0,"<@ARGV[0]") || die "Couldn't open infile0. @ARGV[0]\n ";

$out_file_opened = 0;
$entity_name = "your_entity";
$arch_name = "arch";
$one_time = 0;
while ($line = <infile0>) {
if($line =~ /^--/) {
}
else {
if($line =~ /entity/i) {
chomp($line);
@lines = split(/\s+/, $line); #split the line using spaces/tabs..etc..
print "entity found\n";
$entity_name =$lines[1];
print "entity name=$entity_name\n";
}##if($line =~ /entity/i)
if($out_file_opened == 0) {
if($out_file_given == 0) {
open(out1,">$entity_name.tb.vhdl") || die "Couldn't open output file.\n ";
}
else {
open(out1,">$ARGV[1]") || die "Couldn't open output file.\n ";
}
$out_file_opened = 1;
}
if($one_time == 0) {
#The following is printed on the test bench file.
print out1 "-----------------------------------------------------\n";
print out1 "--Generated by Utility gen_entity.pl by Aviral Mittal\n";
print out1 "-----------------------------------------------------\n";
print out1 "--Copy Right Aviral Mittal avimit\@yahoo.com\n";
print out1 "--Any Reproduction of this code in part or whole is \n";
print out1 "--is strictly prohibited without the written consent of\n";
print out1 "--The copy right holder\n";
print out1 "-----------------------------------------------------\n";
print out1 "LIBRARY IEEE;\n";
print out1 "LIBRARY IEEE;\n";
print out1 "USE IEEE.STD_LOGIC_1164.ALL;\n";
print out1 "USE IEEE.numeric_std.ALL;\n";
print out1 "USE IEEE.std_logic_arith.ALL;\n";
print out1 "USE IEEE.std_logic_unsigned.ALL;\n";
print out1 "USE std.textio.ALL;\n";
print out1 "USE IEEE.std_logic_textio.ALL;\n";
print out1 "\n";

print out1 "ENTITY tb IS\n";

print out1 "END ENTITY;\n";
$one_time = 1;
}##($one_time == 0)

if($line =~ /architecture/i) {
chomp($line);
@lines = split(/\s+/, $line); #split the line using spaces/tabs..etc..
print "architecture found\n";
$arch_name =$lines[1];
$arch_found = 1;
print "architecture name=$arch_name\n";
}##if($line =~ /architecture/i)
################################################################################
##FIND PORTS
################################################################################
if($line =~ /^port/i) {
chomp($line);
@lines = split(/\s+/, $line); #split the line using spaces/tabs..etc..
if($lines[3] eq 0) {
 $component = "$component $lines[1] : $lines[2] std_logic;\n";
$sig_list = "$sig_list SIGNAL $lines[1] : std_logic;\n";
}
else {
$component = "$component $lines[1] : $lines[2] std_logic_vector($lines[3]
downto 0);\n";
$sig_list = "$sig_list SIGNAL $lines[1] : std_logic_vector($lines[3] downto
0);\n";
}
$port_map = "$port_map $lines[1] => $lines[1],\n";
}##if($line =~ /^port/i)
elsif($line =~ /lport/i) {
chomp($line);
@lines = split(/\s+/, $line); #split the line using spaces/tabs..etc..
if($lines[3] eq 0) {
$component = "$component $lines[1] : $lines[2] std_logic\n";
$sig_list = "$sig_list SIGNAL $lines[1] : std_logic;\n";
}#if($lines[3] == 1)
else {
$component = "$component $lines[1] : $lines[2] std_logic_vector($lines[3]
downto 0)\n";
$sig_list = "$sig_list SIGNAL $lines[1] : std_logic_vector($lines[3] downto
0);\n";
}#else
$port_map = "$port_map $lines[1] => $lines[1]\n";
}##if($line =~ /port/i)
}##if($line !=~ /^--/)
}##while ($line = <infile0>)

print out1 "\n";

print out1 "ARCHITECTURE behav OF tb IS\n";
print out1 "--Signal Declaration Section\n";
print out1 $sig_list;
print out1 "--Signal Declaration Section Ends\n";
print out1 "\n";
print out1 "COMPONENT $entity_name\n";
print out1 "\n";
print out1 "PORT (\n";
print out1 "$component";
print out1 ");\n";
print out1 "END COMPONENT; -- $entity_name\n";
print out1 "\n";
print out1 "BEGIN\n";
print out1 "$entity_name";
print out1 "_I0:$entity_name\n PORT MAP (\n";
print out1 "$port_map";
print out1 ");\n";
print out1 "END behav;\n";