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PCB STACK UP TE1 Block Diagram


LAYER 1 : TOP
Azalia CLOCK GENERATOR
LAYER 2 : SGND HDMI Transmitter
HDMI Intel
Page 21 Sil1392 CK505
LAYER 3 : IN1 Page 21 ICS9LPR363
Merom Page 2
A A
LAYER 4 : IN2 (35W)
CRT
Page 20
LAYER 5 : VCC Page 3,4

LAYER 6 : BOT LCD PANEL FSB(667/800MHZ) CRT


Page 19 Azalia VGA CONNECTOR
HDMI
SDVO (FOX)
LCD/LED
VCC_CORE LED
LED PANEL PCI-E 16X Lan Page 18
Page 19 Driver IC CRT Crestline GM
Page 19

+1.5V LVDS DDRII-SODIMM1


533/ 667 MHZ DDR II
DDRII-SODIMM2
SATA Page 5,7,8,9,10,11 Page 12,13
SATA - HDD
Page 22
+1.05V
PATA MINI CARD-3 MINI CARD-4
IDE - ODD DMI(x2/x4)
Page 22
U 9H_HD-DVD D ROBSON
Page 25 Page 25 (FTB)
B +1.25V B

LAN/B USB USB-0


DAUGHTER PCIE-2 PCIE-4
BOARD PCI-Express
Page 26 (FTB)
PCIE-6 PCIE-3 PCIE-1 PCIE-5
+1.8VSUS Camera USB-3
+1.8V MINI CARD-1 MINI CARD-2 NEW CARD
Page 19 Connector
U&D 5.6H_WLAN U 5.6H_TV/ROBSON
+3VPCU WLAN USB-5 USB 2.0 ICH8M Page 25
D 7.5H_HD-DVD Page 27
Page 26

+3V_S5 Page 25 Page 25


LAN/RJ11/RJ45/USB/RF DAUGHTER BOARD
+3VSUS
+3V Finger Printer USB-1
DAUGHTER
+5VPCU BOARD
Page 26 (FTB) Marvell LAN
+5V_S5 10/100/Giga
USB-2
Azalia PCI Bus
+5V Bluetooth Page 14,15,16,17
88E8040T/88E8055
+SMDDR_VTERM Page 26
+SMDDR_VREF PCMCIA Card
New Card USB-9
LPC Controller Reader/1394
32.768KHz
Page 27 (CB 1410) (OZ129T) Transformer
Page 23 Page 24
C M/B USB 2 USB-7 C

Page 27 RJ45 RJ11 USB RF


PCMCIA 5 IN 1 1394
Felica USB-4 WPC8763LDG
DAUGHTER
BOARD
Page 26 (FTB) PCI ROUTING LED Board
TABLE IDSEL INTERUPT DEVICE
Page 28
M/B USB USB-6 REQ0# / GNT0# AD17 INTA# OZ129T
REQ1# / GNT1# AD18 INTC# CB1410
Page 27
Low Cost Board
TV/ROBSON USB-8
Page 26
Page 25
DAUGHTER
Port-A MMB Board
HP VR FAN Kill SW Key FLASH CIR G-Sensor BOARD
Port-B AUDIO CODEC
Page 30 Board ROM Page 26
(CX20561)
Page 30 Page 3 Page 27 Page 26 Page 28 Page 28 Page 22
MIC JACK
Page 30 Page 29 Power Board
Page 26
Port-C
D INT SPK SPK AMP D
Page 29 Page 29 Touch Pad
FM TUNER
Reserve FM Board
& MDC Page 29 Page 26
Reserve MIC Page 30
Page 19 BTO BOM OPTION
IV@ : UMA
EV@ : VGA/B Quanta Computer Inc.
CB@ : CARD BUS
Reserve MIC GS@ : G-SENSOR
Page 29 NEW@ : NEW CARD PROJECT : TE1
LCD@ : LCD TYPE PANEL Size Document Number Rev
MDC Board RJ11 1A
LED@ : LED TYPE PANEL
CIR@ : CIR
Block Diagram
Date: Tuesday, September 18, 2007 Sheet 1 of 38
1 2 3 4 5 6 7 8

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Clock Generator
+1.25V_VDD

PBY160808T-301Y-N_6 L21 +1.25V


VDD :0.25A, 0.106A(Typ)

+3V L44 PBY160808T-301Y-N_6 VDD_CK_VDD_PCI C536 0.1u/10V_4 C211 C212 C519 C213 C214 C509 C218 C215

*10u/10V_8 *10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4


C541
C533 0.1u/10V_4
*10u/10V_8
D C547 *10u/10V_8 D

C529 0.1u/10V_4 U13


2 48
C508 0.1u/10V_4 VDD_PCI IO_VOUT
9
VDD_48 CGCLK_SMB
16 64
C231 33p/50V_4 CG_XIN VDD_PLL3 SCLK CGDAT_SMB
61 63
VDD_REF SDA
CK505
2

Y3 C475 0.1u/10V_4 39 38 PM_STPPCI# (16)


VDD_SRC SRC5/PCI_STOP#
CL=20p 55 37 PM_STPCPU# (16)
14.318MHZ VDDIO : 0.08A, 0.032A(Typ) VDD_CPU SRC5#/CPU_STOP#

+1.25V_VDD 12 54 CLK_CPU_BCLK_R RP54 1 2 0X2


VDD_96_IO CPU0 CLK_CPU_BCLK (3)
1

C234 33p/50V_4 CG_XOUT C534 0.1u/10V_4 20 53 CLK_CPU_BCLK#_R 3 4 To CPU


VDD_PLL3_IO CPU0# CLK_CPU_BCLK# (3)
26
VDD_SRC_IO_1 CLK_MCH_BCLK_R RP52
45 51 1 2 0X2 CLK_MCH_BCLK (5)
VDD_SRC_IO_3 CPU1 CLK_MCH_BCLK#_R
36
VDD_SRC_IO_2 CPU1#
50 3 4 CLK_MCH_BCLK# (5) To NB
49
Realtek FAE PCI3: Int PD driven issue. Add Ext PD for Realtek VDD_CPU_IO CLK_PCIE_MINI3&4_R
47
SRC8/ITP CLK_PCIE_MINI3&4#_R
46
SRC8#/ITP#
To Debug Card PCLK_DEBUG R228 33_4 PCLK_DEBUG_R 1 35 CLK_PCIE_3GPLL#_R RP44 1 2 0X2
(25) PCLK_DEBUG PCI0/CR#_A SRC10# CLK_PCIE_3GPLL# (6)
34 CLK_PCIE_3GPLL_R 3 4 To NB
SRC10 CLK_PCIE_3GPLL (6)
To PCMCIA PCLK_PCM R226 33_4 PCLK_PCM_R 3
(23) PCLK_PCM PCI1/CR#_B
33 CLK_MCH_OE#_R R195 475/F_4 CLK_MCH_OE# (6)
PCLK_OZ129 R223 33_4 PCLK_OZ129_R SRC11/CR#_H NEW_CLKREQ#_R R196 475/F_4
(24) PCLK_OZ129 4 32 NEW_CLKREQ# (27)
PCI2/TME SRC11#/CR#_G
To OZ129
R220 10K_4 PCI_CLK_SIO_R 5 30 CLK_PCIE_NEW_R RP45 3 4 0X2
PCI3 SRC9 CLK_PCIE_NEW (27)
31 CLK_PCIE_NEW_R# 1 2 To New Card
SRC9# CLK_PCIE_NEW# (27)
PCLK_591 R214 33_4 PCLK_591_R 6
(28) PCLK_591 PCI4/SRC5_EN
To EC 44 CLK_PCIE_MINI2_R RP49 1 2 0X2
C SRC7/CR#_F CLK_PCIE_MINI2 (25) C
+3V R208 *10K_4 R211 33_4 PCLK_ICH_R 7 43 CLK_PCIE_MINI2#_R 3 4 To MINI2
PCIF5/ITP_EN SRC7#/CR#_E CLK_PCIE_MINI2# (25)
To SB PCLK_ICH CG_XIN 60 41 CLK_PCIE_MINI_R RP47 1 2 0X2
(15) PCLK_ICH XTAL_IN SRC6 CLK_PCIE_MINI (25)
40 CLK_PCIE_MINI#_R 3 4 To MINI1
SRC6# CLK_PCIE_MINI# (25)
R207 10K_4 CG_XOUT 59
XTAL_OUT CLK_PCIE_LAN_R RP46
27 3 4 0X2 CLK_PCIE_LAN (26)
CLKUSB_48 R205 33_4 FSA SRC4 CLK_PCIE_LAN#_R
To SB (16) CLKUSB_48
10
USB_48/FSA SRC4#
28 1 2 CLK_PCIE_LAN# (26) To LAN
CLK_BSEL0 R210 2.2K_4
CLK_BSEL1 57 24 CLK_PCIE_ICH_R RP48 3 4 0X2
FSB/TEST/MODE SRC3/CR#_C CLK_PCIE_ICH (15)
25 CLK_PCIE_ICH#_R 1 2 To SB
SRC3#/CR#_D CLK_PCIE_ICH# (15)
CLK_BSEL2 R219 10K_4 FSC 62
REF0/FSC/TESTSEL CLK_PCIE_SATA_R RP50
21 3 4 0X2 CLK_PCIE_SATA (14)
14M_ICH R213 33_4 SRC2/SATA CLK_PCIE_SATA#_R
To SB (16) 14M_ICH 8
VSS_PCI SRC2#/SATA#
22 1 2 CLK_PCIE_SATA# (14) To SB
11
VSS_48 DREFSSCLK_R
15 17
VSS_IO SRC1/SE1 DREFSSCLK#_R
19 18
VSS_PLL3 SRC1#/SE2
52
R218 *10K_4 PCLK_591 R227 10K_4 PCLK_OZ129 VSS_CPU DREFCLK_R RP55
+3V +3V 23 13 3 4 IV@0X2 DREFCLK (6)
VSS_SRC1 SRC0/DOT96 DREFCLK#_R
29
VSS_SRC2 SRC0#/DOT96#
14 1 2 DREFCLK# (6) To NB
R217 10K_4 R222 *10K_4 42
VSS_SRC3
58 56 CK_PWRGD (16)
VSS_REF CKPWRGD/PWRDWN#
ICS9LPRS365BGLFT CLK_PCIE_MINI3&4_R RP51 1 2 IV@0X2 CLK_PCIE_MINI3 (25)
CLK_PCIE_MINI3&4#_R 3 4 To MINI3
CLK_PCIE_MINI3# (25)
ICS9LPRS365 RTM875T-606
(ALPRS365K13) (AL000875K06) PULL HIGH PULL DOWN RP72 3 4 EV@0X2 CLK_PCIE_MINI4 (25)
1 2 CLK_PCIE_MINI4# (25) To MINI4
PCI2/TME
Pin 4 PCI2/TME internal PD NO OVERCLOCKING (default) NORMAL RUN DREFSSCLK_R RP70 1 2 IV@0X2 DREFSSCLK (6)
DREFSSCLK#_R 3 4 To NB
DREFSSCLK# (6)
PCI-3/SRC5_EN PIN37/38 IS
Pin 5 PCI-3 internal PD PIN37/38 IS SRC5 PCI_STOP/CPU_STOP (default)
B PCLK_PCM C230 *33p/50V_4 RP53 3 4 EV@0X2 B
CLK_MXM (18)
PCI-4/27M_SEL PIN 17/18 PCLK_591 C225 *33p/50V_4 1 2 To VGA Card
CLK_MXM# (18)
Pin 6 PCI-4/27M_SEL internal PD PIN 17/18 IS 27MHz IS SRC/DOT (default) CLKUSB_48 C221 *33p/50V_4
14M_ICH C223 *33p/50V_4
PCIF-5/ITP_EN PCLK_ICH C222 *33p/50V_4
Pin 7 PCIF-5/ITP_EN internal PD PIN 46/47 IS CPUITP PIN 46/47 IS SRC8 (default) PCLK_DEBUG C229 *33p/50V_4

+3V
BSEL Frequency Select Table Clock Gen I2C

R464 0_4 CLK_BSEL0


(3) CPU_BSEL0 MCH_BSEL0 (6)
FSC FSB FSA Frequency Q35
R221

2
+1.05V R463 *56_4 RHU002N06
0 0 0 266Mhz 10K_4
3 1 CGDAT_SMB
(16,21,25,27) SDATA CGDAT_SMB (13)
R465 *1K_4
0 0 1 133Mhz
+3V
0 1 1 166Mhz
R206 0_4 CLK_BSEL1
(3) CPU_BSEL1 MCH_BSEL1 (6)
0 1 0 200Mhz
Q37
R204 *0_4 R225

2
A RHU002N06 A
1 1 0 400Mhz
10K_4
+1.05V R203 *1K_4 3 1 CGCLK_SMB
(16,21,25,27) SCLK CGCLK_SMB (13)
1 1 1 Reserved

1 0 1 100Mhz
R460 0_4 CLK_BSEL2
(3) CPU_BSEL2 MCH_BSEL2 (6)
R197 10K_4 NEW_CLKREQ#_R
Quanta Computer Inc.
1 0 0 333Mhz +3V
R209 *0_4
PROJECT : TE1
Size Document Number Rev
+1.05V R454 *1K_4
CLK. GEN./ CK505 1A

Date: Thursday, September 20, 2007 Sheet 2 of 38


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U26A
CPU(HOST) (5) H_A#[16:3]
H_A#3 J4 H1
CPU Thermal monitor
A[3]# ADS# H_ADS# (5)
H_A#4

ADDR GROUP 0
L5 E2 H_BNR# (5)
H_A#5 A[4]# BNR# +3V
L4 G5 H_BPRI# (5)
H_A#6 A[5]# BPRI#
K5
H_A#7 A[6]#
M3 H5 H_DEFER# (5)
H_A#8 A[7]# DEFER# +3V
N2 F21 H_DRDY# (5)
H_A#9 A[8]# DRDY#
J1 E1 H_DBSY# (5)
H_A#10 A[9]# DBSY#
N3
H_A#11 A[10]# Q10
P5 F1 H_BREQ#0 (5)
H_A#12 A[11]# BR0#
P2
A[12]#

CONTROL

2
H_A#13 L2 D20 H_IERR# R35 56.2/F_4 +1.05V RHU002N06
H_A#14 A[13]# IERR# R79 R83 R42
P4 B3 H_INIT# (14)
H_A#15 A[14]# INIT#
P1 (22,28) 2ND_MBCLK 3 1
H_A#16 A[15]# 10K_4 10K_4 200_6
R1 H4 H_LOCK# (5)
D A[16]# LOCK# LM86VCC D
(5) H_ADSTB0# M1
ADSTB[0]#
(5) H_REQ#[4:0] C1 H_CPURST# (5)
H_REQ#0 RESET# C52
K3 F3 H_RS#0 (5)
H_REQ#1 REQ[0]# RS[0]# +3V
H2 F4 H_RS#1 (5)
H_REQ#2 REQ[1]# RS[1]# 0.1u/10V_4
K2 G3 H_RS#2 (5)
H_REQ#3 REQ[2]# RS[2]#
J3 G2 H_TRDY# (5)
H_REQ#4 REQ[3]# TRDY# Q11 U28
L1
REQ[4]# H_THERMDA
(5) H_A#[35:17] G6 H_HIT# (5)
HIT#

2
H_A#17 Y2 E4 RHU002N06 8 1
A[17]# HITM# H_HITM# (5) SCLK VCC
H_A#18 U5
H_A#19 A[18]# C402
R3 AD4 T7 (22,28) 2ND_MBDATA 3 1 7 2
A[19]# BPM[0]# SDA DXP

ADDR GROUP 1
H_A#20 W6 AD3
A[20]# BPM[1]# T6
H_A#21 U4 2200p/50V_4

XDP/ITP SIGNALS
AD1 T4 6 3
H_A#22 A[21]# BPM[2]# ALERT# DXN
Y5 AC4 T8
H_A#23 A[22]# BPM[3]# H_THERMDC
U1 AC2 T2 4 5
H_A#24 A[23]# PRDY# R81 *10K_4 OVERT# GND
R4 AC1 T1 +3V
H_A#25 A[24]# PREQ# XDP_TCK
T5 AC5
H_A#26 A[25]# TCK XDP_TDI LM95245
T3 AA6
H_A#27 A[26]# TDI THERM_ALERT#_R
W2
A[27]# TDO
AB3 T5 (16) THERM_ALERT# R80 *0_4 ADDRESS: 98H
H_A#28 W5 AB5 XDP_TMS
H_A#29 A[28]# TMS XDP_TRST# +3V R39 10K_4 THER_SHD#
Y4 AB6
H_A#30 A[29]# TRST# XDP_DBRESET# R33 0_4
U2 C20 SYS_RST# (16)
H_A#31 A[30]# DBR# +3V
V4
H_A#32 A[31]#
W3
H_A#33 A[32]# R43 56.2/F_4
AA4 THERMAL +1.05V
H_A#34 A[33]# R92
AB2
H_A#35 A[34]# H_PROCHOT_R# R45 *2.2K_4
AA3 D21 H_PROCHOT# (33)
A[35]# PROCHOT# H_THERMDA 330_4
(5) H_ADSTB1# V1 A24
ADSTB[1]# THERMDA H_THERMDC
B25
THERMDC <check list>
(14) H_A20M# A6
A20M# THERMTRIP#_PWR Default PU 56ohm if no use.
ICH

A5 C7 Q9
(14) H_FERR# FERR# THERMTRIP#

2
Serial R NC, If connect to power side PU 68ohm. Serial R 2.2K
(14) H_IGNNE# C4
C IGNNE# MMBT3904 C

(14) H_STPCLK# D5 1 3 SYS_SHDN# (32)


STPCLK#
(14) H_INTR C6 H CLK
LINT0
(14) H_NMI B4 A22 CLK_CPU_BCLK (2)
LINT1 BCLK[0]
(14) H_SMI# A3 A21 CLK_CPU_BCLK# (2)
SMI# BCLK[1]
M4
RSVD[01] +3V
N5
T2
RSVD[02] CPU FAN
RSVD[03]
V3
RSVD[04]
RESERVED

B2
RSVD[05] R86
C3
RSVD[06]
D2
RSVD[07] 10K_4
D22
RSVD[08]
D3 +5V
RSVD[09] (28) FANSIG CN22
F6
RSVD[10] U27
C68 2.2u/6.3V_6 2 3 TH_FAN_POWER
VIN VO 1
5
Merom Ball-out Rev 1a R84 0_4 GND 2
(5) H_D#[15:0] H_D#[47:32] (5) (18) SYSFANON# 1 6
U26B /FON GND C65 C70 C71 3
7
H_D#0 H_D#32 GND
E22 Y22 4 8
H_D#1 D[0]# D[32]# H_D#33 (28) VFAN VSET GND *10u/10V_8 0.01u/16V_4 0.01u/16V_4
F24 AB24
H_D#2 D[1]# D[33]# H_D#34 G995
E26 V24 FAN_CON
H_D#3 D[2]# D[34]# H_D#35 FANPWR = 1.6*VSET
G22 V26
H_D#4 D[3]# D[35]# H_D#36
DATA GRP 0

F23 V23
H_D#5 D[4]# D[36]# H_D#37
G25 T22
H_D#6 D[5]# D[37]# H_D#38
E25 U25
H_D#7 D[6]# D[38]# H_D#39
H_D#8
E23
K24
D[7]# D[39]#
U23
Y25 H_D#40
PU/PD (ITP700) Thermal Trip
DATA GRP 2

H_D#9 D[8]# D[40]# H_D#41


G24 W22
H_D#10 D[9]# D[41]# H_D#42
J24 Y23
B H_D#11 D[10]# D[42]# H_D#43 B
J23 W24
H_D#12 D[11]# D[43]# H_D#44 +1.05V
H22 W25
H_D#13 D[12]# D[44]# H_D#45
F26 AA23
H_D#14 D[13]# D[45]# H_D#46
K22 AA24
H_D#15 D[14]# D[46]# H_D#47 +1.05V
H23 AB25
D[15]# D[47]#
(5) H_DSTBN#0 J26 Y26 H_DSTBN#2 (5)
DSTBN[0]# DSTBN[2]#
(5) H_DSTBP#0 H26 AA26 H_DSTBP#2 (5)
DSTBP[0]# DSTBP[2]#
(5) H_DINV#0 H25 U22 H_DINV#2 (5)
DINV[0]# DINV[2]#

3
(5) H_D#[31:16] H_D#[63:48] (5)
H_D#16 N22 AE24 H_D#48 XDP_TMS R17 39/F_4
H_D#17 D[16]# D[48]# H_D#49 Q5 R34 D3
K25 AD24 (6,16,33) DELAY_VR_PWRGOOD 2
H_D#18 D[17]# D[49]# H_D#50
P26 AA21
H_D#19 D[18]# D[50]# H_D#51 FDV301N *10K_4 *BAS316
R23 AB22
H_D#20 D[19]# D[51]# H_D#52 XDP_TDI R21 150_4
L23 AB21
H_D#21 D[20]# D[52]# H_D#53
DATA GRP 1

M24 AC26
D[21]# D[53]#

1
H_D#22 L22 AD20 H_D#54 +1.05V C50 *1u/16V_6
H_D#23 D[22]# D[54]# H_D#55
M23 AE22
H_D#24 D[23]# D[55]# H_D#56
P25 AF23
+1.05V H_D#25 D[24]# D[56]# H_D#57
P23 AC25
H_D#26 D[25]# D[57]# H_D#58
P22 AE21
DATA GRP 3

H_D#27 D[26]# D[58]# H_D#59 R30


T24 AD21
H_D#28 D[27]# D[59]# H_D#60 XDP_TCK R22 27_4 Q6
R24 AC22
H_D#29 D[28]# D[60]# H_D#61 56.2/F_4
L25 AD23
D[29]# D[61]#

2
H_D#30 T25 AF22 H_D#62 MMBT3904
H_D#31 D[30]# D[62]# H_D#63
N25 AC23
R68 D[31]# D[63]# XDP_TRST# R18 680/F_4 THERMTRIP#_PWR
(5) H_DSTBN#1 L26 AE25 H_DSTBN#3 (5) 1 3 SYS_SHDN# (32)
1K/F_4 DSTBN[1]# DSTBN[3]#
(5) H_DSTBP#1 M26 AF24 H_DSTBP#3 (5)
DSTBP[1]# DSTBP[3]#
(5) H_DINV#1 N24 AC20 H_DINV#3 (5)
DINV[1]# DINV[3]#
H_GTLREF AD26 R26 COMP0 R67 27.4/F_6 <Check list & CRB>
R48 *1K_4 CPU_TEST1 GTLREF COMP[0] COMP1 R63 54.9/F_4 Layout note: L<0.5" R31 *0_4
C23 MISC U26 PM_THRMTRIP# (6,14)
A R59 *1K_4 CPU_TEST2 TEST1 COMP[1] COMP2 R20 27.4/F_6 COMP0/2 Z=27.4ohm A
D25 AA1
<Check list & CRB> CPU_TEST3 TEST2 COMP[2] COMP3 R19 54.9/F_4 COMP1/3 Z=54.9
T9 C24 Y1
Layout note: Z=55 ohm CPU_TEST4 AF26 TEST3 COMP[3]
H_GTLREF<0.5" T11 TEST4
CPU_TEST5 AF1 E5
T3 TEST5 DPRSTP# ICH_DPRSTP# (6,14,33)
CPU_TEST6 A26 B5
T10 TEST6 DPSLP# H_DPSLP# (14)
R64 D24
DPWR# H_DPWR# (5)
2K/F_4 B22 D6
(2) CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGD (14)
B23 D7
(2)
(2)
CPU_BSEL1
CPU_BSEL2 C21
BSEL[1]
BSEL[2]
SLP#
PSI#
AE6
H_CPUSLP# (5)
PSI# (33)
Quanta Computer Inc.
Merom Ball-out Rev 1a
PROJECT : TE1
Size Document Number Rev
CPU(1 of 2)/FAN/Thermal 1A

Date: Thursday, September 20, 2007 Sheet 3 of 38


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CPU(Power)
VCC_CORE

U26D
<REV.NO. 0.5/REF.NO.19343> A4 P6
VSS[001] VSS[082]
A8 VSS[002] VSS[083] P21
Ivcc Max 52A A11 P24
VSS[003] VSS[084]
A14 VSS[004] VSS[085] R2
U26C Ivccp Max 6A(VCCP supply before Vcc stable)
A16 VSS[005] VSS[086] R5
C376 C33 C392 C394 C382 C390 C372 C374 C34 C381 Max 2A(VCCP supply after Vcc stable)
D A7 AB20 A19 R22 D
VCC[001] VCC[068] VSS[006] VSS[087]
A9 AB7 A23 R25
10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 10u/6.3V_8 VCC[002] VCC[069] Ivcca Max 130mA VSS[007] VSS[088]
A10 VCC[003] VCC[070] AC7 AF2 VSS[008] VSS[089] T1
A12 VCC[004] VCC[071] AC9 B6 VSS[009] VSS[090] T4
A13 AC12 B8 T23
VCC[005] VCC[072] VSS[010] VSS[091]
A15 AC13 B11 T26
VCC[006] VCC[073] VSS[011] VSS[092]
A17 VCC[007] VCC[074] AC15 B13 VSS[012] VSS[093] U3
A18 VCC[008] VCC[075] AC17 B16 VSS[013] VSS[094] U6
A20 AC18 B19 U21
VCC[009] VCC[076] VSS[014] VSS[095]
B7 VCC[010] VCC[077] AD7 B21 VSS[015] VSS[096] U24
B9 VCC[011] VCC[078] AD9 B24 VSS[016] VSS[097] V2
B10 AD10 C5 V5
C389 C391 C393 C373 C385 C45 C39 C44 C378 C371 VCC[012] VCC[079] VSS[017] VSS[098]
B12 AD12 C8 V22
VCC[013] VCC[080] +1.05V VSS[018] VSS[099]
B14 VCC[014] VCC[081] AD14 C11 VSS[019] VSS[100] V25
10u/6.3V_8 10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 B15 AD15 C14 W1
VCC[015] VCC[082] VSS[020] VSS[101]
B17 AD17 C16 W4
VCC[016] VCC[083] VSS[021] VSS[102]
B18 VCC[017] VCC[084] AD18 C19 VSS[022] VSS[103] W23
B20 VCC[018] VCC[085] AE9 C2 VSS[023] VSS[104] W26
C9 AE10 C22 Y3
VCC[019] VCC[086] VSS[024] VSS[105]
C10 AE12 C25 Y6
VCC[020] VCC[087] VSS[025] VSS[106]
C12 AE13 D1 Y21
VCC[021] VCC[088] VSS[026] VSS[107]
C13 VCC[022] VCC[089] AE15 D4 VSS[027] VSS[108] Y24
C15 AE17 C28 C26 C47 D8 AA2
VCC[023] VCC[090] VSS[028] VSS[109]
C17 AE18 D11 AA5
C29 C32 C383 C386 C30 C384 VCC[024] VCC[091] 0.1u/16V_6 0.1u/16V_6 0.1u/16V_6 VSS[029] VSS[110]
C18 VCC[025] VCC[092] AE20 D13 VSS[030] VSS[111] AA8
D9 AF9 D16 AA11
*10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 VCC[026] VCC[093] VSS[031] VSS[112]
D10 AF10 D19 AA14
VCC[027] VCC[094] VSS[032] VSS[113]
C D12 VCC[028] VCC[095] AF12 D23 VSS[033] VSS[114] AA16 C
D14 VCC[029] VCC[096] AF14 D26 VSS[034] VSS[115] AA19
D15 AF15 E3 AA22
VCC[030] VCC[097] VSS[035] VSS[116]
D17 VCC[031] VCC[098] AF17 E6 VSS[036] VSS[117] AA25
D18 VCC[032] VCC[099] AF18 E8 VSS[037] VSS[118] AB1
E7 AF20 <Check list> E11 AB4
VCC[033] VCC[100] ESR=12m ohm VSS[038] VSS[119]
E9 E14 AB8
VCC[034] VSS[039] VSS[120]
E10 VCC[035] VCCP[01] G21 E16 VSS[040] VSS[121] AB11
E12 VCC[036] VCCP[02] V6 E19 VSS[041] VSS[122] AB13
C375 C37 C387 C38 C43 C395 E13 J6 E21 AB16
VCC[037] VCCP[03] + C35 C25 C48 C46 VSS[042] VSS[123]
E15 K6 E24 AB19
*10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 *10u/6.3V_8 VCC[038] VCCP[04] VSS[043] VSS[124]
E17 M6 F5 AB23
VCC[039] VCCP[05] *330u/2.5V_7343 0.1u/16V_6 0.1u/16V_6 0.1u/16V_6 VSS[044] VSS[125]
E18 VCC[040] VCCP[06] J21 F8 VSS[045] VSS[126] AB26
E20 K21 F11 AC3
VCC[041] VCCP[07] VSS[046] VSS[127]
F7 M21 F13 AC6
VCC[042] VCCP[08] VSS[047] VSS[128]
F9 VCC[043] VCCP[09] N21 F16 VSS[048] VSS[129] AC8
F10 N6 F19 AC11
VCC[044] VCCP[10] VSS[049] VSS[130]
F12 R21 F2 AC14
VCC[045] VCCP[11] VSS[050] VSS[131]
F14 VCC[046] VCCP[12] R6 F22 VSS[051] VSS[132] AC16
F15 VCC[047] VCCP[13] T21 F25 VSS[052] VSS[133] AC19
+ C40 + C41 F17 T6 G4 AC21
VCC[048] VCCP[14] +1.5V VSS[053] VSS[134]
F18 VCC[049] VCCP[15] V21 G1 VSS[054] VSS[135] AC24
*330u/2.5V_7343 *330u/2.5V_7343 F20 W21 <CRB> G23 AD2
VCC[050] VCCP[16] .01U near to B26 ball VSS[055] VSS[136]
AA7 G26 AD5
VCC[051] +VCCA_PROC R73 0_6 VSS[056] VSS[137]
AA9 B26 H3 AD8
VCC[052] VCCA[01] VSS[057] VSS[138]
AA10 VCC[053] VCCA[02] C26 H6 VSS[058] VSS[139] AD11
AA12 VCC[054] H21 VSS[059] VSS[140] AD13
AA13 AD6 VCC_CORE C62 C64 H24 AD16
B VCC[055] VID[0] H_VID0 (33) VSS[060] VSS[141] B
AA15 VCC[056] VID[1] AF5 H_VID1 (33) J2 VSS[061] VSS[142] AD19
AA17 AE5 0.01u/16V_4 *10u/10V_8 J5 AD22
VCC[057] VID[2] H_VID2 (33) VSS[062] VSS[143]
AA18 VCC[058] VID[3] AF4 H_VID3 (33) J22 VSS[063] VSS[144] AD25
AA20 AE3 R391 J25 AE1
VCC[059] VID[4] H_VID4 (33) VSS[064] VSS[145]
AB9 AF3 H_VID5 (33) K1 AE4
VCC[060] VID[5] 100/F_6 VSS[065] VSS[146]
AC10 VCC[061] VID[6] AE2 H_VID6 (33) K4 VSS[066] VSS[147] AE8
AB10 K23 AE11
VCC[062] VSS[067] VSS[148]
AB12 K26 AE14
VCC[063] VSS[068] VSS[149]
AB14 VCC[064] VCCSENSE AF7 VCCSENSE (33) L3 VSS[069] VSS[150] AE16
AB15 VCC[065] L6 VSS[070] VSS[151] AE19
AB17 L21 AE23
VCC[066] VSS[071] VSS[152]
AB18 VCC[067] VSSSENSE AE7 VSSSENSE (33) L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
Merom Ball-out Rev 1a <CRB> M5 AF6
Routing 27.4ohm with 50mils spacing VSS[074] VSS[155]
. M22 VSS[075] VSS[156] AF8
R390 PU/PD near to CPU 1" M25 AF11
VSS[076] VSS[157]
N1 VSS[077] VSS[158] AF13
100/F_6 N4 AF16
VSS[078] VSS[159]
N23 AF19
VSS[079] VSS[160]
N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] A25
VSS[163] AF25
Merom Ball-out Rev 1a
.

A A

Quanta Computer Inc.


PROJECT : TE1
Size Document Number Rev
CPU(2 of 2) 1A

Date: Thursday, September 20, 2007 Sheet 4 of 38


5 4 3 2 1

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NB(HOST)
H_A#[35:3] (3)
U29A
(3) H_D#[63:0]
J13 H_A#3
H_D#0 H_A#_3 H_A#4
E2 B11
+1.05V H_D#1 H_D#_0 H_A#_4 H_A#5
G2 C11
H_D#2 H_D#_1 H_A#_5 H_A#6
G7 M11
H_D#3 H_D#_2 H_A#_6 H_A#7
M6 C15
H_D#4 H_D#_3 H_A#_7 H_A#8
H7 F16
H_D#5 H_D#_4 H_A#_8 H_A#9
H3 L13
R411 H_D#6 H_D#_5 H_A#_9 H_A#10
D G4 G17 D
H_D#7 H_D#_6 H_A#_10 H_A#11
F3 C14
221/F_4 H_D#8 H_D#_7 H_A#_11 H_A#12
N8 K16
H_D#9 H_D#_8 H_A#_12 H_A#13
H2 B13
H_SWING H_D#10 H_D#_9 H_A#_13 H_A#14
M10 L16
H_D#11 H_D#_10 H_A#_14 H_A#15
N12 J17
H_D#12 H_D#_11 H_A#_15 H_A#16
N9 B14
R410 C404 H_D#13 H_D#_12 H_A#_16 H_A#17
H5 K19
H_D#14 H_D#_13 H_A#_17 H_A#18
P13 P15
100/F_4 0.1u/10V_4 H_D#15 H_D#_14 H_A#_18 H_A#19
K9 R17
H_D#16 H_D#_15 H_A#_19 H_A#20
M2 B16
H_D#17 H_D#_16 H_A#_20 H_A#21
W10 H20
H_D#18 H_D#_17 H_A#_21 H_A#22
Y8 L19
H_D#19 H_D#_18 H_A#_22 H_A#23
V4 D17
H_D#20 H_D#_19 H_A#_23 H_A#24
M3 M17
H_D#21 H_D#_20 H_A#_24 H_A#25
J1 N16
H_D#22 H_D#_21 H_A#_25 H_A#26
N5 J19
H_D#23 H_D#_22 H_A#_26 H_A#27
N3 B18
H_D#24 H_D#_23 H_A#_27 H_A#28
W6 E19
H_D#25 H_D#_24 H_A#_28 H_A#29
W9 B17
H_D#26 H_D#_25 H_A#_29 H_A#30
N2 B15
H_RCOMP H_D#27 H_D#_26 H_A#_30 H_A#31
Y7 E17
H_D#28 H_D#_27 H_A#_31 H_A#32
Y9 C18
10:20 mils(Width:Spacing) H_D#29 H_D#_28 H_A#_32 H_A#33
P4 A19
R409 H_D#30 H_D#_29 H_A#_33 H_A#34
W3 B19
C
H_D#31 H_D#_30 H_A#_34 H_A#35
C
N1 N19
24.9/F_4 H_D#32 H_D#_31 H_A#_35
AD12
H_D#33 H_D#_32
AE3 G12 H_ADS# (3)
H_D#34 H_D#_33 H_ADS#
AD9 H17

HOST
H_D#_34 H_ADSTB#_0 H_ADSTB0# (3)
H_D#35 AC9 G20
H_D#_35 H_ADSTB#_1 H_ADSTB1# (3)
H_D#36 AC7 C8
H_D#_36 H_BNR# H_BNR# (3)
H_D#37 AC14 E8
H_D#_37 H_BPRI# H_BPRI# (3)
H_D#38 AD11 F12
H_D#_38 H_BREQ# H_BREQ#0 (3)
H_D#39 AC11 D6
H_D#_39 H_DEFER# H_DEFER# (3)
H_D#40 AB2 C10
+1.05V H_D#_40 H_DBSY# H_DBSY# (3)
H_D#41 AD7 AM5
H_D#_41 HPLL_CLK CLK_MCH_BCLK (2)
H_D#42 AB1 AM7
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# (2)
H_D#43 Y3 H8
H_D#_43 H_DPWR# H_DPWR# (3)
H_D#44 AC6 K7
H_D#_44 H_DRDY# H_DRDY# (3)
H_D#45 AE2 E4
H_D#_45 H_HIT# H_HIT# (3)
R97 H_D#46 AC5 C6
H_D#_46 H_HITM# H_HITM# (3)
H_D#47 AG3 G10
Impedance 55ohm H_D#_47 H_LOCK# H_LOCK# (3)
54.9/F_4 H_D#48 AJ9 B7
H_D#_48 H_TRDY# H_TRDY# (3)
H_D#49 AH8
H_SCOMP H_D#50 H_D#_49
AJ14
H_D#51 H_D#_50
AE9
H_D#52 H_D#_51
AE11 H_DINV#[3:0] (3)
H_D#53 H_D#_52 H_DINV#0
AH12 K5
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1
AJ5 L2
H_D#55 H_D#_54 H_DINV#_1 H_DINV#2
B AH5 AD13 B
+1.05V H_D#56 H_D#_55 H_DINV#_2 H_DINV#3
AJ6 AE13
H_D#57 H_D#_56 H_DINV#_3
AE7 H_DSTBN#[3:0] (3)
H_D#58 H_D#_57 H_DSTBN#0
AJ7 M7
H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1
AJ2 K3
H_D#60 H_D#_59 H_DSTBN#_1 H_DSTBN#2
AE5 AD2
R98 H_D#61 H_D#_60 H_DSTBN#_2 H_DSTBN#3
AJ3 AH11
Impedance 55ohm H_D#62 H_D#_61 H_DSTBN#_3
AH2 H_DSTBP#[3:0] (3)
54.9/F_4 H_D#63 H_D#_62 H_DSTBP#0
AH13 L7
H_D#_63 H_DSTBP#_0 H_DSTBP#1
K2
H_SCOMP# H_DSTBP#_1 H_DSTBP#2
AC2
H_SWING H_DSTBP#_2 H_DSTBP#3
B3 AJ10
H_RCOMP H_SWING H_DSTBP#_3
C2 H_REQ#[4:0] (3)
+1.05V H_RCOMP H_REQ#0
M14
H_SCOMP H_REQ#_0 H_REQ#1
W1 E13
H_SCOMP# H_SCOMP H_REQ#_1 H_REQ#2
W2 A11
H_SCOMP# H_REQ#_2 H_REQ#3
H13
H_REQ#_3 H_REQ#4
(3) H_CPURST# B6 B12
R413 H_CPURST# H_REQ#_4
(3) H_CPUSLP# E5 H_RS#[2:0] (3)
H_CPUSLP# H_RS#0
E12
1K/F_4 H_RS#_0 H_RS#1
D7
H_RS#_1 H_RS#2
D8
H_AVREF H_RS#_2
B9
H_AVREF
A9
0.1U close to B9,L<100mils H_DVREF
A A
R412 C406 CRESTLINE_1p0

2K/F_4 0.1u/10V_4
965GM : AJSLA5T0T20
Quanta Computer Inc.
965PM : AJSLA5U0T25
PROJECT : TE1
960GML : AJSLA5V0T09 Size Document Number Rev
GMCH HOST(1 of 7) 1A

Date: Thursday, September 20, 2007 Sheet 5 of 38


5 4 3 2 1

PROJECT : ZU
Quanta Compu

www.vinafix.vn
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5 4 3 2 1

(19) INT_LVDS_PWM
U29B
(19) INT_LVDS_BLON +VCC_PEG
+3V R147 IV@10K_4
P36 U29C
RSVD1 R170 EV@0_4
P37 AV29 M_CLK_DDR0 (13)
RSVD2 SM_CK_0
R35 BB23 M_CLK_DDR1 (13) J40
RSVD3 SM_CK_1 R145 EV@0_4 L_BKLT_CTRL
N35 BA25 M_CLK_DDR3 (13) H39 N43 EXP_A_COMPX R173 24.9/F_4
RSVD4 SM_CK_3 L_CTRL_CLK L_BKLT_EN PEG_COMPI
AR12 AV23 M_CLK_DDR4 (13) E39 M43
RSVD5 SM_CK_4 R161 IV@10K_4 L_CTRL_DATA L_CTRL_CLK PEG_COMPO
AR13 +3V E40
RSVD6 L_CTRL_DATA
AM12 AW30 M_CLK_DDR#0 (13) (19) INT_LVDS_EDIDCLK C37
RSVD7 SM_CK#_0 L_DDC_CLK
AN13 BA23 M_CLK_DDR#1 (13) (19) INT_LVDS_EDIDDATA D35 J51 PEG_RXN0 (18)
RSVD8 SM_CK#_1 L_DDC_DATA PEG_RX#_0
J12 AW25 M_CLK_DDR#3 (13) (19) INT_LVDS_DIGON K40 L51 PEG_RXN1 (18,21)
RSVD9 SM_CK#_3 L_VDD_EN PEG_RX#_1

RSVD
AR37 AW23 M_CLK_DDR#4 (13) N47 PEG_RXN2 (18)
RSVD10 SM_CK#_4 R175 IV@2.4K/F_4 LVDS_IBG PEG_RX#_2
AM36 L41 T45 PEG_RXN3 (18)
RSVD11 LVDS_IBG PEG_RX#_3
AL36 BE29 M_CKE0 (12,13) T31 L43 T50 PEG_RXN4 (18)
RSVD12 SM_CKE_0 R177 IV@0_4 LVDS_VBG PEG_RX#_4
AM37 AY32 M_CKE1 (12,13) N41 U40 PEG_RXN5 (18)
D RSVD13 SM_CKE_1 LVDS_VREFH PEG_RX#_5 D
D20 BD39 M_CKE3 (12,13) N40 Y44 PEG_RXN6 (18)
RSVD14 SM_CKE_3 LVDS_VREFL PEG_RX#_6
BG37 M_CKE4 (12,13) (19) INT_TXLCLKOUT- D46 Y40 PEG_RXN7 (18)
SM_CKE_4 LVDSA_CLK# PEG_RX#_7
(19) INT_TXLCLKOUT+ C45 AB51 PEG_RXN8 (18)
LVDSA_CLK PEG_RX#_8
BG20 M_CS#0 (12,13) T29 D44 W49 PEG_RXN9 (18)
SM_CS#_0 LVDSB_CLK# PEG_RX#_9
BK16 M_CS#1 (12,13) T30 E42 AD44 PEG_RXN10 (18)
SM_CS#_1 LVDSB_CLK PEG_RX#_10

LVDS
BG16 M_CS#2 (12,13) AD40 PEG_RXN11 (18)
SM_CS#_2 PEG_RX#_11
H10 BE13 M_CS#3 (12,13) (19) INT_TXLOUT0- G51 AG46 PEG_RXN12 (18)
RSVD20 SM_CS#_3 LVDSA_DATA#_0 PEG_RX#_12
B51 (19) INT_TXLOUT1- E51 AH49 PEG_RXN13 (18)
RSVD21 LVDSA_DATA#_1 PEG_RX#_13

MUXING
BJ20 BH18 M_ODT0 (12,13) (19) INT_TXLOUT2- F49 AG45 PEG_RXN14 (18)
RSVD22 SM_ODT_0 LVDSA_DATA#_2 PEG_RX#_14
BK22 BJ15 M_ODT1 (12,13) AG41 PEG_RXN15 (18)
RSVD23 SM_ODT_1 PEG_RX#_15

GRAPHICS
BF19 BJ14 M_ODT2 (12,13)
RSVD24 SM_ODT_2
BH20 BE16 M_ODT3 (12,13) (19) INT_TXLOUT0+ G50 J50 PEG_RXP0 (18)
RSVD25 SM_ODT_3 LVDSA_DATA_0 PEG_RX_0
BK18 (19) INT_TXLOUT1+ E50 L50 PEG_RXP1 (18,21)
RSVD26 M_RCOMP LVDSA_DATA_1 PEG_RX_1
BJ18 BL15 (19) INT_TXLOUT2+ F48 M47 PEG_RXP2 (18)
RSVD27 SM_RCOMP M_RCOMP# LVDSA_DATA_2 PEG_RX_2
BF23 BK14 U44 PEG_RXP3 (18)
RSVD28 SM_RCOMP# PEG_RX_3
BG23 T49 PEG_RXP4 (18)
RSVD29 SM_RCOMP_VOH PEG_RX_4
BC23 BK31 T28 G44 T41 PEG_RXP5 (18)
RSVD30 SM_RCOMP_VOH SM_RCOMP_VOL LVDSB_DATA#_0 PEG_RX_5
BD24 BL31 T34 B47 W45 PEG_RXP6 (18)

DDR
RSVD31 SM_RCOMP_VOL LVDSB_DATA#_1 PEG_RX_6
(12,13) M_A_A14 BJ29 T32 B45 W41 PEG_RXP7 (18)
RSVD32 SMDDR_VREF_MCH R93 0_6 LVDSB_DATA#_2 PEG_RX_7
(12,13) M_B_A14 BE24 AR49 +SMDDR_VREF AB50 PEG_RXP8 (18)
RSVD33 SM_VREF_0 PEG_RX_8
BH39 AW4 Y48 PEG_RXP9 (18)
RSVD34 SM_VREF_1 R96 *10K_6 PEG_RX_9
AW20 +1.8VSUS T27 E44 AC45 PEG_RXP10 (18)
RSVD35 R100 *10K_6 LVDSB_DATA_0 PEG_RX_10
BK20 T35 A47 AC41 PEG_RXP11 (18)
RSVD36 LVDSB_DATA_1 PEG_RX_11
C48 T33 A45 AH47 PEG_RXP12 (18)
RSVD37 DREFCLK LVDSB_DATA_2 PEG_RX_12

PCI-EXPRESS
D47 B42 DREFCLK (2) AG49 PEG_RXP13 (18)
RSVD38 DPLL_REF_CLK DREFCLK# PEG_RX_13
B44 C42 DREFCLK# (2) AH45 PEG_RXP14 (18)
RSVD39 DPLL_REF_CLK# DREFSSCLK PEG_RX_14
C44 H48 DREFSSCLK (2) AG42 PEG_RXP15 (18)
RSVD40 DPLL_REF_SSCLK DREFSSCLK# PEG_RX_15
A35 H47 DREFSSCLK# (2)
RSVD41 DPLL_REF_SSCLK# R127 IV@75_4 NB_TVA C_PEG_TXN0 C526 EV@0.1u/10V_4 PEG_TXN0
B37 E27 N45 PEG_TXN0 (18)
RSVD42 R124 IV@75_4 NB_TVB TVA_DAC PEG_TX#_0 C_PEG_TXN1 C524 EV@0.1u/10V_4 PEG_TXN1
B36 K44 CLK_PCIE_3GPLL (2) G27 U39 PEG_TXN1 (18)
RSVD43 PEG_CLK TVB_DAC PEG_TX#_1

CLK
B34 K45 R105 IV@75_4 NB_TVC K27 U47 C_PEG_TXN2 C522 EV@0.1u/10V_4 PEG_TXN2
RSVD44 PEG_CLK# CLK_PCIE_3GPLL# (2) TVC_DAC PEG_TX#_2 PEG_TXN2 (18)

TV
C34 N51 C_PEG_TXN3 C520 EV@0.1u/10V_4 PEG_TXN3
C RSVD45 PEG_TX#_3 PEG_TXN3 (18) C
For EV@ For IV@ F27 R50 C_PEG_TXN4 C487 EV@0.1u/10V_4 PEG_TXN4
DMI_TXN[3:0] (15) TV A/B/C TV A/B/C TVA_RTN PEG_TX#_4 PEG_TXN4 (18)
J27 T42 C_PEG_TXN5 C511 EV@0.1u/10V_4 PEG_TXN5
use 0 ohm R use 75 ohm R TVB_RTN PEG_TX#_5 PEG_TXN5 (18)
AN47 DMI_TXN0 L27 Y43 C_PEG_TXN6 C499 EV@0.1u/10V_4 PEG_TXN6
PEG_TXN6 (18)
DMI_RXN_0 TVC_RTN PEG_TX#_6
AJ38 DMI_TXN1 W46 C_PEG_TXN7 C489 EV@0.1u/10V_4 PEG_TXN7
PEG_TXN7 (18)
DMI_RXN_1 R159 0_4 PEG_TX#_7 C479 EV@0.1u/10V_4
AN42 DMI_TXN2 NB_TV_DCONSEL_0 M35 W38 C_PEG_TXN8 PEG_TXN8
PEG_TXN8 (18)
DMI_RXN_2 TV_DCONSEL_0 PEG_TX#_8
AN46 DMI_TXN3 DMI_TXP[3:0] (15)
R169 0_4 NB_TV_DCONSEL_1 P33 AD39 C_PEG_TXN9 C483 EV@0.1u/10V_4 PEG_TXN9
PEG_TXN9 (18)
DMI_RXN_3 TV_DCONSEL_1 PEG_TX#_9 C_PEG_TXN10 C493 EV@0.1u/10V_4 PEG_TXN10
AC46 PEG_TXN10 (18)
PEG_TX#_10
AM47 DMI_TXP0 AC49 C_PEG_TXN11 C515 EV@0.1u/10V_4 PEG_TXN11
PEG_TXN11 (18)
DMI_RXP_0 PEG_TX#_11
(2) MCH_BSEL0 P27 AJ39 DMI_TXP1 AC42 C_PEG_TXN12 C497 EV@0.1u/10V_4 PEG_TXN12
PEG_TXN12 (18)
CFG_0 DMI_RXP_1 PEG_TX#_12 C513 EV@0.1u/10V_4
(2) MCH_BSEL1 N27 AN41 DMI_TXP2 AH39 C_PEG_TXN13 PEG_TXN13
PEG_TXN13 (18)
CFG_1 DMI_RXP_2 PEG_TX#_13
(2) MCH_BSEL2 N24 AN45 DMI_TXP3 DMI_RXN[3:0] (15) AE49 C_PEG_TXN14 C495 EV@0.1u/10V_4 PEG_TXN14
PEG_TXN14 (18)
MCH_CFG_3 CFG_2 DMI_RXP_3 PEG_TX#_14 C_PEG_TXN15 C517 EV@0.1u/10V_4 PEG_TXN15
T19 C21 AH44 PEG_TXN15 (18)
MCH_CFG_4 CFG_3 PEG_TX#_15
T25 C23 AJ46 DMI_RXN0
CFG_4 DMI_TXN_0
(11) MCH_CFG_5 F23 AJ41 DMI_RXN1 (20) INT_CRT_BLU
INT_CRT_BLU H32 M45 C_PEG_TXP0 C527 EV@0.1u/10V_4 PEG_TXP0
PEG_TXP0 (18)
MCH_CFG_6 CFG_5 DMI_TXN_1 CRT_BLUE PEG_TX_0 C525 EV@0.1u/10V_4
T17 N23 AM40 DMI_RXN2 G32 T38 C_PEG_TXP1 PEG_TXP1
PEG_TXP1 (18)
MCH_CFG_7 CFG_6 DMI_TXN_2 CRT_BLUE# PEG_TX_1
T21 G23 AM44 DMI_RXN3 DMI_RXP[3:0] (15) (20) INT_CRT_GRN
INT_CRT_GRN K29 T46 C_PEG_TXP2 C523 EV@0.1u/10V_4 PEG_TXP2
PEG_TXP2 (18)
MCH_CFG_8 CFG_7 DMI_TXN_3 CRT_GREEN PEG_TX_2 C_PEG_TXP3 C521 EV@0.1u/10V_4 PEG_TXP3
T16 J20 J29 N50 PEG_TXP3 (18)
DMI

CFG_8 CRT_GREEN# PEG_TX_3


CFG

(11) MCH_CFG_9 C20 AJ47 DMI_RXP0 (20) INT_CRT_RED


INT_CRT_RED F29 R51 C_PEG_TXP4 C488 EV@0.1u/10V_4 PEG_TXP4
PEG_TXP4 (18)
CFG_9 DMI_TXP_0 CRT_RED PEG_TX_4

VGA
MCH_CFG_10 R24 AJ42 DMI_RXP1 E29 U43 C_PEG_TXP5 C512 EV@0.1u/10V_4 PEG_TXP5
T20 CFG_10 DMI_TXP_1 CRT_RED# PEG_TX_5 PEG_TXP5 (18)
MCH_CFG_11 L23 AM39 DMI_RXP2 W42 C_PEG_TXP6 C500 EV@0.1u/10V_4 PEG_TXP6
T23 CFG_11 DMI_TXP_2 PEG_TX_6 PEG_TXP6 (18)
(11) MCH_CFG_12 J23 AM43 DMI_RXP3 Y47 C_PEG_TXP7 C490 EV@0.1u/10V_4 PEG_TXP7
PEG_TXP7 (18)
CFG_12 DMI_TXP_3 INT_CRT_DDCCLK PEG_TX_7 C_PEG_TXP8 C480 EV@0.1u/10V_4 PEG_TXP8
(11) MCH_CFG_13 E23 (20) INT_CRT_DDCCLK K33 Y39 PEG_TXP8 (18)
MCH_CFG_14 CFG_13 INT_CRT_DDCDAT CRT_DDC_CLK PEG_TX_8 C_PEG_TXP9 C484 EV@0.1u/10V_4 PEG_TXP9
T15 E20 (20) INT_CRT_DDCDAT G35 AC38 PEG_TXP9 (18)
MCH_CFG_15 CFG_14 R149 IV@30/F_4 HSYNC_A CRT_DDC_DATA PEG_TX_9 C_PEG_TXP10 C494 EV@0.1u/10V_4 PEG_TXP10
T22 K23 (20) INT_HSYNC F33 AD47 PEG_TXP10 (18)
CFG_15 CRTIREF CRT_HSYNC PEG_TX_10 C_PEG_TXP11 C516 EV@0.1u/10V_4 PEG_TXP11
(11) MCH_CFG_16 M20 C32 AC50 PEG_TXP11 (18)
MCH_CFG_17 CFG_16 R154 IV@30/F_4 VSYNC_A CRT_TVO_IREF PEG_TX_11 C_PEG_TXP12 C498 EV@0.1u/10V_4 PEG_TXP12
T18 M24 (20) INT_VSYNC E33 AD43 PEG_TXP12 (18)
MCH_CFG_18 CFG_17 CRT_VSYNC PEG_TX_12 C_PEG_TXP13 C514 EV@0.1u/10V_4 PEG_TXP13
GRAPHICS VID

T26 L32 AG39 PEG_TXP13 (18)


CFG_18 PEG_TX_13 C_PEG_TXP14 C496 EV@0.1u/10V_4 PEG_TXP14
(11) MCH_CFG_19 N33 AE50 PEG_TXP14 (18)
CFG_19 PEG_TX_14 C_PEG_TXP15 C518 EV@0.1u/10V_4 PEG_TXP15
(11) MCH_CFG_20 L35 AH43 PEG_TXP15 (18)
CFG_20 PEG_TX_15

E35 CRESTLINE_1p0
B GFX_VID_0 B
(16) PM_BMBUSY# G41 A39
PM_BM_BUSY# GFX_VID_1
(3,14,33) ICH_DPRSTP# L39 C38
PM_EXTTS#0 PM_DPRSTP# GFX_VID_2
(13) PM_EXTTS#0 L36 B39
PM_EXT_TS#_0 GFX_VID_3
PM

(13) PM_EXTTS#1 PM_EXTTS#1 J36 E36


PM_EXT_TS#_1 GFX_VR_EN C_PEG_TXP0 C510 IV@0.1u/10V_4
(3,16,33) DELAY_VR_PWRGOOD AW49 SDVOB_RED+ (21)
R117 100_4 RST_IN#_MCH PWROK C_PEG_TXN0 C507 IV@0.1u/10V_4
(15) PLTRST#_NB AV20 SDVOB_RED- (21)
R113 *0_4 PM_THRMTRIP#_GMCH RSTIN# +1.25V_AXD C_PEG_TXP1 C506 IV@0.1u/10V_4
(3,14) PM_THRMTRIP# N20 SDVOB_GREEN+ (21)
THERMTRIP# For EV@ For IV@ C_PEG_TXN1 C505 IV@0.1u/10V_4
(16,33) PM_DPRSLPVR G36 SDVOB_GREEN- (21)
DPRSLPVR CRT R/G/B CRT R/G/B C_PEG_TXP2 C504 IV@0.1u/10V_4 SDVOB_BLUE+ (21)
AM49 R190 use 0 ohm R use 150 ohm R C_PEG_TXN2 C503 IV@0.1u/10V_4
CL_CLK CL_CLK0 (16) SDVOB_BLUE- (21)
AK50 C_PEG_TXP3 C502 IV@0.1u/10V_4 SDVOB_CLK+ (21)
CL_DATA CL_DATA0 (16)
BJ51 AT43 1K/F_4 C_PEG_TXN3 C501 IV@0.1u/10V_4 SDVOB_CLK- (21)
NC_1 CL_PWROK MPWROK (16)
BK51 AN49 R132 IV@150/F_4 INT_CRT_BLU
ME

NC_2 CL_RST# CL_RST#0 (16)


BK50 AM50 +1.25V_CL_VREF
NC_3 CL_VREF R133 IV@150/F_4 INT_CRT_GRN
BL50
NC_4
BL49
NC_5 C210 R192 R131 IV@150/F_4 INT_CRT_RED
BL3
NC_6
BL2
NC_7
NC

BK1 0.1u/10V_4 392/F_6


NC_8 R137 IV@1.3K_4 CRTIREF
BJ1 H35 SDVO_CTRLCLK (21)
NC_9 SDVO_CTRL_CLK
E1 K36
MISC

NC_10 SDVO_CTRL_DATA SDVO_CTRLDATA (21)


A5 G39 CLK_MCH_OE# CLK_MCH_OE# (2)
For IV@ USE 1.3K ohm R R150 EV@0_4 HSYNC_A
NC_11 CLK_REQ# For EV@ USE 0 ohm R
C51 G40 MCH_ICH_SYNC# (16)
NC_12 ICH_SYNC# R156 EV@0_4 VSYNC_A
B50
NC_13
A50
NC_14
A49 A37 GMCH_TEST1 R166 0_4 R158 EV@0_4 INT_CRT_DDCCLK
NC_15 TEST_1
BK2 R32 GMCH_TEST2 R152 20K_4
NC_16 TEST_2 R157 EV@0_4 INT_CRT_DDCDAT
CRESTLINE_1p0
+1.8VSUS R422 1K/F_4 SM_RCOMP_VOH RP30 3 4 EV@0X2 DREFCLK
1 2 DREFCLK#

A R423 C431 C428 RP39 A


1 2 EV@0X2 DREFSSCLK
3 4 DREFSSCLK#
3.01K/F_4 0.01u/16V_4 2.2u/6.3V_6
M_RCOMP# +1.8VSUS +3V

R415 SM_RCOMP_VOL
R417 R163 10K_4 CLK_MCH_OE#
20/F_4
20/F_4 R162 10K_4 PM_EXTTS#0
Quanta Computer Inc.
R421 C425 C419
M_RCOMP R146 10K_4 PM_EXTTS#1 PROJECT : TE1
1K/F_4 0.01u/16V_4 2.2u/6.3V_6 Size Document Number Rev
1A
GMCH DMI/VIDEO(2 of 7)
Date: Thursday, September 20, 2007 Sheet 6 of 38
5 4 3 2 1

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NB(Memory controller)

(13) M_A_DQ[63:0] (13) M_B_DQ[63:0]


U29D U29E
D M_A_DQ0 AR43 BB19 M_B_DQ0 AP49 AY17 D
M_A_DQ1 SA_DQ_0 SA_BS_0 M_A_BS#0 (12,13) M_B_DQ1 SB_DQ_0 SB_BS_0 M_B_BS#0 (12,13)
AW44 BK19 M_A_BS#1 (12,13) AR51 BG18 M_B_BS#1 (12,13)
M_A_DQ2 SA_DQ_1 SA_BS_1 M_B_DQ2 SB_DQ_1 SB_BS_1
BA45 BF29 M_A_BS#2 (12,13) AW50 BG36 M_B_BS#2 (12,13)
M_A_DQ3 SA_DQ_2 SA_BS_2 M_B_DQ3 SB_DQ_2 SB_BS_2
AY46 M_A_CAS# (12,13) AW51 M_B_CAS# (12,13)
M_A_DQ4 SA_DQ_3 M_B_DQ4 SB_DQ_3
AR41 BL17 AN51 BE17
M_A_DQ5 SA_DQ_4 SA_CAS# M_B_DQ5 SB_DQ_4 SB_CAS#
AR45 M_A_DM[7:0] (13) AN50 M_B_DM[7:0] (13)
M_A_DQ6 SA_DQ_5 M_A_DM0 M_B_DQ6 SB_DQ_5 M_B_DM0
AT42 AT45 AV50 AR50
M_A_DQ7 SA_DQ_6 SA_DM_0 M_A_DM1 M_B_DQ7 SB_DQ_6 SB_DM_0 M_B_DM1
AW47 BD44 AV49 BD49
M_A_DQ8 SA_DQ_7 SA_DM_1 M_A_DM2 M_B_DQ8 SB_DQ_7 SB_DM_1 M_B_DM2
BB45 BD42 BA50 BK45
M_A_DQ9 SA_DQ_8 SA_DM_2 M_A_DM3 M_B_DQ9 SB_DQ_8 SB_DM_2 M_B_DM3
BF48 AW38 BB50 BL39
M_A_DQ10 SA_DQ_9 SA_DM_3 M_A_DM4 M_B_DQ10 SB_DQ_9 SB_DM_3 M_B_DM4
BG47 AW13 BA49 BH12
M_A_DQ11 SA_DQ_10 SA_DM_4 M_A_DM5 M_B_DQ11 SB_DQ_10 SB_DM_4 M_B_DM5
BJ45 BG8 BE50 BJ7
M_A_DQ12 SA_DQ_11 SA_DM_5 M_A_DM6 M_B_DQ12 SB_DQ_11 SB_DM_5 M_B_DM6
BB47 AY5 BA51 BF3
M_A_DQ13 SA_DQ_12 SA_DM_6 M_A_DM7 M_B_DQ13 SB_DQ_12 SB_DM_6 M_B_DM7
BG50 AN6 AY49 AW2
M_A_DQ14 SA_DQ_13 SA_DM_7 M_B_DQ14 SB_DQ_13 SB_DM_7
BH49 M_A_DQS[7:0] (13) BF50 M_B_DQS[7:0] (13)
M_A_DQ15 SA_DQ_14 M_A_DQS0 M_B_DQ15 SB_DQ_14 M_B_DQS0
BE45 AT46 BF49 AT50

A
SA_DQ_15 SA_DQS_0 SB_DQ_15 SB_DQS_0

B
M_A_DQ16 AW43 BE48 M_A_DQS1 M_B_DQ16 BJ50 BD50 M_B_DQS1
M_A_DQ17 SA_DQ_16 SA_DQS_1 M_A_DQS2 M_B_DQ17 SB_DQ_16 SB_DQS_1 M_B_DQS2
BE44 BB43 BJ44 BK46
M_A_DQ18 SA_DQ_17 SA_DQS_2 M_A_DQS3 M_B_DQ18 SB_DQ_17 SB_DQS_2 M_B_DQS3
BG42 BC37 BJ43 BK39
M_A_DQ19 SA_DQ_18 SA_DQS_3 M_A_DQS4 M_B_DQ19 SB_DQ_18 SB_DQS_3 M_B_DQS4
BE40 BB16 BL43 BJ12
M_A_DQ20 SA_DQ_19 SA_DQS_4 M_A_DQS5 M_B_DQ20 SB_DQ_19 SB_DQS_4 M_B_DQS5
BF44 BH6 BK47 BL7

MEMORY

MEMORY
M_A_DQ21 SA_DQ_20 SA_DQS_5 M_A_DQS6 M_B_DQ21 SB_DQ_20 SB_DQS_5 M_B_DQS6
BH45 BB2 BK49 BE2
M_A_DQ22 SA_DQ_21 SA_DQS_6 M_A_DQS7 M_B_DQ22 SB_DQ_21 SB_DQS_6 M_B_DQS7
BG40 AP3 M_A_DQS#[7:0] (13) BK43 AV2 M_B_DQS#[7:0] (13)
M_A_DQ23 SA_DQ_22 SA_DQS_7 M_A_DQS#0 M_B_DQ23 SB_DQ_22 SB_DQS_7 M_B_DQS#0
BF40 AT47 BK42 AU50
M_A_DQ24 SA_DQ_23 SA_DQS#_0 M_A_DQS#1 M_B_DQ24 SB_DQ_23 SB_DQS#_0 M_B_DQS#1
AR40 BD47 BJ41 BC50
C
M_A_DQ25 SA_DQ_24 SA_DQS#_1 M_A_DQS#2 M_B_DQ25 SB_DQ_24 SB_DQS#_1 M_B_DQS#2 C
AW40 BC41 BL41 BL45
M_A_DQ26 SA_DQ_25 SA_DQS#_2 M_A_DQS#3 M_B_DQ26 SB_DQ_25 SB_DQS#_2 M_B_DQS#3
AT39 BA37 BJ37 BK38
M_A_DQ27 SA_DQ_26 SA_DQS#_3 M_A_DQS#4 M_B_DQ27 SB_DQ_26 SB_DQS#_3 M_B_DQS#4
AW36 BA16 BJ36 BK12
M_A_DQ28 SA_DQ_27 SA_DQS#_4 M_A_DQS#5 M_B_DQ28 SB_DQ_27 SB_DQS#_4 M_B_DQS#5
AW41 BH7 BK41 BK7
M_A_DQ29 SA_DQ_28 SA_DQS#_5 M_A_DQS#6 M_B_DQ29 SB_DQ_28 SB_DQS#_5 M_B_DQS#6
AY41 BC1 BJ40 BF2
M_A_DQ30 SA_DQ_29 SA_DQS#_6 M_A_DQS#7 M_B_DQ30 SB_DQ_29 SB_DQS#_6 M_B_DQS#7
AV38 AP2 BL35 AV3
M_A_DQ31 SA_DQ_30 SA_DQS#_7 M_B_DQ31 SB_DQ_30 SB_DQS#_7
AT38 M_A_A[13:0] (12,13) BK37 M_B_A[13:0] (12,13)
M_A_DQ32 SA_DQ_31 M_A_A0 M_B_DQ32 SB_DQ_31 M_B_A0
AV13 BJ19 BK13 BC18
M_A_DQ33 SA_DQ_32 SA_MA_0 M_A_A1 M_B_DQ33 SB_DQ_32 SB_MA_0 M_B_A1
SYSTEM

AT13 BD20 BE11 BG28


SA_DQ_33 SA_MA_1 SB_DQ_33 SB_MA_1

SYSTEM
M_A_DQ34 AW11 BK27 M_A_A2 M_B_DQ34 BK11 BG25 M_B_A2
M_A_DQ35 SA_DQ_34 SA_MA_2 M_A_A3 M_B_DQ35 SB_DQ_34 SB_MA_2 M_B_A3
AV11 BH28 BC11 AW17
M_A_DQ36 SA_DQ_35 SA_MA_3 M_A_A4 M_B_DQ36 SB_DQ_35 SB_MA_3 M_B_A4
AU15 BL24 BC13 BF25
M_A_DQ37 SA_DQ_36 SA_MA_4 M_A_A5 M_B_DQ37 SB_DQ_36 SB_MA_4 M_B_A5
AT11 BK28 BE12 BE25
M_A_DQ38 SA_DQ_37 SA_MA_5 M_A_A6 M_B_DQ38 SB_DQ_37 SB_MA_5 M_B_A6
BA13 BJ27 BC12 BA29
M_A_DQ39 SA_DQ_38 SA_MA_6 M_A_A7 M_B_DQ39 SB_DQ_38 SB_MA_6 M_B_A7
BA11 BJ25 BG12 BC28
M_A_DQ40 SA_DQ_39 SA_MA_7 M_A_A8 M_B_DQ40 SB_DQ_39 SB_MA_7 M_B_A8
BE10 BL28 BJ10 AY28
M_A_DQ41 SA_DQ_40 SA_MA_8 M_A_A9 M_B_DQ41 SB_DQ_40 SB_MA_8 M_B_A9
BD10 BA28 BL9 BD37
M_A_DQ42 SA_DQ_41 SA_MA_9 M_A_A10 M_B_DQ42 SB_DQ_41 SB_MA_9 M_B_A10
BD8 BC19 BK5 BG17
M_A_DQ43 SA_DQ_42 SA_MA_10 M_A_A11 M_B_DQ43 SB_DQ_42 SB_MA_10 M_B_A11
AY9 BE28 BL5 BE37
M_A_DQ44 SA_DQ_43 SA_MA_11 M_A_A12 M_B_DQ44 SB_DQ_43 SB_MA_11 M_B_A12
BG10 BG30 BK9 BA39
M_A_DQ45 SA_DQ_44 SA_MA_12 M_A_A13 M_B_DQ45 SB_DQ_44 SB_MA_12 M_B_A13
AW9 BJ16 BK10 BG13
SA_DQ_45 SA_MA_13 SB_DQ_45 SB_MA_13
DDR

M_A_DQ46 BD7 M_B_DQ46 BJ8


SA_DQ_46 SB_DQ_46

DDR
M_A_DQ47 BB9 M_B_DQ47 BJ6 AV16
M_A_DQ48 SA_DQ_47 M_B_DQ48 SB_DQ_47 SB_RAS# TP_SB_RCVEN# M_B_RAS# (12,13)
BB5 BE18 M_A_RAS# (12,13) BF4 AY18 T14
M_A_DQ49 SA_DQ_48 SA_RAS# TP_SA_RCVEN# M_B_DQ49 SB_DQ_48 SB_RCVEN#
B AY7 AY20 T24 BH5 B
M_A_DQ50 SA_DQ_49 SA_RCVEN# M_B_DQ50 SB_DQ_49
AT5 BG1 BC17 M_B_WE# (12,13)
M_A_DQ51 SA_DQ_50 M_B_DQ51 SB_DQ_50 SB_WE#
AT7 BA19 M_A_WE# (12,13) BC2
M_A_DQ52 SA_DQ_51 SA_WE# M_B_DQ52 SB_DQ_51
AY6 BK3
M_A_DQ53 SA_DQ_52 M_B_DQ53 SB_DQ_52
BB7 BE4
M_A_DQ54 SA_DQ_53 M_B_DQ54 SB_DQ_53
AR5 BD3
M_A_DQ55 SA_DQ_54 M_B_DQ55 SB_DQ_54
AR8 BJ2
M_A_DQ56 SA_DQ_55 M_B_DQ56 SB_DQ_55
AR9 BA3
M_A_DQ57 SA_DQ_56 M_B_DQ57 SB_DQ_56
AN3 BB3
M_A_DQ58 SA_DQ_57 M_B_DQ58 SB_DQ_57
AM8 AR1
M_A_DQ59 SA_DQ_58 M_B_DQ59 SB_DQ_58
AN10 AT3
M_A_DQ60 SA_DQ_59 M_B_DQ60 SB_DQ_59
AT9 AY2
M_A_DQ61 SA_DQ_60 M_B_DQ61 SB_DQ_60
AN9 AY3
M_A_DQ62 SA_DQ_61 M_B_DQ62 SB_DQ_61
AM9 AU2
M_A_DQ63 SA_DQ_62 M_B_DQ63 SB_DQ_62
AN11 AT2
SA_DQ_63 SB_DQ_63
CRESTLINE_1p0 CRESTLINE_1p0

A A

Quanta Computer Inc.


PROJECT : TE1
Size Document Number Rev
MCH DDR(3 of 7) 1A

Date: Thursday, September 20, 2007 Sheet 7 of 38


5 4 3 2 1

PROJECT : ZU1
Quanta Computer Inc.

www.vinafix.vn
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NB(Power-1)
+1.05V
GM:1572.62mA
U29G +1.05_VCC_AXG_NCTF
PM:1310mA
AT35 U29F
VCC_1
AT34 T17
VCC_2 VCC_AXG_NCTF_1
AH28 T18 +1.05V AB33
VCC_3 VCC_AXG_NCTF_2 VCC_NCTF_1
AC32 T19 AB36
VCC_5 VCC_AXG_NCTF_3 VCC_NCTF_2
AC31 T21 AB37
D VCC_4 VCC_AXG_NCTF_4 + C403 C149 C115 C140 C137 VCC_NCTF_3 D
AK32 T22 AC33 T27
VCC_6 VCC_AXG_NCTF_5 VCC_NCTF_4 VSS_NCTF_1
AJ31 T23 AC35 T37
VCC_7 VCC_AXG_NCTF_6 *330u/2.5V_3528 10u/10V_8 0.22u/6.3V_4 0.22u/6.3V_4 0.1u/10V_4 VCC_NCTF_5 VSS_NCTF_2
AJ28 T25 AC36 U24
VCC_8 VCC_AXG_NCTF_7 VCC_NCTF_6 VSS_NCTF_3
AH32 U15 AD35 U28
VCC_9 VCC_AXG_NCTF_8 VCC_NCTF_7 VSS_NCTF_4
AH31 U16 AD36 V31

VCC CORE
VCC_10 VCC_AXG_NCTF_9 VCC_NCTF_8 VSS_NCTF_5
AH29 U17 AF33 V35
VCC_11 VCC_AXG_NCTF_10 VCC_NCTF_9 VSS_NCTF_6
AF32 U19 AF36 AA19
VCC_12 VCC_AXG_NCTF_11 VCC_NCTF_10 VSS_NCTF_7
U20 AH33 AB17
VCC_AXG_NCTF_12 VCC_NCTF_11 VSS_NCTF_8
U21 AH35 AB35

VSS NCTF
VCC_AXG_NCTF_13 VCC_NCTF_12 VSS_NCTF_9
U23 AH36 AD19
VCC_AXG_NCTF_14 VCC_NCTF_13 VSS_NCTF_10
R30 U26 AH37 AD37
VCC_13 VCC_AXG_NCTF_15 VCC_NCTF_14 VSS_NCTF_11
V16 AJ33 AF17
VCC_AXG_NCTF_16 +1.05V VCC_NCTF_15 VSS_NCTF_12
V17 AJ35 AF35
VCC_AXG_NCTF_17 VCC_NCTF_16 VSS_NCTF_13
V19 AK33 AK17
VCC_AXG_NCTF_18 VCC_NCTF_17 VSS_NCTF_14
V20 AK35 AM17
VCC_AXG_NCTF_19 VCC_NCTF_18 VSS_NCTF_15
V21 AK36 AM24
VCC_AXG_NCTF_20 VCC_NCTF_19 VSS_NCTF_16
V23 AK37 AP26
VCC_AXG_NCTF_21 VCC_NCTF_20 VSS_NCTF_17
V24 AD33 AP28
+1.8VSUS VCC_AXG_NCTF_22 VCC_NCTF_21 VSS_NCTF_18
533MHz:2700mA Y15 R107 R130 R138 AJ36 AR15
667MHz:3300mA POWER VCC_AXG_NCTF_23
Y16 +1.05_VCC_AXG_NCTF AM35
VCC_NCTF_22 VSS_NCTF_19
AR19

VCC NCTF
VCC_AXG_NCTF_24 IV@0_8 IV@0_8 IV@0_8 VCC_NCTF_23 VSS_NCTF_20
Y17 AL33 AR28
VCC_AXG_NCTF_25 VCC_NCTF_24 VSS_NCTF_21
AU32 Y19 AL35
VCC_SM_1 VCC_AXG_NCTF_26 VCC_NCTF_25
AU33 Y20 AA33
VCC_SM_2 VCC_AXG_NCTF_27 VCC_NCTF_26
AU35 Y21 AA35
VCC_SM_3 VCC_AXG_NCTF_28 VCC_NCTF_27
AV33 Y23 AA36
C151 C443 C436 VCC_SM_4 VCC_AXG_NCTF_29 VCC_NCTF_28
AW33 Y24 AP35
VCC_SM_5 VCC_AXG_NCTF_30 C114 C97 C98 C100 C109 C104 R125 VCC_NCTF_29
AW35 Y26 AP36
0.1u/10V_4 10u/10V_8 10u/10V_8 VCC_SM_6 VCC_AXG_NCTF_31 VCC_NCTF_30
AY35 Y28 AR35
VCC_SM_7 VCC_AXG_NCTF_32 IV@0.47u/10V_6 IV@1u/10V_6 IV@10u/10V_8 IV@22u/6.3V_8 IV@0.1u/10V_4 IV@0.1u/10V_4 EV@0_4 VCC_NCTF_31
BA32 Y29 AR36
VCC_SM_8 VCC_AXG_NCTF_33 VCC_NCTF_32
C BA33 AA16 Y32 C
VCC_SM_9 VCC_AXG_NCTF_34 VCC_NCTF_33
BA35 AA17 Y33
BB33
BC32
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
AB16
AB19
Y35
Y36
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
POWER
BC33 AC16 Y37 A3
VCC_SM_13 VCC_AXG_NCTF_38 VCC_NCTF_37 VSS_SCB1
BC35 AC17 T30 B2
VCC_SM_14 VCC_AXG_NCTF_39 VCC_NCTF_38 VSS_SCB2
BD32 AC19 T34 C1
VCC SM

VSS SCB
VCC_SM_15 VCC_AXG_NCTF_40 VCC_NCTF_39 VSS_SCB3
BD35 AD15 T35 BL1
VCC_SM_16 VCC_AXG_NCTF_41 VCC_NCTF_40 VSS_SCB4
BE32 AD16 U29 BL51
VCC_SM_17 VCC_AXG_NCTF_42 VCC_NCTF_41 VSS_SCB5
BE33 AD17 U31 A51
VCC_SM_18 VCC_AXG_NCTF_43 VCC_NCTF_42 VSS_SCB6
BE35 AF16 U32
VCC GFX NCTF

VCC_SM_19 VCC_AXG_NCTF_44 VCC_NCTF_43


BF33 AF19 U33
VCC_SM_20 VCC_AXG_NCTF_45 VCC_NCTF_44
BF34 AH15 U35
VCC_SM_21 VCC_AXG_NCTF_46 VCC_NCTF_45
BG32 AH16 U36
VCC_SM_22 VCC_AXG_NCTF_47 VCC_NCTF_46
BG33 AH17 V32
VCC_SM_23 VCC_AXG_NCTF_48 VCC_NCTF_47
BG35 AH19 V33
VCC_SM_24 VCC_AXG_NCTF_49 VCC_NCTF_48 +1.05V
BH32 AJ16 V36
VCC_SM_25 VCC_AXG_NCTF_50 VCC_NCTF_49
BH34 AJ17 V37
VCC_SM_26 VCC_AXG_NCTF_51 VCC_NCTF_50
BH35 AJ19
VCC_SM_27 VCC_AXG_NCTF_52
BJ32 AK16 AT33
VCC_SM_28 VCC_AXG_NCTF_53 VCC_AXM_1
BJ33 AK19 AT31
VCC_SM_29 VCC_AXG_NCTF_54 +1.05V VCC_AXM_2
BJ34 AL16 AK29

VCC AXM
VCC_SM_30 VCC_AXG_NCTF_55 VCC_AXM_3
BK32 AL17 540mA AK24
VCC_SM_31 VCC_AXG_NCTF_56 VCC_AXM_4
BK33 AL19 AK23
VCC_SM_32 VCC_AXG_NCTF_57 VCC_AXM_5
BK34 AL20 AL24 AJ26
VCC_SM_33 VCC_AXG_NCTF_58 VCC_AXM_NCTF_1 VCC_AXM_6
BK35 AL21 AL26 AJ23
VCC_SM_34 VCC_AXG_NCTF_59 VCC_AXM_NCTF_2 VCC_AXM_7
BL33 AL23 AL28
VCC_SM_35 VCC_AXG_NCTF_60 C155 C141 C159 C127 C158 C154 VCC_AXM_NCTF_3
AU30 AM15 AM26
VCC_SM_36 VCC_AXG_NCTF_61 VCC_AXM_NCTF_4
AM16 AM28

VCC AXM NCTF


+1.05_VCC_AXG_NCTF VCC_AXG_NCTF_62 10u/10V_8 0.22u/6.3V_4 0.22u/6.3V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 VCC_AXM_NCTF_5
AM19 AM29
B VCC_AXG_NCTF_63 VCC_AXM_NCTF_6 B
7700mA AM20 AM31
VCC_AXG_NCTF_64 VCC_AXM_NCTF_7
AM21 AM32
VCC_AXG_NCTF_65 VCC_AXM_NCTF_8
R20 AM23 AM33
VCC_AXG_1 VCC_AXG_NCTF_66 VCC_AXM_NCTF_9
T14 AP15 AP29
VCC_AXG_2 VCC_AXG_NCTF_67 VCC_AXM_NCTF_10
W13 AP16 AP31
VCC_AXG_3 VCC_AXG_NCTF_68 VCC_AXM_NCTF_11
W14 AP17 AP32
VCC_AXG_4 VCC_AXG_NCTF_69 VCC_AXM_NCTF_12
Y12 AP19 AP33
VCC_AXG_5 VCC_AXG_NCTF_70 VCC_AXM_NCTF_13
AA20 AP20 AL29
VCC_AXG_6 VCC_AXG_NCTF_71 VCC_AXM_NCTF_14
AA23 AP21 AL31
VCC_AXG_7 VCC_AXG_NCTF_72 VCC_AXM_NCTF_15
AA26 AP23 AL32
VCC_AXG_8 VCC_AXG_NCTF_73 VCC_AXM_NCTF_16
AA28 AP24 AR31
VCC_AXG_9 VCC_AXG_NCTF_74 VCC_AXM_NCTF_17
AB21 AR20 AR32
VCC_AXG_10 VCC_AXG_NCTF_75 VCC_AXM_NCTF_18
AB24 AR21 AR33
VCC_AXG_11 VCC_AXG_NCTF_76 VCC_AXM_NCTF_19
AB29 AR23
VCC_AXG_12 VCC_AXG_NCTF_77
AC20 AR24
VCC_AXG_13 VCC_AXG_NCTF_78
AC21 AR26
VCC GFX

VCC_AXG_14 VCC_AXG_NCTF_79
AC23 V26
VCC_AXG_15 VCC_AXG_NCTF_80 CRESTLINE_1p0
AC24 V28
VCC_AXG_16 VCC_AXG_NCTF_81
AC26 V29
VCC_AXG_17 VCC_AXG_NCTF_82
AC28 Y31
VCC_AXG_18 VCC_AXG_NCTF_83
AC29
VCC_AXG_19
AD20
VCC_AXG_20
AD23
VCC_AXG_21 VCCSM_LF1
AD24 AW45
VCC_AXG_22 VCC_SM_LF1 VCCSM_LF2
AD28 BC39
VCC_AXG_23 VCC_SM_LF2 VCCSM_LF3
AF21 BE39
VCC SM LF

VCC_AXG_24 VCC_SM_LF3 VCCSM_LF4


AF26 BD17
VCC_AXG_25 VCC_SM_LF4 VCCSM_LF5
AA31 BD4
VCC_AXG_26 VCC_SM_LF5 VCCSM_LF6
AH20 AW8
VCC_AXG_27 VCC_SM_LF6 VCCSM_LF7
A AH21 AT6 A
VCC_AXG_28 VCC_SM_LF7
AH23
VCC_AXG_29
AH24
VCC_AXG_30 C93 C94 C88 C96 C161 C163 C176
AH26
VCC_AXG_31
AD31
VCC_AXG_32 0.1u/10V_4 0.1u/10V_4 0.22u/6.3V_4 0.22u/6.3V_4 0.47u/10V_6 1u/10V_6 1u/10V_6
AJ20
VCC_AXG_33
AN14
VCC_AXG_34 Quanta Computer Inc.
PROJECT : TE1
Size Document Number Rev

CRESTLINE_1p0
GMCH Power-1(4 of 7) 1A

Date: Friday, September 21, 2007 Sheet 8 of 38


5 4 3 2 1

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5 4 3 2 1

NB(Power-2) +3V_VCCSYNC 10mA CRT/TV Disable/Enable guideline LVDS Disable/Enable guideline


+1.25V L17
External VGA with EV@part,Internal VGA with IV@ part
+3V R167 IV@0_6
IV@10uh_8 If SDVO Disable If SDVO enable If SDVO enable
C143 R165 Ball Enable Disable Ball Enable Disable Signal LVDS Disable LVDS Disable LVDS enable

C466 IV@0.1u/10V_4 *EV@0_4 VCCA_CRT 3.3V GND VCCA_C_TVO 3.3V GND VCCD_LVDS GND 1.8V 1.8V
+ C185
VCCD_CRT 1.5V GND VCCD_TVO 1.5V 1.5V VCCA_LVDS GND GND 1.8V
IV@220u/6.3V_7343 IV@0.1u/10V_4
70mA VCCDQ_CRT 1.5V GND VCCABG_DAC 3.3V GND VCCTX_LVDS GND GND 1.8V
+3V L36 IV@PBY160808T-301Y-N_6 +3V_VCCA_CRT_DAC
VCCA_A_TVO 3.3V GND VSSABG_DAC GND GND
C427 C433 C432 R424 EXTERNAL INTERNAL
D VCCA_B_TVO 3.3V GND VCC_SYNC 3.3V GND D
100mA **IV@22u/6.3V_8 IV@0.1u/10V_4 IV@22n/16V_4 *EV@0_4 850mA
+1.05V
U29H
+1.25V L19
+1.05V
IV@10uh_8 5mA J32
VCCSYNC VTT_1
U13
+3V_TV_DAC R120 IV@0_6 +3V_VCCA_DAC_BG U12
VTT_2
A33 U11
C464 C120 C123 R139 VCCA_CRT_DAC_1 VTT_3 C89 C73 C95 C82
B33 U9
+ C181 VCCA_CRT_DAC_2 VTT_4
U8
IV@0.1u/10V_4 IV@22n/16V_4 *EV@0_4 VTT_5 *4.7u/10V_8 *4.7u/10V_8 *2.2u/10V_8 0.47u/10V_6

CRT
U7
IV@220u/6.3V_7343 IV@0.1u/10V_4 VTT_6
A30 U5
VCCA_DAC_BG VTT_7
U3
VTT_8 +1.25V_AXD
B32 U2
VSSA_DAC_BG VTT_9
U1
VTT_10
VTT_11
T13 515mA
+1.25V_VCCA_DPLLA R140 0_6

VTT
B49 T11 +1.25V
VCCA_DPLLA VTT_12
T10
+1.25V_VCCA_DPLLB VTT_13
H49 T9
VCCA_DPLLB VTT_14 C119 C116
T7
L10 PBY160808T-301Y-N_6 +1.25VM_VCCA_HPLL VTT_15

PLL
+1.25V AL2 T6
VCCA_HPLL VTT_16 1u/10V_6 *22u/6.3V_8
T5
+1.25VM_VCCA_MPLL VTT_17
50mA C75 C85 AM2
VCCA_MPLL VTT_18
T3
+1.25V_VCCA_DPLLA 10mA T2
*22u/6.3V_8 0.1u/10V_4 VTT_19
R3
+1.25V_VCCA_DPLLB +1.8VSUS_VCC_TX_LVDS VTT_20 R414 0_6

A LVDS
A41 R2 +1.25V
VCCA_LVDS VTT_21
150mA VTT_22
R1
B41
VSSA_LVDS 495mA
R180 R183 L9 PBY160808T-301Y-N_6 C449 C407 C410
AT23
VCC_AXD_1
*EV@0_4 *EV@0_4 IV@1000p/50V_4 0.4mA VCC_AXD_2
AU28 1u/10V_6 *10u/10V_8
R76 C79 K50 AU24
C +3V_VCCA_PEG_BG VCCA_PEG_BG VCC_AXD_3 C

AXD
+3V R187 0_8 AT29
0.5/F_6 0.1u/10V_4 VCC_AXD_4
K49 AT25
VSSA_PEG_BG VCC_AXD_5
C192 Share VCCD_PEG_PLL

A PEG
AT30
C67 22u/6.3V_8 V1.25M_MPLL_RC VCC_AXD_6 R188 0_6 +1.25V
0.1u/10V_4 +1.25V_VCCD_PEG_PLL U51 AR29
VCCA_PEG_PLL VCC_AXD_NCTF
C177 0.1u/10V_4 DDR2:550mA 100mA C205

+1.25V R102 0_6 +1.25VM_VCCA_SM AW18 B23 +1.25V_VCC_AXF 0.1u/10V_4


VCCA_SM_1 VCC_AXF_1
AV19 B21
VCCA_SM_2
POWER VCC_AXF_2
200mA

AXF
AU19 A21
+ C69 C105 C102 C99 C101 VCCA_SM_3 VCC_AXF_3 L14 1uh_8
AU18 +1.8VSUS
VCCA_SM_4
AU17 AJ50 +1.25V_VCC_DMI
*100u/6.3V_3528 *22u/6.3V_8 *4.7u/10V_6 *22u/6.3V_8 *1u/10V_6 VCCA_SM_5 VCC_DMI C106 C118
R419 1_6 +V1.8_SMCK_RC C412 22u/6.3V_8

A SM
AT22
VCCA_SM_7
AT21 BK24 +1.8VSUS_VCC_SM_CK 0.1u/10V_4 10u/10V_8
VCCA_SM_8 VCC_SM_CK_1

SM CK
AT19 BK23
VCCA_SM_9 VCC_SM_CK_2
AT18 BJ24
R430 0_6 VCCA_SM_10 VCC_SM_CK_3
+1.25V AT17 BJ23
VCCA_SM_11 VCC_SM_CK_4
AR17
C452 C453 C458 C133 VCCA_SM_NCTF_1
AR16
VCCA_SM_NCTF_2
35mA 100mA +1.8VSUS
+3V_TV_DAC *1u/16V_6 *1u/16V_6 10u/10V_8 0.1u/10V_4 A43 +1.8VSUS_VCC_TX_LVDS L37 IV@1uh_8
+1.25VM_VCCA_SM_CK BC29 VCC_TX_LVDS

A CK
L31 IV@PBY160808T-301Y-N_6 VCCA_SM_CK_1
+3V BB29
VCCA_SM_CK_2
40mA VCC_HV_1
C40 +3V_VCC_HV 100mA R428 C448 + C444
C415 C416 R420 C25 B40
VCCA_TVA_DAC_1 VCC_HV_2
40mA

HV
B25 *EV@0_4 IV@1000p/50V_4 IV@220u/6.3V_7343
IV@0.1u/10V_4 IV@22n/16V_4 *EV@0_4 VCCA_TVA_DAC_2
C27
VCCA_TVB_DAC_1
40mA B27
VCCA_TVB_DAC_2 VCC_PEG_1
AD51

TV
B28 W50
VCCA_TVC_DAC_1 VCC_PEG_2

PEG
A28 W51
VCCA_TVC_DAC_2 VCC_PEG_3 +VCC_PEG
R143 *EV@0_4
VCC_PEG_4
V49 1310mA
B 60mA VCC_PEG_5
V50 B
R126 IV@0_6 +1.5V_VCCD_CRT

D TV/CRT
M32
VCCD_CRT
+1.5V_VCCD_TVDAC L29
VCCD_TVDAC
260mA
C413 C422 60mA 0.5mA VCC_RXR_DMI_1
AH50 L38 91nh_L32 +1.05V
+1.5V_VCCD_QDAC

DMI
N28 AH51
IV@0.1u/10V_4 IV@22n/16V_4 VCCD_QDAC VCC_RXR_DMI_2

+1.25V R99 0_6 +1.25VM_MCH_VCCD_HPLL AN2 C467 + C463


VCCD_HPLL
A7
+1.25V_VCCD_PEG_PLL VTTLF1
250mA C86 *10u/10V_8 *220u/6.3V_7343

VTTLF
U48 F2
VCCD_PEG_PLL VTTLF2
AH1
0.1u/10V_4 VTTLF3
J41
VCCD_LVDS_1 LVDS C81 C83 C405
H42
VCCD_LVDS_2
C411 C420 C421 C414 90mA
0.47u/6.3V_4 0.47u/6.3V_4 0.47u/6.3V_4
IV@22u/6.3V_8 IV@10u/10V_8 IV@0.1u/10V_4 IV@22n/16V_4 +1.25V L20 PBY160808T-301Y-N_6
CRESTLINE_1p0

R185 C190

1_8 0.1u/10V_4

+V1.25S_PEGPLL_FB
+3V_VCCSYNC +1.05V
C209
R151 IV@10_4 VCCGFPLLOW D15 1 2 IV@PDZ5.6B
10u/10V_8
+1.5V R118 0_6

C128 C107

0.1u/10V_4 22n/16V_4 +1.05V D18 2 1 PDZ5.6B +1.05V_SD


A 150mA A
+3V_VCC_HV
+1.8VSUS R176 IV@0_6 +1.8V_VCCD_LVDS R191

10_4
R109 IV@100/F_6 C167 C172 R172
+3V R425 0_4
IV@1u/10V_6 **IV@10u/10V_8 *EV@0_4
C126 C112 C108 R122
C441
Quanta Computer Inc.
IV@0.1u/10V_4 IV@22n/16V_4 IV@1u/10V_6 *EV@0_4
0.1u/10V_4
PROJECT : TE1
Size Document Number Rev
GMCH Power-2(5 of 7) 1A

Date: Friday, September 21, 2007 Sheet 9 of 38


5 4 3 2 1

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5 4 3 2 1

NB(Power-3)
U29I
U29J
A13 AW24 C46 W11
VSS_1 VSS_100 VSS_199 VSS_287
A15 AW29 C50 W39
VSS_2 VSS_101 VSS_200 VSS_288
A17 AW32 C7 W43
VSS_3 VSS_102 VSS_201 VSS_289
A24 AW5 D13 W47
VSS_4 VSS_103 VSS_202 VSS_290
AA21 AW7 D24 W5
VSS_5 VSS_104 VSS_203 VSS_291
AA24 AY10 D3 W7
VSS_6 VSS_105 VSS_204 VSS_292
AA29 AY24 D32 Y13
VSS_7 VSS_106 VSS_205 VSS_293
AB20 AY37 D39 Y2
D VSS_8 VSS_107 VSS_206 VSS_294 D
AB23 AY42 D45 Y41
VSS_9 VSS_108 VSS_207 VSS_295
AB26 AY43 D49 Y45
VSS_10 VSS_109 VSS_208 VSS_296
AB28 AY45 E10 Y49
VSS_11 VSS_110 VSS_209 VSS_297
AB31 AY47 E16 Y5
VSS_12 VSS_111 VSS_210 VSS_298
AC10 AY50 E24 Y50
VSS_13 VSS_112 VSS_211 VSS_299
AC13 B10 E28 Y11
VSS_14 VSS_113 VSS_212 VSS_300
AC3 B20 E32 P29
VSS_15 VSS_114 VSS_213 VSS_301
AC39 B24 E47 T29
VSS_16 VSS_115 VSS_214 VSS_302
AC43 B29 F19 T31
VSS_17 VSS_116 VSS_215 VSS_303
AC47 B30 F36 T33
VSS_18 VSS_117 VSS_216 VSS_304
AD1 B35 F4 R28
VSS_19 VSS_118 VSS_217 VSS_305
AD21 B38 F40
VSS_20 VSS_119 VSS_218
AD26 B43 F50
VSS_21 VSS_120 VSS_219
AD29 B46 G1
VSS_22 VSS_121 VSS_220
AD3 B5 G13 AA32
VSS_23 VSS_122 VSS_221 VSS_306
AD41 B8 G16 AB32
VSS_24 VSS_123 VSS_222 VSS_307
AD45 BA1 G19 AD32
VSS_25 VSS_124 VSS_223 VSS_308
AD49 BA17 G24 AF28
VSS_26 VSS_125 VSS_224 VSS_309
AD5 BA18 G28 AF29
VSS_27 VSS_126 VSS_225 VSS_310
AD50 BA2 G29 AT27
VSS_28 VSS_127 VSS_226 VSS_311
AD8 BA24 G33 AV25
VSS_29 VSS_128 VSS_227 VSS_312
AE10 BB12 G42 H50
VSS_30 VSS_129 VSS_228 VSS_313
AE14 BB25 G45
VSS_31 VSS_130 VSS_229
AE6 BB40 G48
VSS_32 VSS_131 VSS_230
AF20 BB44 G8
AF23
AF24
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
BB49
BB8
H24
H28
VSS_231
VSS_232
VSS_233
AF31 BC16 H4
VSS_36 VSS_135 VSS_234
C AG2 BC24 H45 C
VSS_37 VSS_136 VSS_235
AG38 BC25 J11
VSS_38 VSS_137 VSS_236
AG43 BC36 J16
VSS_39 VSS_138 VSS_237
AG47 BC40 J2
VSS_40 VSS_139 VSS_238
AG50 BC51 J24
VSS_41 VSS_140 VSS_239
AH3 BD13 J28
VSS_42 VSS_141 VSS_240
AH40 BD2 J33
AH41
AH7
VSS_43
VSS_44
VSS_45
VSS_142
VSS_143
VSS_144
BD28
BD45
J35
J39
VSS_241
VSS_242
VSS_243
VSS
AH9 BD48
VSS_46 VSS_145
AJ11 BD5 K12
VSS_47 VSS_146 VSS_245
AJ13 BE1 K47
VSS_48 VSS_147 VSS_246
AJ21 BE19 K8
VSS_49 VSS_148 VSS_247
AJ24 BE23 L1
VSS_50 VSS_149 VSS_248
AJ29 BE30 L17
VSS_51 VSS_150 VSS_249
AJ32 BE42 L20
VSS_52 VSS_151 VSS_250
AJ43 BE51 L24
VSS_53 VSS_152 VSS_251
AJ45 BE8 L28
VSS_54 VSS_153 VSS_252
AJ49 BF12 L3
VSS_55 VSS_154 VSS_253
AK20 BF16 L33
VSS_56 VSS_155 VSS_254
AK21 BF36 L49
VSS_57 VSS_156 VSS_255
AK26 BG19 M28
VSS_58 VSS_157 VSS_256
AK28 BG2 M42
VSS_59 VSS_158 VSS_257
AK31 BG24 M46
VSS_60 VSS_159 VSS_258
AK51 BG29 M49
VSS_61 VSS_160 VSS_259
AL1 BG39 M5
VSS_62 VSS_161 VSS_260
AM11 BG48 M50
VSS_63 VSS_162 VSS_261
AM13 BG5 M9
VSS_64 VSS_163 VSS_262
B AM3 BG51 N11 B
VSS_65 VSS_164 VSS_263
AM4 BH17 N14
VSS_66 VSS_165 VSS_264
AM41 BH30 N17
VSS_67 VSS_166 VSS_265
AM45 BH44 N29
VSS_68 VSS_167 VSS_266
AN1 BH46 N32
VSS_69 VSS_168 VSS_267
AN38 BH8 N36
VSS_70 VSS_169 VSS_268
AN39 BJ11 N39
VSS_71 VSS_170 VSS_269
AN43 BJ13 N44
VSS_72 VSS_171 VSS_270
AN5 BJ38 N49
VSS_73 VSS_172 VSS_271
AN7 BJ4 N7
VSS_74 VSS_173 VSS_272
AP4 BJ42 P19
VSS_75 VSS_174 VSS_273
AP48 BJ46 P2
VSS_76 VSS_175 VSS_274
AP50 BK15 P23
VSS_77 VSS_176 VSS_275
AR11 BK17 P3
VSS_78 VSS_177 VSS_276
AR2 BK25 P50
VSS_79 VSS_178 VSS_277
AR39 BK29 R49
VSS_80 VSS_179 VSS_278
AR44 BK36 T39
VSS_81 VSS_180 VSS_279
AR47 BK40 T43
VSS_82 VSS_181 VSS_280
AR7 BK44 T47
VSS_83 VSS_182 VSS_281
AT10 BK6 U41
VSS_84 VSS_183 VSS_282
AT14 BK8 U45
VSS_85 VSS_184 VSS_283
AT41 BL11 U50
VSS_86 VSS_185 VSS_284
AT49 BL13 V2
VSS_87 VSS_186 VSS_285
AU1 BL19 V3
VSS_88 VSS_187 VSS_286
AU23 BL22
VSS_89 VSS_188
AU29 BL37
VSS_90 VSS_189 CRESTLINE_1p0
AU3 BL47
VSS_91 VSS_190
AU36 C12
VSS_92 VSS_191
AU49 C16
A VSS_93 VSS_192 A
AU51 C19
VSS_94 VSS_193
AV39 C28
VSS_95 VSS_194
AV48 C29
VSS_96 VSS_195
AW1 C33
VSS_97 VSS_196
AW12 C36
VSS_98 VSS_197
AW16 C41
VSS_99 VSS_198 Quanta Computer Inc.
CRESTLINE_1p0
PROJECT : TE1
Size Document Number Rev
GMCH Power-3(6 of 7) 1A

Date: Thursday, September 20, 2007 Sheet 10 of 38


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Strap table(base on checklist Ver1.6)


All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal
CFG[17:3] Have internal Pull-up
CFG[18:19] Have internal Pull-down
Any CFG signal strapping option not list below should be left NC Pin

Pin Name Strap description Configuration

CFG[2:0] FSB Frequency Select 010 = FSB 800MHz


D 011 = FSB 667MHz D

CFG[4:3] Reserved

CFG5 DMI X2 Select 0 = DMI X2


1 = DMI X4(Default)

CFG6 Reserved

CFG7 Intel? Management Engine Crypto strap 0 = Intel? Management Engine Crypto Transport Layer.Security (TLS) cipher suite with no confidentiality
1= Intel Management Engine Crypto TLS Cipher Suite with confidentiality (default)

CFG8 Reserved

CFG9 PCI Express Graphics Lane Reversal 0 = Reverse Lanes


1 = Normal operation(Default)

CFG[11:10] Reserved

C C
CFG[13:12] XOR/ALLZ 00 = Reserved
01 = XOR Mode Enable
10 = All-Z Mode Enabled
11 = Normal operation(Default)

CFG[15:14] Reserved

CFG16 FSB Dynamic ODT 0 = Dynamic ODT disable


1 = Dynamic ODT Enable(Default)

CFG[18:17] Reserved

SDVO_CTRLDATA SDVO Present 0 = No SDVO Card present(Default)


1 = SDVO Card Present

CFG19 DMI Lane Reversal 0 = Normal operation(Default)


1 = Reverse Lanes

CFG20 SDVO/PCIe concurrent 0 = Only SDVO or PCIE is operation(Default)


1 = SDVO and PCIE are operating simultaneously via the PEG port
B B

DMI X2 Select DMI Lane Reversal XOR /ALLz /Clock Un-gating PCI Express Graphics SDVO Present

MCH_CFG_5 Low = DMIX2 MCH_CFG_19 Low = Normal operation(Default) MCH_CFG_12 MCH_CFG_13 Configuration MCH_CFG_9 Low = Reverse Lane Strap define at External
High = IDMIX4(Default) High = Reverse Lane High = Normal operation(Default)
HDMI control page
0 0 Clock gating disable

+3V
(6) MCH_CFG_5 (6) MCH_CFG_9
0 1 XOR Mode Enable

1 0 ALL-z Mode Enable


R114 R111
R164
*4.02K_4 1 1 Normal operation(Default) *4.02K_4
*4.02K_4

(6) MCH_CFG_19
FSB Dynamic ODT SDVO/PCIE Concurrent operation
Low = Only SDVO or PCIE is
MCH_CFG_16 Low = ODT Disable MCH_CFG_20 operational(Default)
High = ODT Enable(Default) High = SDVO andPCIE are operating
simultaneously via the PEG port
(6) MCH_CFG_12
A (6) MCH_CFG_13 A
(6) MCH_CFG_16 +3V

R123 R112
R108
*4.02K_4 *4.02K_4
*4.02K_4 R148

*4.02K_4
Quanta Computer Inc.
PROJECT : TE1
Size Document Number Rev
(6) MCH_CFG_20 GMCH Strap(7 of 7) 1A

Date: Thursday, September 20, 2007 Sheet 11 of 38


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DDR2 Dual channel A/B PU

A A
M_A_A[13..0]
M_A_A[13..0] (7,13)
M_B_A[13..0]
M_B_A[13..0] (7,13)
DDRII A CHANNEL DDRII B CHANNEL
+SMDDR_VTERM +SMDDR_VTERM

C148 C165 C121 C132 C183 C174 C162 C147 C142 C194 C193 C195 C134 C202 C171 C124 C139 C125 C196 C203 C169 C160 C144 C178 C199 C152

0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4

Place one cap close to every 2 pull-up resistor terminated to SMDDR_VTERM

B B

M_A_A3 RP28 1 2 56X2 +SMDDR_VTERM


M_A_A1 3 4

M_A_A9 RP34 1 2 56X2 M_A_A7 RP37 1 2 56X2 +SMDDR_VTERM


M_A_A5 3 4 M_A_A6 3 4

M_A_A2 RP32 1 2 56X2 RP43 1 2 56X2


(6,13) M_CKE3
M_A_A4 3 4 (7,13) M_B_BS#2 3 4

M_A_A11 RP40 1 2 56X2 RP18 1 2 56X2


(6,13) M_ODT1
(6,13) M_CKE1 3 4 (6,13) M_CS#1 3 4

RP38 1 2 56X2
(6,13) M_CKE0
M_A_A8 3 4 (6,13) M_ODT3 RP19 1 2 56X2
(7,13) M_B_BS#0 3 4

M_A_A12 RP41 1 2 56X2


3 4 M_A_A10 RP24 1 2 56X2
(7,13) M_A_BS#2
(7,13) M_A_BS#0 3 4

RP25 1 2 56X2
(7,13) M_A_BS#1
M_A_A0 3 4 RP21 1 2 56X2
(7,13) M_A_CAS#
(7,13) M_A_WE# 3 4
C C
RP23 1 2 56X2
(6,13) M_CS#0
(7,13) M_A_RAS# 3 4

M_B_A10 RP26 1 2 56X2 +SMDDR_VTERM


(7,13) M_B_WE# 3 4 (7,13) M_B_CAS# RP22 1 2 56X2
(6,13) M_CS#3 3 4

M_B_A3 RP29 1 2 56X2


M_B_A1 3 4 M_B_A6 RP42 1 2 56X2
(6,13) M_CKE4 3 4

RP27 1 2 56X2
(7,13) M_B_BS#1
M_B_A0 3 4 (6,13) M_ODT2 RP20 1 2 56X2
(7,13) M_B_RAS# 3 4

M_B_A7 RP35 1 2 56X2


M_B_A11 3 4 (6,13) M_ODT0 RP16 1 2 56X2
M_A_A13 3 4

M_B_A8 RP33 1 2 56X2


M_B_A5 3 4 M_B_A13 RP17 1 2 56X2
(6,13) M_CS#2 3 4

M_B_A2 RP31 1 2 56X2


M_B_A4 3 4

M_B_A9 RP36 1 2 56X2


D M_B_A12 3 4 D

R181 56_4 +SMDDR_VTERM


Quanta Computer Inc.
(6,13) M_A_A14
R178 56_4
(6,13) M_B_A14 PROJECT : TE1
Size Document Number Rev
DDR RES. ARRAY 1A

Date: Thursday, September 20, 2007 Sheet 12 of 38


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DDR2 Dual channel A/B CONN SMDDR_VREF_DIMM


M_A_DM[0..7] (7) M_B_DM[0..7] (7)
SMDDR_VREF_DIMM Close to DIMM0
M_A_DQ[0..63] (7) M_B_DQ[0..63] (7)
DDR2 VCC(SUS)
M_A_DQS[0..7] (7) M_B_DQS[0..7] (7)
DDR2-800 each dimm is 2.8A +1.8VSUS +1.8VSUS +1.8VSUS +1.8VSUS
M_A_DQS#[0..7] (7) M_B_DQS#[0..7] (7)
DDR2-667 EACH DIMM IS 2.6A CN24
M_A_A[0..13] (7,12) M_B_A[0..13] (7,12)
VTERM(SUS) CN25 1 2
3A VREF VSS46 M_B_DQ4 +1.8VSUS
1 VREF VSS46 2 3 VSS47 DQ4 4
3 4 M_A_DQ4 M_B_DQ0 5 6 M_B_DQ1
M_A_DQ6 VSS47 DQ4 M_A_DQ0 M_B_DQ5 DQ0 DQ5
5 6 7 8
M_A_DQ5 DQ0 DQ5 DQ1 VSS15 M_B_DM0
7 8 9 10
DQ1 VSS15 M_A_DM0 M_B_DQS#0 VSS37 DM0
9 10 11 12
M_A_DQS#0 VSS37 DM0 M_B_DQS0 DQS#0 VSS5 M_B_DQ2
11 12 13 14
M_A_DQS0 DQS#0 VSS5 M_A_DQ7 DQS0 DQ6 M_B_DQ6 + C461 C447 C459 C438 C446 C440
13 DQS0 DQ6 14 15 VSS48 DQ7 16
15 16 M_A_DQ1 M_B_DQ7 17 18
M_A_DQ2 VSS48 DQ7 M_B_DQ3 DQ2 VSS16 M_B_DQ12 *330u/2.5V_3528 *2.2u/6.3V_6 *2.2u/6.3V_6 *2.2u/6.3V_6 *2.2u/6.3V_6 *2.2u/6.3V_6
17 DQ2 VSS16 18 19 DQ3 DQ12 20
A M_A_DQ3 19 20 M_A_DQ13 21 22 M_B_DQ13 A
DQ3 DQ12 M_A_DQ12 M_B_DQ9 VSS38 DQ13
21 VSS38 DQ13 22 23 DQ8 VSS17 24
M_A_DQ9 23 24 M_B_DQ8 25 26 M_B_DM1
M_A_DQ8 DQ8 VSS17 M_A_DM1 DQ9 DM1
25 26 27 28
DQ9 DM1 M_B_DQS#1 VSS49 VSS53 +1.8VSUS +3V
27 VSS49 VSS53 28 29 DQS#1 CK0 30 M_CLK_DDR3 (6)
M_A_DQS#1 29 30 M_B_DQS1 31 32
DQS#1 CK0 M_CLK_DDR0 (6) DQS1 CK0# M_CLK_DDR#3 (6)
M_A_DQS1 31 32 33 34
DQS1 CK0# M_CLK_DDR#0 (6) VSS39 VSS41
33 34 M_B_DQ11 35 36 M_B_DQ14
M_A_DQ14 VSS39 VSS41 M_A_DQ10 M_B_DQ10 DQ10 DQ14 M_B_DQ15 C136 C180 C450 C168 C74 C78
35 36 37 38
M_A_DQ11 DQ10 DQ14 M_A_DQ15 DQ11 DQ15
37 DQ11 DQ15 38 39 VSS50 VSS54 40
39 40 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 *2.2u/6.3V_6 0.1u/10V_4
VSS50 VSS54
41 42

PC4800 DDR2 SDRAM


M_B_DQ20 VSS18 VSS20 M_B_DQ16
41 VSS18 VSS20 42 43 DQ16 DQ20 44
M_A_DQ17 43 44 M_A_DQ16 M_B_DQ17 45 46 M_B_DQ21
M_A_DQ20 DQ16 DQ20 M_A_DQ21 DQ17 DQ21 SMDDR_VREF_DIMM

PC4800 DDR2 SDRAM


45 DQ17 DQ21 46 47 VSS1 VSS6 48
47 48 M_B_DQS#2 49 50 PM_EXTTS#1 (6)
M_A_DQS#2 VSS1 VSS6 M_B_DQS2 DQS#2 NC3 M_B_DM2
49 DQS#2 NC3 50 PM_EXTTS#0 (6) 51 DQS2 DM2 52
M_A_DQS2 51 52 M_A_DM2 53 54
SO-DIMM (200P)
DQS2 DM2 M_B_DQ22 VSS19 VSS21 M_B_DQ18 C217 C220
53 54 55 56
M_A_DQ23 VSS19 VSS21 M_A_DQ18 M_B_DQ23 DQ18 DQ22 M_B_DQ19
55 56 57 58
M_A_DQ19 DQ18 DQ22 M_A_DQ22 DQ19 DQ23 0.1u/10V_4 *2.2u/6.3V_6

SO-DIMM (200P)
57 58 59 60
DQ19 DQ23 M_B_DQ29 VSS22 VSS24 M_B_DQ24
59 60 61 62
M_A_DQ28 VSS22 VSS24 M_A_DQ29 M_B_DQ28 DQ24 DQ28 M_B_DQ25
61 DQ24 DQ28 62 63 DQ25 DQ29 64
M_A_DQ25 63 64 M_A_DQ24 65 66
DQ25 DQ29 M_B_DM3 VSS23 VSS25 M_B_DQS#3
65 VSS23 VSS25 66 67 DM3 DQS#3 68
M_A_DM3 67 68 M_A_DQS#3 69 70 M_B_DQS3
DM3 DQS#3 M_A_DQS3 NC4 DQS3
69 NC4 DQS3 70 71 VSS9 VSS10 72
71 72 M_B_DQ26 73 74 M_B_DQ30
M_A_DQ26 VSS9 VSS10 M_A_DQ30 M_B_DQ27 DQ26 DQ30 M_B_DQ31
73 74 75 76
M_A_DQ27 DQ26 DQ30 M_A_DQ31 DQ27 DQ31
75 DQ27 DQ31 76 77 VSS4 VSS8 78
77 78 (6,12) M_CKE3 79 80 M_CKE4 (6,12)
VSS4 VSS8 CKE0 CKE1
(6,12) M_CKE0 79 CKE0 CKE1 80 M_CKE1 (6,12) 81 VDD7 VDD8 82
B 81 82 83 84 B
VDD7 VDD8 NC1 A15
83 84 (7,12) M_B_BS#2 85 86 M_B_A14 (6,12)
NC1 A15 A16_BA2 A14 Close to DIMM1
(7,12) M_A_BS#2 85 A16_BA2 A14 86 M_A_A14 (6,12) 87 VDD9 VDD11 88
87 88 M_B_A12 89 90 M_B_A11
M_A_A12 VDD9 VDD11 M_A_A11 M_B_A9 A12 A11 M_B_A7
89 A12 A11 90 91 A9 A7 92
M_A_A9 91 92 M_A_A7 M_B_A8 93 94 M_B_A6
M_A_A8 A9 A7 M_A_A6 A8 A6
93 94 95 96
A8 A6 M_B_A5 VDD5 VDD4 M_B_A4
95 VDD5 VDD4 96 97 A5 A4 98
M_A_A5 97 98 M_A_A4 M_B_A3 99 100 M_B_A2 +1.8VSUS
M_A_A3 A5 A4 M_A_A2 M_B_A1 A3 A2 M_B_A0
99 A3 A2 100 101 A1 A0 102
M_A_A1 101 102 M_A_A0 103 104
A1 A0 M_B_A10 VDD10 VDD12
103 104 105 106 M_B_BS#1 (7,12)
M_A_A10 VDD10 VDD12 A10/AP BA1
105 106 M_A_BS#1 (7,12) (7,12) M_B_BS#0 107 108 M_B_RAS# (7,12)
A10/AP BA1 BA0 RAS# + C138 C435 C456 C451 C429 C457
(7,12) M_A_BS#0 107 108 M_A_RAS# (7,12) (7,12) M_B_WE# 109 110 M_CS#2 (6,12)
BA0 RAS# WE# S0#
(7,12) M_A_WE# 109 110 M_CS#0 (6,12) 111 112
WE# S0# VDD2 VDD1 *330u/2.5V_3528 *2.2u/6.3V_6 *2.2u/6.3V_6 *2.2u/6.3V_6 *2.2u/6.3V_6 *2.2u/6.3V_6
111 VDD2 VDD1 112 (7,12) M_B_CAS# 113 CAS# ODT0 114 M_ODT2 (6,12)
113 114 115 116 M_B_A13
(7,12) M_A_CAS# CAS# ODT0 M_ODT0 (6,12) (6,12) M_CS#3 S1# A13
115 116 M_A_A13 117 118
(6,12) M_CS#1 S1# A13 VDD3 VDD6
117 118 (6,12) M_ODT3 119 120
VDD3 VDD6 ODT1 NC2
(6,12) M_ODT1 119 ODT1 NC2 120 121 VSS11 VSS12 122
121 122 M_B_DQ37 123 124 M_B_DQ32
M_A_DQ36 VSS11 VSS12 M_A_DQ32 M_B_DQ38 DQ32 DQ36 M_B_DQ36 +1.8VSUS +3V
123 124 125 126
M_A_DQ37 DQ32 DQ36 M_A_DQ33 DQ33 DQ37
125 DQ33 DQ37 126 127 VSS26 VSS28 128
127 128 M_B_DQS#4 129 130 M_B_DM4
M_A_DQS#4 VSS26 VSS28 M_A_DM4 M_B_DQS4 DQS#4 DM4
129 DQS#4 DM4 130 131 DQS4 VSS42 132
M_A_DQS4 131 132 133 134 M_B_DQ39 C191 C157 C164 C150 C76 C80
DQS4 VSS42 M_A_DQ35 M_B_DQ34 VSS2 DQ38 M_B_DQ33
133 134 135 136
M_A_DQ39 VSS2 DQ38 M_A_DQ38 M_B_DQ35 DQ34 DQ39 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 *2.2u/6.3V_6 0.1u/10V_4
135 DQ34 DQ39 136 137 DQ35 VSS55 138
M_A_DQ34 137 138 139 140 M_B_DQ44
DQ35 VSS55 M_A_DQ44 M_B_DQ40 VSS27 DQ44 M_B_DQ45
139 VSS27 DQ44 140 141 DQ40 DQ45 142
M_A_DQ40 141 142 M_A_DQ45 M_B_DQ41 143 144
M_A_DQ41 DQ40 DQ45 DQ41 VSS43 M_B_DQS#5
143 DQ41 VSS43 144 145 VSS29 DQS#5 146
C 145 146 M_A_DQS#5 M_B_DM5 147 148 M_B_DQS5 SMDDR_VREF_DIMM C
M_A_DM5 VSS29 DQS#5 M_A_DQS5 DM5 DQS5
147 DM5 DQS5 148 149 VSS51 VSS56 150
149 150 M_B_DQ46 151 152 M_B_DQ42
M_A_DQ42 VSS51 VSS56 M_A_DQ43 M_B_DQ43 DQ42 DQ46 M_B_DQ47
151 DQ42 DQ46 152 153 DQ43 DQ47 154
M_A_DQ46 153 154 M_A_DQ47 155 156 C216 C219
DQ43 DQ47 M_B_DQ53 VSS40 VSS44 M_B_DQ52
155 VSS40 VSS44 156 157 DQ48 DQ52 158
M_A_DQ53 157 158 M_A_DQ48 M_B_DQ49 159 160 M_B_DQ48 0.1u/10V_4 *2.2u/6.3V_6
M_A_DQ49 DQ48 DQ52 M_A_DQ52 DQ49 DQ53
159 DQ49 DQ53 160 161 VSS52 VSS57 162
161 VSS52 VSS57 162 163 NCTEST CK1 164 M_CLK_DDR4 (6)
163 NCTEST CK1 164 M_CLK_DDR1 (6) 165 VSS30 CK1# 166 M_CLK_DDR#4 (6)
165 166 M_B_DQS#6 167 168
VSS30 CK1# M_CLK_DDR#1 (6) DQS#6 VSS45
M_A_DQS#6 167 168 M_B_DQS6 169 170 M_B_DM6
M_A_DQS6 DQS#6 VSS45 M_A_DM6 DQS6 DM6
169 DQS6 DM6 170 171 VSS31 VSS32 172
171 172 M_B_DQ51 173 174 M_B_DQ55
M_A_DQ50 VSS31 VSS32 M_A_DQ54 M_B_DQ54 DQ50 DQ54 M_B_DQ50
173 DQ50 DQ54 174 175 DQ51 DQ55 176
M_A_DQ51 175 176 M_A_DQ55 177 178
DQ51 DQ55 M_B_DQ56 VSS33 VSS35 M_B_DQ60
177 VSS33 VSS35 178 179 DQ56 DQ60 180
M_A_DQ56 179 180 M_A_DQ61 M_B_DQ57 181 182 M_B_DQ61
M_A_DQ60 DQ56 DQ60 M_A_DQ57 DQ57 DQ61
181 DQ57 DQ61 182 183 VSS3 VSS7 184
183 184 M_B_DM7 185 186 M_B_DQS#7
M_A_DM7 VSS3 VSS7 M_A_DQS#7 DM7 DQS#7 M_B_DQS7
185 186 187 188
DM7 DQS#7 M_A_DQS7 M_B_DQ59 VSS34 DQS7 SMDDR_VREF_DIMM
187 VSS34 DQS7 188 189 DQ58 VSS36 190
M_A_DQ62 189 190 M_B_DQ62 191 192 M_B_DQ63
M_A_DQ63 DQ58 VSS36 M_A_DQ58 DQ59 DQ62 M_B_DQ58
191 DQ59 DQ62 192 193 VSS14 DQ63 194
193 194 M_A_DQ59 CGDAT_SMB 195 196
VSS14 DQ63 (2) CGDAT_SMB SDA VSS13
CGDAT_SMB 195 196 CGCLK_SMB 197 198 R408 10K_4
SDA VSS13 (2) CGCLK_SMB SCL SA0
CGCLK_SMB 197 198 R89 10K_4 +3V 199 200 R407 10K_4 R199 0_6 +SMDDR_VREF
SCL SA0 R87 10K_4 VDD(SPD) SA1
+3V 199 VDD(SPD) SA1 200
DDR2_10.1H +3V
DDR2_5.6H R202 *10K_4 R201 *10K_4 +1.8VSUS
SO-DIMM0 SPD Address is 0xA0 SO-DIMM1 SPD Address is 0xA4
SO-DIMM0 TS Address is 0x30 SO-DIMM1 TS Address is 0x34
D D

H: 5.6mm H: 10.1mm
CLOCK 0,1 CLOCK 3,4
CKE 0,1 CKE 2,3 Quanta Computer Inc.
PROJECT : TE1
Size Document Number Rev
1A
DDR SO-DIMM(200P)
Date: Thursday, September 20, 2007 Sheet 13 of 38
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RTC VCCRTC SB-1

D32 CH500H-40 VCCRTC C478 1u/10V_6


+3VPCU

Delay 18~25ms
C589 15p/50V_4
VCCRTC_4 D35 CH500H-40 R443 20K_6

1
R451 R442 G1 C477 Y6 R532

1K_4 *SHORT_PAD 1u/10V_6 32.768KHZ 10M_6


U37A

2
D 1M_6 D
CLK_32KX1 AG25 E5
RTCX1 FWH0/LAD0 LAD0 (25,28)
C590 15p/50V_4 CLK_32KX2 AF24 F5
RTCX2 FWH1/LAD1 LAD1 (25,28)
CN28 G8
FWH2/LAD2 LAD2 (25,28)
1 RTCRST# AF23 F6
1 RTCRST# FWH3/LAD3 LAD3 (25,28)
2
2 SM_INTRUDER# AD22 C4 LFRAME# (25,28)
RTC_CONN INTRUDER# FWH4/LFRAME#
ICH_INTVRMEN +1.05V_V_CPU_IO

RTC
LPC
AF25 G9 T40
LAN100_SLP INTVRMEN LDRQ0# LDRQ#1
CMOS Setting G1 AD21
LAN100_SLP LDRQ1#/GPIO23
E6 LDRQ#1 (25)
Clear CMOS Short B24 AF13 GATEA20
GLAN_CLK A20GATE GATEA20 (28)
Keep CMOS Open A20M#
AG26 H_A20M# (3)
D22 R284
LAN_RSTSYNC
AF26 ICH_DPRSTP# (3,6,33)
DPRSTP# 56.2/F_4
C21 AE26 H_DPSLP# (3)
LAN_RXD0 DPSLP#
B21
LAN_RXD1
C22 AD24 H_FERR# (3)
VCCRTC_3 LAN_RXD2 FERR#

LAN / GLAN
D21 AG29 H_PWRGD (3)
LAN_TXD0 CPUPWRGD/GPIO49
E20
LAN_TXD1
C20 AF27 H_IGNNE# (3)
LAN_TXD2 IGNNE#
+5VPCU AH21 AE24
GLAN_DOCK#/GPIO13 INIT# H_INIT# (3) +1.05V_V_CPU_IO
AC20 H_INTR (3)
R246 24.9/F_4 GLAN_COMP_SB INTR RCIN#

CPU
+1.5V_PCIE D25 AH14 RCIN# (28)
R456 8.66K/F_4 VCCRTC_1 R455 8.66K/F_4 VCCRTC_2 GLAN_COMPI RCIN#
3 1 C25
GLAN_COMPO R537
AD23 H_NMI (3)
ACZ_BCLK NMI
AJ16 AG28 H_SMI# (3)
R449 Q33 ACZ_SYNC HDA_BIT_CLK SMI# 56.2/F_4
AJ15
HDA_SYNC
2

AA24 Placement close SB L<2"


STPCLK# H_STPCLK# (3)
4.7K_4 MMBT3904 ACZ_RST# AE14
C HDA_RST# H_THERMTRIP_R R529 24/F_6 R533 *0_4 C
AE27 PM_THRMTRIP# (3,6)
THRMTRIP#
(29) ACZ_SDIN0 AJ17
HDA_SDIN0 ICH_TP8
AH17 AA23 T42
ACZ_SDIN2 T65 HDA_SDIN1 TP8
(21) ACZ_SDIN2 AH15 PDD[15:0] (22)
R450 HDA_SDIN2 PDD0

IHDA
AD13 V1
T46 HDA_SDIN3 DD0 PDD1
U2
15K_4 ACZ_SDOUT DD1 PDD2
AE13 V3
HDA_SDOUT DD2 PDD3 +3V +3V
T1
DD3 PDD4
AE10 V4
T47 HDA_DOCK_EN#/GPIO33 DD4 PDD5
AG14 T5
T66 HDA_DOCK_RST#/GPIO34 DD5 PDD6
AB2
SATA_LED# DD6 PDD7 R559 R317
(26) SATA_LED# AF10 T6
SATALED# DD7 PDD8
T3
C316 3900p/25V_4 SATA_RXN0_C DD8 PDD9 10K_4 8.2K_4
(22) SATA_RXN0 AF6 R2
C313 3900p/25V_4 SATA_RXP0_C SATA0RXN DD9 PDD10
(22) SATA_RXP0 AF5 T4
C318 3900p/25V_4 SATA_TXN0_C SATA0RXP DD10 PDD11 RCIN#
(22) SATA_TXN0 AH5 V6
C320 3900p/25V_4 SATA_TXP0_C SATA0TXN DD11 PDD12 GATEA20
(22) SATA_TXP0 AH6 V5
SATA0TXP DD12 PDD13
U1
R322 10K_4 DD13 PDD14
AG3 V2
R321 10K_4 SATA1RXN DD14 PDD15
AG4 U6
SATA1RXP DD15

IDE
T51 AJ4 PDA[2:0] (22)
SATA1TXN PDA0
T50 AJ3 AA4
SATA1TXP DA0 PDA1
AA1
R324 10K_4 DA1 PDA2

SATA
AF2 AB3
R323 10K_4 SATA2RXN DA2
AF1
SATA2RXP
T48 AE4 Y6 PDCS1# (22)
SATA2TXN DCS1#
SATA Disable T49 AE3 Y5 PDCS3# (22)
SATA2TXP DCS3#
1.Connect to GND: SATA[2:0]RXp/n , SATARBIAS , SATARBIAS# , SATA_CLKP , SATACLKN AB7 W4
2.NC: SATA[2:0]TXp/n , SATALED# (2) CLK_PCIE_SATA# SATA_CLKN DIOR# PDIOR# (22)
(2) CLK_PCIE_SATA AC6 W3 PDIOW# (22)
3.VccSATAPLL should be connected directly to Vcc1_5,Filter cap are not required SATA_CLKP DIOW#
Y2 PDDACK# (22)
4.BIOS disable DDACK#
AG1 Y3 IRQ14 (22)
B R296 24.9/F_4 SATA_BIAS SATARBIAS# IDEIRQ B
AG2 Y1 PDIORDY (22)
SATARBIAS IORDY
W5 PDDREQ (22)
L<500mils DDREQ
ICH8M REV 1.0

SB Strap HDA
XOR Chain Entrance Strap BIT_CLK_AUDIO ACZ_SDOUT R347 33_4
ACZ_SDOUT_AUDIO (29)
ICH8-M Internal VR Enable strap ICH8-M LAN100_SLP Strap R330 33_4
ACZ_SDOUT_HDMI (21)
(Internal VR for Vccsus1_05,VccSus1_5 and VccCL1_5) (Internal VR for VccLAN1_05 and VccCL1.05) ICH_RSV0 HDA_SDOUT Description
R331

INTVRMEN Low = Internal VR disable LAN100_SLP Low = Internal VR disable 0 0 RSVD *22_4
High = Internal VR enable(Default) High = Internal VR enable(Default)
ACZ_SYNC R560 33_4
ACZ_SYNC_AUDIO (29)
0 1 Enter XOR Chain
C330 R561 33_4
ACZ_SYNC_HDMI (21)
1 0 Normal opration(Default) *22p/50V_4

1 1 Set PCIE port config bit 1


ACZ_BCLK R563 33_4 BIT_CLK_AUDIO
BIT_CLK_AUDIO (29)
BIT_CLK_HDMI R562 33_4 BIT_CLK_HDMI
VCCRTC +3V BIT_CLK_HDMI (21)
VCCRTC

R332
A R309 R335 A
R289 *22_4 ACZ_RST# R302 33_4
ACZ_RST#_AUDIO (29)
332K/F_6 *1K_4
332K/F_6 R300 33_4
ACZ_RST#_HDMI (21)
ICH_INTVRMEN ACZ_SDOUT
LAN100_SLP C331
ICH_TP3 (16)
R307 *22p/50V_4

*0_4
R299
R566
Quanta Computer Inc.
*0_4
*1K_4
PROJECT : TE1
Size Document Number Rev
ICH8M HOST(1 of 4) 1A

Date: Thursday, September 20, 2007 Sheet 14 of 38


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SB-PCIE/USB/DMI
U37D
(27) PCIE_RXN1 P27 V27 DMI_RXN0 (6) A16 SWAP Override strap
PERN1 DMI0RXN
To New Card (27) PCIE_RXP1 P26
PERP1 DMI0RXP
V26 DMI_RXP0 (6)
C574 0.1u/10V_4 PCIE_TXN1_C N29 U29
(27) PCIE_TXN1 PETN1 DMI0TXN DMI_TXN0 (6)
C573 0.1u/10V_4 PCIE_TXP1_C N28 U28 PCI_GNT#3 Low = A16 swap override enabled
(27) PCIE_TXP1 PETP1 DMI0TXP DMI_TXP0 (6)

Direct Media Interface


High = Default
(25) PCIE_RXN2 M27 PERN2 DMI1RXN Y27 DMI_RXN1 (6)
To MINI-3 (25) PCIE_RXP2 M26 PERP2 DMI1RXP Y26 DMI_RXP1 (6)
C572 0.1u/10V_4 PCIE_TXN2_C L29 W29 GNT3# R469 *1K_4
(25) PCIE_TXN2 PETN2 DMI1TXN DMI_TXN1 (6)
C571 0.1u/10V_4 PCIE_TXP2_C L28 W28
(25) PCIE_TXP2 PETP2 DMI1TXP DMI_TXP1 (6)
D D
K27 AB26 ICH8 Boot BIOS select

PCI-Express
(25) PCIE_RXN3 PERN3 DMI2RXN DMI_RXN2 (6)
To MINI-2 (25) PCIE_RXP3 K26
PERP3 DMI2RXP
AB25 DMI_RXP2 (6)
C566 0.1u/10V_4 PCIE_TXN3_C J29 AA29
(25) PCIE_TXN3 PETN3 DMI2TXN DMI_TXN2 (6)
C563 0.1u/10V_4 PCIE_TXP3_C J28 AA28 PCI_GNT#0 SPI_CS#1 Boot BIOS Location
(25) PCIE_TXP3 PETP3 DMI2TXP DMI_TXP2 (6)

(25) PCIE_RXN4 H27 AD27 DMI_RXN3 (6)


PERN4 DMI3RXN +1.5V_PCIE 0 1 SPI(Default)
To MINI-4 (25) PCIE_RXP4 H26 PERP4 DMI3RXP AD26 DMI_RXP3 (6)
C249 0.1u/10V_4 PCIE_TXN4_C G29 AC29
(25) PCIE_TXN4 PETN4 DMI3TXN DMI_TXN3 (6)
C253 0.1u/10V_4 PCIE_TXP4_C G28 AC28
(25) PCIE_TXP4 PETP4 DMI3TXP DMI_TXP3 (6)
1 0 PCI
F27 T26 R268
(26) PCIE_RXN5 PERN5 DMI_CLKN CLK_PCIE_ICH# (2)
To LAN (26) PCIE_RXP5 F26 PERP5 DMI_CLKP T25 CLK_PCIE_ICH (2)
C243 0.1u/10V_4 PCIE_TXN5_C E29 24.9/F_4 55ohm 1 1 LPC
(26) PCIE_TXN5 PETN5 L<500mils
C244 0.1u/10V_4 PCIE_TXP5_C E28 Y23
(26) PCIE_TXP5 PETP5 DMI_ZCOMP
Y24 DMI_IRCOMP_R
DMI_IRCOMP
(25) PCIE_RXN6 D27
PERN6/GLAN_RXN SPI_CS1# R467 *1K_4
To MINI-1 (25) PCIE_RXP6 D26
PERP6/GLAN_RXP USBP0N
G3 USBP0- (26)
C235 0.1u/10V_4 PCIE_TXN6_C C29 G2 To USB BOARD
(25) PCIE_TXN6 PETN6/GLAN_TXN USBP0P USBP0+ (26)
C239 0.1u/10V_4 PCIE_TXP6_C C28 H5 GNT0# R244 *1K_4
(25) PCIE_TXP6 PETP6/GLAN_TXP USBP1N USBP1- (26)
USBP1P
H4 USBP1+ (26) To Finger Printer
T60 C23 H2 USBP2- (26)
SPI_CLK USBP2N
T56 B23 SPI_CS0# USBP2P H1 USBP2+ (26) To Bluetooth
SPI_CS1# E22 J3
T54 SPI_CS1# USBP3N USBP3- (19)

SPI
USBP3P
J2 USBP3+ (19) To Camera
T55 D23 SPI_MOSI USBP4N K5 USBP4- (26)
T57 F21 SPI_MISO USBP4P K4 USBP4+ (26) To Felica
K2 USBP5- (25)
USBOC#0 USBP5N
(26,28) USBOC#0 AJ19 OC0# USBP5P K1 USBP5+ (25) To WLAN
USBOC#1 AG16 L3
(27,28) USBOC#1 OC1#/GPIO40 USBP6N USBP6- (27)
USBOC#2 AG15 L2 To M/B USB
USBOC#3 AE15
OC2#/GPIO41 USB USBP6P
M5
USBP6+ (27)
OC3#/GPIO42 USBP7N USBP7- (27)
USBOC#4 AF15 M4 To M/B USB
C OC4#/GPIO43 USBP7P USBP7+ (27) C
USBOC#5 AG17 M2
OC5#/GPIO29 USBP8N USBP8- (25)
USBOC#6 AD12 M1 To TV
OC6#/GPIO30 USBP8P USBP8+ (25)
USBOC#7 AJ18 N3 +3V
OC7#/GPIO31 USBP9N USBP9- (27)
USBOC#8 AD14 N2 To New Card
OC8# USBP9P USBP9+ (27) RP73
USBOC#9 AH18 OC9#
F2 6 5
USBRBIAS# USB_RBIAS_PN SERR#
F3 7 4
USBRBIAS INTH# 8 3
ICH8M REV 1.0 REQ0# 9 2 INTF#
R249 +3V 10 1 INTE#
L<500mils
22.6/F_4 8.2KX8

+3V_S5
RP57

SB-PCI USBOC#4
USBOC#5
6
7
5
4 USBOC#3
USBOC#7 8 3 USBOC#8
U37B USBOC#9 9 2 USBOC#2
(23,24) AD[0..31]
AD0 D20 A4 REQ0# +3V_S5 10 1 USBOC#6
AD0 REQ0# REQ0# (24)
AD1 E19 GNT0#
AD2 D19
AD1 PCI GNT0# D7
E18 REQ1#
GNT0# (24)
8.2KX8
AD2 REQ1#/GPIO50 REQ1# (23)
AD3 A20 C18 GNT1#
AD3 GNT1#/GPIO51 GNT1# (23)
AD4 D17 B19 REQ2# USBOC#1 R274 8.2K_4 +3V_S5
AD5 AD4 REQ2#/GPIO52 GNT2#
A21 F18 T38
AD6 AD5 GNT2#/GPIO53 REQ3# USBOC#0 R564 8.2K_4
A19 AD6 REQ3#/GPIO54 A11 +3V_S5
AD7 C19 C10 GNT3#
AD7 GNT3#/GPIO55 T59
AD8 A18 +3V
AD9 AD8
B16 AD9 C/BE0# C17 CBE0# (23,24) RP75
AD10 A12 E15
AD10 C/BE1# CBE1# (23,24)
AD11 E16 F16 REQ1# 6 5
AD11 C/BE2# CBE2# (23,24)
AD12 A14 E17 DEVSEL# 7 4 INTG#
B AD12 C/BE3# CBE3# (23,24) B
AD13 G16 FRAME# 8 3 TRDY#
AD14 AD13 IRDY# STOP# REQ2#
A15 AD14 IRDY# C8 IRDY# (23,24) 9 2
AD15 B6 D9 +3V 10 1
AD15 PAR PAR (23,24)
AD16 C11 G6
AD16 PCIRST# PCIRST# (23,24)
AD17 A9 D16 DEVSEL# 8.2KX8 +3V
AD17 DEVSEL# DEVSEL# (23,24)
AD18 D11 A7 PERR#
AD18 PERR# PERR# (23) RP74
AD19 B12 B7 LOCK#
AD20 AD19 PLOCK# SERR# LOCK#
C12 AD20 SERR# F10 SERR# (23) 6 5
AD21 D10 C16 STOP# PERR# 7 4 INTB#
AD21 STOP# STOP# (23,24)
AD22 C7 C9 TRDY# R569 0_4 IRDY# 8 3 INTC#
AD22 TRDY# TRDY# (23,24) GFXRST# (18)
AD23 F13 A17 FRAME# INTD# 9 2 INTA#
AD23 FRAME# FRAME# (23,24)
AD24 E11 +3V 10 1 REQ3#
AD25 AD24 PLT_RST-R# R363 0_4
E13 AD25 PLTRST# AG24 PLTRST#_NB (6)
AD26 E12 B10 PCLK_ICH 8.2KX8
AD26 PCICLK PCLK_ICH (2)
AD27 D8 G7
AD27 PME# PCI_PME# (23,24)
AD28 A6
AD29 AD28
E8 AD29
AD30 D6 +3V_S5
AD31 AD30
A3 AD31

INTA# F9
Interrupt I/F F8 INTE# C342
(24) INTA# PIRQA# PIRQE#/GPIO2
INTB# B5 G11 INTF#
INTC# PIRQB# PIRQF#/GPIO3 INTG# 0.1u/10V_4
(23) INTC# C5 PIRQC# PIRQG#/GPIO4 F12
INTD# A10 B3 INTH# R234 *0_4
T58 PIRQD# PIRQH#/GPIO5 CRT_SENSE# (20,28)

5
ICH8M REV 1.0 PLT_RST-R# 2
4 PLTRST# (16,21,22,25,26,27,28)
1
PCI ROUTING R365

TABLE IDSEL INTERUPT DEVICE

3
100K_4 U23
A A
REQ0# / GNT0# AD17 INTA# OZ129T TC7SH08FU
REQ1# / GNT1# AD20 INTC# CB1410

Quanta Computer Inc.


PROJECT : TE1
Size Document Number Rev
ICH8M PCIE(2 of 4)/ BIOS 1A

Date: Thursday, September 20, 2007 Sheet 15 of 38


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SB-GPIO SCLK AJ26


U37C
AJ12 BOARD_ID3
(2,21,25,27) SCLK SMBCLK SATA0GP/GPIO21
SDATA AD19 AJ10 BOARD_ID2 CLKUSB_48 14M_ICH
(2,21,25,27) SDATA SMBDATA SATA1GP/GPIO19
CL_RST#1 AG21 AF11 GPIO36

SATA
GPIO
(25) CL_RST#1 LINKALERT# SATA2GP/GPIO36
SMLINK0 GPIO37 R248 R303

SMB
AC17 AG11
SMLINK1 SMLINK0 SATA3GP/GPIO37
AE19
+3V SMLINK1 14M_ICH *10_4 *33_4
AG9 14M_ICH (2)
RI# CLK14 CLKUSB_48
AF17 G5

Clocks
RI# CLK48 CLKUSB_48 (2)
T37 LPC_PD# F4 D3
SYS_RST# SUS_STAT#/LPCPD# SUSCLK T36 C242 C319
(3) SYS_RST# AD15
SYS_RESET# SLP_S3# R319 100_4
AG23 SUSB# (28)
SLP_S3# SLP_S4# R311 100_4 *6.8p/50V_4 *10p/50V_4
(6) PM_BMBUSY# AG12 AF21 SUSC# (28)
R359 R339 BMBUSY#/GPIO0 SLP_S4# SLP_S5#
AD18
*10K_4 *10K_4 SMB_ALERT# SLP_S5# T45
AG22
D SMBALERT#/GPIO11 D
AH27
S4_STATE#/GPIO26 T67

GPIO
(2) PM_STPPCI# AE20
STP_PCI#/GPIO15 ICH_PWROK

SYS
(2) PM_STPCPU# AG18 AE23
STP_CPU#/GPIO25 PWROK
CLKRUN# AH11 AJ14 PM_DPRSLPVR_R R546 100_4 PM_DPRSLPVR
(24,28) CLKRUN# CLKRUN#/GPIO32 DPRSLPVR/GPIO16 PM_DPRSLPVR (6,33)

Power MGT
PCIE_WAKE# AE17 AE21 PM_BATLOW#_R
(25,26,27) PCIE_WAKE# WAKE# BATLOW#
SERIRQ AF12
(23,25,28) SERIRQ SERIRQ
THERM_ALERT# AC13 C2 DNBSWON#
(3) THERM_ALERT# THRM# PWRBTN# DNBSWON# (28)
PM_LAN_ENABLE_R R582 *10K_4 +3V
VR_PWRGD_CLKEN AJ20 AH20 PM_LAN_ENABLE_R R581 *0_4 PLTRST#
VRMPWRGD LAN_RST# PLTRST# (15,21,22,25,26,27,28)
T52 ICH_TP7 AJ22 AG27 RSMRST#_R R583 10K_4
TP7 RSMRST#
KBSMI#_ICH AJ8 E1 Internal LAN disable. 10K PD
TACH1/GPIO1 CK_PWRGD CK_PWRGD (2)
(29) Port_C# AJ9 ECPWROK (28)
R326 0_4 TACH2/GPIO6 ECPWROK R229 0_4
(30) SB_GPIO7 AH9 E3 MPWROK (6)
SCI# TACH3/GPIO7 CLPWROK +3V_S5 +3V
(28) SCI# AE16
GPIO12 GPIO8
AC19 AJ25
BOARD_ID0 GPIO12 SLP_M# T68
AG8
BOARD_ID1 TACH0/GPIO17
AH12 F23 CL_CLK0 (6)
LOW_DET GPIO18 CL_CLK0 R337 R243
AE11 AE18 CL_CLK1 (25)
BOARD_ID4 GPIO20 CL_CLK1

GPIO
Controller Link
AG10
R325 0_4 SCLOCK/GPIO22 3.24K/F_6 3.24K/F_6
(30) SB_GPIO27 AH25 F22 CL_DATA0 (6)
R291 0_4 QRT_STATE0/GPIO27 CL_DATA0
(30) FM_INT AD16 AF19 CL_DATA1 (25)
GPIO35 QRT_STATE1/GPIO28 CL_DATA1
AG13
RST_HDD# SATACLKREQ#/GPIO35 CL_VREF0_SB
(22) RST_HDD# AF9 D24
ICH_GPIO39 SLOAD/GPIO38 CL_VREF0 CL_VREF1_SB
AJ11 AH23
ICH_GPIO48 SDATAOUT0/GPIO39 CL_VREF1
AD10
SDATAOUT1/GPIO48
AJ23 CL_RST#0 (6)
SPKR CL_RST#
(27) SPKR AD9
SPKR ICH_GPIO24 R313 C315 R242 C240
AJ27
C MCH_ICH_SYNC#_R MEM_LED/GPIO24 HDPACT C

MISC
R557 0_4 AJ13 AJ24
(6) MCH_ICH_SYNC# MCH_SYNC# ME_EC_ALERT/GPIO10 HDPACT (22)
AF22 ICH_GPIO14 453/F_4 0.1u/10V_4 453/F_4 0.1u/10V_4
EC_ME_ALERT/GPIO14 HDPINT
(14) ICH_TP3 AJ21 AG19 HDPINT (22)
TP3 WOL_EN/GPIO9
ICH8M REV 1.0

+3V_S5

C232 0.1u/10V_4

5
DELAY_VR_PWRGOOD 1
+3V (3,6,33) DELAY_VR_PWRGOOD
4 ICH_PWROK
ECPWROK 2
C329 0.1u/10V_4 U14

3
U18 R233 100K_4
1 5 TC7SH08FU
(33) VR_PWRGD_CK410# 2
3 4 VR_PWRGD_CLKEN

NC7SZ04
R295 *0_4

R565 100K_4

Q22
MMBT3906

No Reboot strap +3V +3V +3V +3V +3V +3V RSMRST#_R 3 1 RSMRST# (28)
B B
SPKR Low = Default

2
High = No Reboot +3V R344 R554 R549 R555 R293 R341 R306
10K_4 R318 4.7K_4 +3V_S5
10K_4 *10K_4 *10K_4 10K_4 10K_4 10K_4

2
+3V_S5
SPKR R286 *10K_4 BOARD_ID4 BOARD_ID3 BOARD_ID2 BOARD_ID1 BOARD_ID0 LOW_DET D23
LOW_DET (26)
3 BAV99
GPIO35 R314 10K_4
SMLINK0 R272 10K_4
THERM_ALERT# R282 8.2K_4 R345 R553 R548 R556 R297 R342

1
SMLINK1 R290 10K_4
SERIRQ R308 10K_4 *10K_4 10K_4 10K_4 *10K_4 *10K_4 *10K_4

2
SYS_RST# R273 10K_4
CLKRUN# R551 8.2K_4 D27
3 BAV99
MCH_ICH_SYNC#_R R558 *10K_4 DNBSWON# R235 *10K_4

CL_RST#1 R310 10K_4 Internal Pull up R364

1
ICH_GPIO24 R571 *10K_4 2.2K_4
KBSMI#_ICH R580 10K_4
HDPACT R568 *10K_4 Board ID ID4 ID3 ID2 ID1 ID0 M/L
SCI# R304 10K_4
RI# R275 10K_4 NEW CARD H
ICH_GPIO48 R285 10K_4 CARD BUS L
RST_HDD# R343 10K_4 CCFL Panel H
SCLK R570 2.2K_4 LED Panel L
GPIO36 R340 8.2K_4
SDATA R279 2.2K_4 W/ G-SENSOR H
GPIO37 R550 8.2K_4 W/O G-SENSOR L
SMB_ALERT# R567 10K_4
A W/ TV H A
PCIE_WAKE# R346 1K_4 W/O TV L
PM_BATLOW#_R R270 8.2K_4 W/ HDMI H
PM_DPRSLPVR R573 100K_4 W/O HDMI L
GPIO12 R280 10K_4
ICH_PWROK R294 10K_4 Main Strem H
Low Cost L
ICH_GPIO14 R298 10K_4 Quanta Computer Inc.
HDPINT R305 *10K_4
PROJECT : TE1
ICH_GPIO39 R552 10K_4 Size Document Number Rev
ICH8M GPIO(3 of 4) 1A

Date: Thursday, September 20, 2007 Sheet 16 of 38


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+3V_S5 +3V
VCCRTC
C310 C311 C309 6uA +1.05V

2
D19 D20 1130mA
1u/6.3V_4 0.1u/10V_4 0.1u/10V_4 U37F
+5V AD25 A13 +1.05V_SB R232 0_1206
PDZ5.6B PDZ5.6B VCCRTC VCC1_05[01] U37E
B13
VCC1_05[02]
1mA A16
V5REF[1] VCC1_05[03]
C13 A23
VSS[001] VSS[099]
K7

1
+5V_S5 R252 R257 +5VREF_SB T7 C14 C270 C284 A5 L1
10_6 C259 100/F_6 V5REF[2] VCC1_05[04] VSS[002] VSS[100]
D14 AA2 L13
C296 +5VREF_SUS_SB VCC1_05[05] 0.1u/10V_4 10u/10V_8 VSS[003] VSS[101]
G4 E14 AA7 L15
0.1u/10V_4 V5REF_SUS VCC1_05[06] VSS[004] VSS[102]
F14 A25 L26
1u/10V_6 VCC1_05[07] VSS[005] VSS[103]
AA25 G14 AB1 L27
VCC1_5_B[01] VCC1_05[08] +1.5V VSS[006] VSS[104]
AA26 L11 AB24 L4
VCC1_5_B[02] VCC1_05[09] VSS[007] VSS[105]
1mA AA27
VCC1_5_B[03] VCC1_05[10]
L12 23mA AC11
VSS[008] VSS[106]
L5
D 657mA AB27
VCC1_5_B[04] VCC1_05[11]
L14 L27 AC14
VSS[009] VSS[107]
M12 D
0818 Hsin modify AB28 L16 VCCDMIPLL_ICH VCCDMIPLL_+1.5V R254 1_8 AC25 M13
Change CAP value from 0.1u to 1u +1.5V_PCIE VCC1_5_B[05] VCC1_05[12] VSS[010] VSS[108]
AB29 L17 AC26 M14
follow BL5 REV_04 VCC1_5_B[06] VCC1_05[13] PBY160808T-301Y-N_6 VSS[011] VSS[109]
D28 L18 AC27 M15
VCC1_5_B[07] VCC1_05[14] C285 C289 VSS[012] VSS[110]
D29 M11 AD17 M16
L22 FBMJ2125HS420-T_8 VCC1_5_B[08] VCC1_05[15] VSS[013] VSS[111]

CORE
+1.5V E25 M18 AD20 M17
VCC1_5_B[09] VCC1_05[16] 0.01u/16V_4 10u/10V_6 VSS[014] VSS[112]
E26 P11 AD28 M23
VCC1_5_B[10] VCC1_05[17] VSS[015] VSS[113]
E27 P18 AD29 M28
+ C267 C265 C271 C300 VCC1_5_B[11] VCC1_05[18] VSS[016] VSS[114]
F24 T11 AD3 M29
VCC1_5_B[12] VCC1_05[19] +1.25V VSS[017] VSS[115]
F25 T18 AD4 M3
VCC1_5_B[13] VCC1_05[20] VSS[018] VSS[116]
*330u/2.5V_3528 22u/6.3V_8 22u/6.3V_8 2.2u/6.3V_6 G24
VCC1_5_B[14] VCC1_05[21]
U11 50mA AD6
VSS[019] VSS[117]
N1
H23 U18 AE1 N11
VCC1_5_B[15] VCC1_05[22] +1.25V_DMI R513 0_8 +1.05V VSS[020] VSS[118]
H24 V11 AE12 N12
VCC1_5_B[16] VCC1_05[23] VSS[021] VSS[119]
J23 V12 AE2 N13
VCC1_5_B[17] VCC1_05[24] VSS[022] VSS[120]
J24 V14 AE22 N14
+1.5V VCC1_5_B[18] VCC1_05[25] C579 R258 0_6 VSS[023] VSS[121]
K24 V16 AD1 N15
VCC1_5_B[19] VCC1_05[26] VSS[024] VSS[122]
K25 V17 AE25 N16
VCC1_5_B[20] VCC1_05[27] 10u/10V_8 VSS[025] VSS[123]
L23 V18 AE5 N17
VCC1_5_B[21] VCC1_05[28] VSS[026] VSS[124]
47mA L24
VCC1_5_B[22]
C304 C294 C293 AE6
VSS[027] VSS[125]
N18
+1.5V_SATA R579 +1.5V_APLL_RR +1.5V_APLL

VCCA3GP
R578 L25 R29 AE9 N26
0_8 0_8 VCC1_5_B[23] VCCDMIPLL 0.1u/10V_4 0.1u/10V_4 4.7u/10V_6 VSS[028] VSS[126]
M24 AF14 N27
L53 C606 C613 VCC1_5_B[24] VSS[029] VSS[127]
M25 AE28 AF16 N4
10uh_8 VCC1_5_B[25] VCC_DMI[1] +1.05V_V_CPU_IO VSS[030] VSS[128]
N23 AE29 AF18 N5
VCC1_5_B[26] VCC_DMI[2] +3V VSS[031] VSS[129]
CV01001MN08 10u/10V_6 1u/10V_6 N24
VCC1_5_B[27] 1mA AF3
VSS[032] VSS[130]
N6
N25 AC23 AF4 P12
VCC1_5_B[28] V_CPU_IO[1] VSS[033] VSS[131]
P24 AC24 AG5 P13
VCC1_5_B[29] V_CPU_IO[2] VSS[034] VSS[132]
P25 AG6 P14
VCC1_5_B[30] +V3.3_DMI_ICH R577 0_6 VSS[035] VSS[133]
R24 AF29 AH10 P15
VCC1_5_B[31] VCC3_3[01] VSS[036] VSS[134]
R25 AH13 P16
VCC1_5_B[32] +V3.3_SATA_ICH R276 0_6 VSS[037] VSS[135]
R26 AD2 AH16 P17
VCC1_5_B[33] VCC3_3[02] VSS[038] VSS[136]
R27 AH19 P23
VCC1_5_B[34] +V3.3S_VCCPCORE_ICH VSS[039] VSS[137]
T23 AC8 AH2 P28
C VCC1_5_B[35] VCC3_3[03] VSS[040] VSS[138] C
T24 AD8 AF28 P29
VCC1_5_B[36] VCC3_3[04] VSS[041] VSS[139]

VCCP_CORE
T27 AE8 C306 C614 AH22 R11
VCC1_5_B[37] VCC3_3[05] VSS[042] VSS[140]
T28
VCC1_5_B[38] VCC3_3[06]
AF8 VCC3_3:278mA AH24
VSS[043] VSS[141]
R12
T29 0.1u/10V_4 0.1u/10V_4 AH26 R13
C257 VCC1_5_B[39] +V3.3S_IDE_ICH VSS[044] VSS[142]
U24 AA3 AH3 R14
VCC1_5_B[40] VCC3_3[07] VSS[045] VSS[143]
U25 U7 AH4 R15
1u/10V_6 VCC1_5_B[41] VCC3_3[08] C303 VSS[046] VSS[144]
V23 V7 AH8 R16
VCC1_5_B[42] VCC3_3[09] VSS[047] VSS[145]
V24 W1 AJ5 R17
VCC1_5_B[43] VCC3_3[10] 0.1u/10V_4 R288 0_6 VSS[048] VSS[146]
V25 W6 B11 R18
VCC1_5_B[44] VCC3_3[11] VSS[049] VSS[147]

IDE
W25 W7 B14 R28
VCC1_5_B[45] VCC3_3[12] R269 0_6 VSS[050] VSS[148]
Y25 Y7 B17 R4
VCC1_5_B[46] VCC3_3[13] VSS[051] VSS[149]
B2 T12
+V3.3S_PCI_ICH R231 0_6 VSS[052] VSS[150]
AJ6 A8 B20 T13
VCCSATAPLL VCC3_3[14] VSS[053] VSS[151]
B15 B22 T14
VCC3_3[15] VSS[054] VSS[152]
AE7 B18 B8 T15
C258 VCC1_5_A[01] VCC3_3[16] VSS[055] VSS[153]
AF7 B4 C24 T16
VCC1_5_A[02] VCC3_3[17] VSS[056] VSS[154]

ARX
AG7 B9 C26 T17
1u/10V_6 VCC1_5_A[03] VCC3_3[18] C238 C245 C236 VSS[057] VSS[155]
AH7 C15 C27 T2
VCC1_5_A[04] VCC3_3[19] VSS[058] VSS[156]
AJ7 D13 C6 U12
VCC1_5_A[05] VCC3_3[20] VSS[059] VSS[157]

PCI
D5 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 D12 U13
VCC3_3[21] VSS[060] VSS[158]
AC1 E10 D15 U14
VCC1_5_A[06] VCC3_3[22] VSS[061] VSS[159]
AC2 E7 D18 U15
VCC1_5_A[07] VCC3_3[23] VSS[062] VSS[160]
ATX

AC3 F11 D2 U16


VCC1_5_A[08] VCC3_3[24] VSS[063] VSS[161]
VCC1_5_A:1560mA AC4
VCC1_5_A[09] 32mA D4
VSS[064] VSS[162]
U17
AC5 AC12 +3V_1.5V_HDA_IO_ICH R271 0_6 +3V E21 U23
VCC1_5_A[10] VCCHDA VSS[065] VSS[163]
32mA E24
VSS[066] VSS[164]
U26
AC10 AD11 +VCCSUSHDA R266 0_6 +3V_S5 E4 U27
VCC1_5_A[11] VCCSUSHDA C307 VSS[067] VSS[165]
AC9 E9 U3
VCC1_5_A[12] TP_VCCSUS1_05_ICH_1 C302 VSS[068] VSS[166]
J6 F15 U5
VCCSUS1_05[1] TP_VCCSUS1_05_ICH_2 0.1u/10V_4 VSS[069] VSS[167]
AA5 AF20 E23 V13
VCC1_5_A[13] VCCSUS1_05[2] 0.1u/16V_6 VSS[070] VSS[168]
AA6 F28 V15
R245 0_6 +1.5V_USB VCC1_5_A[14] TP_VCCSUS1_5_ICH_1 VSS[071] VSS[169]
AC16 F29 V28
B VCCSUS1_5[1] VSS[072] VSS[170] B
G12 F7 V29
C272 VCC1_5_A[15] TP_VCCSUS1_5_ICH_2 +3V_S5 VSS[073] VSS[171]
G17 J7 G1 W2
VCC1_5_A[16] VCCSUS1_5[2] VSS[074] VSS[172]
H7 E2 W26
0.1u/10V_4 VCC1_5_A[17] +V3.3A_ICH R241 0_6 VSS[075] VSS[173]
C3 G10 W27
VCCSUS3_3[01] VSS[076] VSS[174]
AC7 G13 Y28
VCC1_5_A[18] VSS[077] VSS[175]
AD7 AC18 G19 Y29
VCC1_5_A[19] VCCSUS3_3[02] VSS[078] VSS[176]
10mA VCCSUS3_3[03]
AC21 C312 C308 G23
VSS[079] VSS[177]
Y4
D1 AC22 G25 AB4
VCCUSBPLL VCCSUS3_3[04] VSS[080] VSS[178]
VCCPSUS

AG20 0.1u/10V_4 22n/16V_4 G26 AB23


VCCSUS3_3[05] VSS[081] VSS[179]
F1 AH28 G27 AB5
VCC1_5_A[20] VCCSUS3_3[06] VSS[082] VSS[180]
USB CORE

L6 H25 AB6
VCC1_5_A[21] VSS[083] VSS[181]
C248 L7
VCC1_5_A[22] VCCSUS3_3[07]
P6 VCCSUS3_3:177mA H28
VSS[084] VSS[182]
AD5
M6 P7 H29 U4
0.1u/10V_4 VCC1_5_A[23] VCCSUS3_3[08] VSS[085] VSS[183]
M7 C1 H3 W24
VCC1_5_A[24] VCCSUS3_3[09] +V3.3A_USB_ICH R260 0_8 VSS[086] VSS[184]
N7 H6
+1.5V_SATA VCCSUS3_3[10] VSS[087]
W23 P1 J1 A1
VCC1_5_A[25] VCCSUS3_3[11] VSS[088] VSS_NCTF[01]
P2 J25 A2
TP_VCCLAN1_05_ICH_1 VCCSUS3_3[12] C283 VSS[089] VSS_NCTF[02]
F17 P3 J26 A28
VCCLAN1_05[1] VCCSUS3_3[13] VSS[090] VSS_NCTF[03]
VCCPUSB

TP_VCCLAN1_05_ICH_2 G18 P4 J27 A29


VCCLAN1_05[2] VCCSUS3_3[14] TP_VCCLAN1_05_ICH_1 VSS[091] VSS_NCTF[04]
18mA VCCSUS3_3[15]
P5 4.7u/10V_6 C250 0.1u/16V_6 J4
VSS[092] VSS_NCTF[05]
AH1
+3V R247 0_6 +3V_VCCLAN F19 R1 TP_VCCLAN1_05_ICH_2 C256 0.1u/16V_6 J5 AH29
VCCLAN3_3[1] VCCSUS3_3[16] VSS[093] VSS_NCTF[06]
G20 R3 K23 AJ1
C247 VCCLAN3_3[2] VCCSUS3_3[17] TP_VCCSUS1_05_ICH_1 C263 0.1u/16V_6 VSS[094] VSS_NCTF[07]
R5 K28 AJ2
+1.5V_VCCGLANPLL VCCSUS3_3[18] TP_VCCSUS1_05_ICH_2 C314 0.1u/16V_6 VSS[095] VSS_NCTF[08]
A24 R6 K29 AJ28
0.1u/10V_4 VCCGLANPLL VCCSUS3_3[19] VSS[096] VSS_NCTF[09]
K3 AJ29
TP_VCCCL1_05_ICH TP_VCCSUS1_5_ICH_1 VSS[097] VSS_NCTF[10]
GLAN POWER

A26 G22 T44 K6 B1


VCCGLAN1_5[1] VCCCL1_05 TP_VCCSUS1_5_ICH_2 VSS[098] VSS_NCTF[11]
23mA A27
VCCGLAN1_5[2] T41 VSS_NCTF[12]
B29
L40 B26 A22 VCCCL1_5_INT_ICH TP_VCCCL1_05_ICH
VCCGLAN1_5[3] VCCCL1_5 T39
+1.5V R466 1_8 +1.5V_VCCGL PBY160808T-301Y-N_6 B27 ICH8M REV 1.0
VCCGLAN1_5[4] +V3.3M_ICH C539 C537
B28 F20
C540 C538 VCCGLAN1_5[5] VCCCL3_3[1]
G21
VCCCL3_3[2] 1u/10V_6 0.1u/10V_4
B25
A 10u/10V_6 2.2u/6.3V_6 VCCGLAN3_3 A
ICH8M REV 1.0

80mA
+1.5V_PCIE
64mA
C254
1mA R251 0_6
4.7u/10V_6
R468 0_6 +3V_GLAN
+3V
Quanta Computer Inc.
+3V
PROJECT : TE1
Size Document Number Rev
ICH8M Power(4 of 4) 1A

Date: Friday, September 21, 2007 Sheet 17 of 38


5 4 3 2 1

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5 4 3 2 1

VGA/B conn
CN31
PEG_TXN15 2 1 PEG_RXN15
(6) PEG_TXN15 PEG_TXP15 2 1 PEG_RXP15 PEG_RXN15 (6)
(6) PEG_TXP15 4 3 PEG_RXP15 (6)
4 3
6 5
PEG_TXN14 6 5 PEG_RXN14
(6) PEG_TXN14 8 7 PEG_RXN14 (6)
PEG_TXP14 8 7 PEG_RXP14
(6) PEG_TXP14 10 9 PEG_RXP