Variables and Sequential Statements

Dr DC Hendry

February 17, 2006

1 Variables

In our code so far we have used signals such as x, Q and so on. The distinguishing feature
of a signal is that it has the delay semantics associated with real signals on actual wires.
Remember that:

In a signal assignment such as x <= y;, x does not take on the value of y until after
one time.
The sequential statements in a process, unless a wait statement intervenes, are all
executed at the same time, without the passage of even time.

Now consider the following process, remember that the assignment statements within a
process are sequential assignments, not concurrent assignments. Each of the signals x, y
and z are integers.
xyz : process
begin
x <= y;
z <= x;
wait on y;
end process xyz;

Suppose that at time 10 nS the signal y changes value to 5, and that x at that point has
the value 10. Then at time 10 nS the process starts execution following the wait statement.
Since the wait statement is the last statement of the process, the process immediately starts
execution again from the top. So at time 10 nS x is scheduled to be updated to the value
5 at time 10 nS + . Next z, at time 10 nS, is scheduled to be updated at time 10 nS +
with the current value of x, so z is scheduled to be updated at time 10 nS + to the value
10, not 5.

This behaviour is actually representative of real hardware in certain circumstances as we

shall see later, but this behaviour is certainly not useful for constructing all sequential
behaviours.

VHDL provides an alternative to signals, variables which do not have the hardware related
behaviout of signals, but instead, behave like the variables we are used to in a language
 EG/ES 3560

such as C. Variables are intended for use only within the sequential bodies of processes
(and within procedures and functions which we will not study). Variables may be declared
within the declarations section of a process (after the process line, and before the begin).
Assignments to variables use an alternative operator, rather than <=, VHDL uses :=.

Note that assignments may be made between variables and signals, and that all the types
available for one are available for the other. The next example shows a typical simulation
model using variables. Suppose that the enclosing architecture body provides the signal
count q of type integer and the clock signal of type std logic.

assume signal count q

declared elsewhere
ct : process (clk)
variable c : integer;
begin
if (clkevent and
clk = 1) then
c := count q;
if (c > 57) then
c := 0; 10
else
c := c + 1;
end if ;
count q <= c;
end if ;
end process ct;

This provides a counter which counts up from 0 to 57 and then back to 0 and so on. Its not
too difficult to make this a synthesisable design, we just need a few more VHDL concepts.

The process uses a sensitivity list of just the clk signal. When clk changes value the
process runs from the top, the if statement ensures that only rising edges of the clock
cause the counter to count. We then copy the signal count q into the variable c. Note that
c is immediately updated to the current value of count q. The next if then updates c
accordingly. Finally, count q is scheduled to be updated to the value of c.

The if statement is an example of a sequential statement that may be used within a process
body. There are a number of sequential statement available within such a body. We will
start with the if statement however.

2 Sequential IF Statement

The VHDL IF statement comes in three forms. The simplest form is:

if <condition> then
<true-statements>
.
.
end if;

Revision : 1.2 Page 2 Dr DC Hendry

 EG/ES 3560

If <condition> is true then the list of <true-statements> between the then and the end
if is executed.

The second form includes an else clause.

if <condition> then
<true-statements>
.
.
else
<false-statements>
.
.
end if;

The third form includes an elsif clause or clauses:

if <condition-1> then
<true-statements-1>
.
elsif <condition-2>
<true-statements-2>
.
elsif ...
.
else
<all-false-statements>
.
end if;

Note the rather immemorable syntax, its elsif NOT else if, despite the use of end if.

Although the <condition> parts dont need to be in round brackets many designers use
round brackets anyway. The <condition> may be built with the usual comparison operators
(see the online reference pages for details).

3 Loops

There are two forms of loop available, while loops and for loops. Lets note now that while
loops are not synthesisable with the majority of todays synthesis tools, for loops may be
synthesised with care.

Revision : 1.2 Page 3 Dr DC Hendry

3.1 While Loop EG/ES 3560

3.1 While Loop

The syntax of the while loop is:

while <condition> loop
sequence of statements
.
end loop;

The sequential statements between loop and end loop are repeated until the <condition>
is false. As has been said this statement is not usually synthesisable, and so use it only for
testbenches.

3.2 For Loop

The for loop is normally synthesisable and very useful for expressing combinational logic.
Here is the syntax:

for loop parameter in range loop

sequence of statements
.
end loop;

The loop parameter should not be previously defined as a signal or as a variable. The
type of loop parameter is determined from the range. The range may be expressed using
downto or to, or often, by using an attribute of an array.

Some examples:

for n in HIGH
downto 0 loop
.
.
end loop;

Note that n should not be declared elsewhere.

signal x :
std logic vector(15 downto 0);
.
p : process
begin
for n in xrange loop#
.
.
end loop;
end process p; 10

Revision : 1.2 Page 4 Dr DC Hendry

3.3 Next Statement EG/ES 3560

In this case n takes the values 15 downto 0.

Here is a complete example which calculates the parity bit or an input vector. Note the use
of the attribute range which permits the design to accommodate any size of input vector.

Parity Example:

entity parity is
port(
inpacket : in std logic vector;
p : out std logic);
end entity parity;

architecture rtl of parity is

begin
pp : process(inpacket)
variable pv : std logic;
begin
pv := 0;
for n in inpacketrange loop
pv := pv xor inpacket(n);
end loop;
p <= pv; 10
end process pp;

end rtl;

3.3 Next Statement

The next statement may be used to immediately start the next iteration of a loop. The
syntax is simply:
next;

or
next when <condition>;

3.4 Exit Statement

The exit statement terminates the loop immediately, the syntax is:
exit;

or
exit when <condition>;

Revision : 1.2 Page 5 Dr DC Hendry

 EG/ES 3560

4 Case Statement

The case statement permits a choice of a number of alternatives based on a signal or variable
which has a discrete number of alternatives. All possible alternatives must be given, or the
final clause in the case statement must be a when others. Here is an example, assume that
sel is of type std logic vector(1 downto 0). The design is for a four way multiplexor:

case sel is
when 00 =>
y <= in0;
when 01 =>
y <= in1;
when 10 =>
y <= in2;
when others =>
y <= in3;
end case; 10

This statement is important in that certain synthesis tools rely on the case statement to
infer multiplexors.

Revision : 1.2 Page 6 Dr DC Hendry