EE 5171 Fall, 2005

Final Exam

1) As part of an experiment you oxidize some metal in an oven containing pure O2 at one
atmosphere. The oven temperature is 1100 oC. Your oxide thickness measurements are
as listed and plotted below. It is determined that the oxide thickness does not depend on
the gas flow in the reactor. You can assume no rapid growth regime.
a. What are A (in nm) and B (in nm2/sec) for this oxidation? Be sure to indicate
how you solved the equations.
b. Is this information sufficient to be able to calculate the diffusion coefficient of O2
in the metal oxide if you knew the density of oxygen atoms in the solid? Why or
why not?

Time (sec) Thickness (nm)

0. 0.
120. 12.9
300. 27.8
600. 47.1
1200. 76.6
1800. 100.0
3600. 153.9
7200. 231.3
14400. 341.6
36000 561.3
72000 809.5

400

300
Thickness (nm)

200

100

0
0 2000 4000 6000 8000 10000 12000 14000 16000

Time (sec)
2a) An immersion lithography tool is available that uses an ArF laser, has a spatial coherence of
1.0, and a numerical aperture of 0.9. If this machine is to be used to produce a minimum feature
size of 90 nm (0.090 m) without the use of phase shift or other contrast enhancement
techniques, what resist contrast is required?
2b) What is the depth of focus (depth of field) for this system in microns?

3a) A state of the art CMOS device has a source/drain diffusion sheet resistance of 800 ohms/sq,
and a CoSi2 sheet resistance of 20 ohms/sq. The metal contact is 90 nm wide and the distance
from the edge of this contact to the edge of the reachthrough is 120 nm. If the barrier height to n-
type silicon is 0.6 V in both cases, the effective mass is 1.1 mo, the surface doping concentration
is 2x1020 cm-3, the device (and contact) are 1 micron wide, and Ao is 2x10-11 ohm-cm2, find the
change in the resistance from the edge of the contact to the edge of the reachthrough for an
unsilicided device and for a silicided device.

4) The following is part of a process sequence for a GaAs self aligned gate (T-gate) structure. In
one or two sentences, explain the significance of the steps marked with a star (*). You can draw
a picture if it helps, but this is not required.

Starting material: Semi insulating undoped GaAs

Epitaxy: n-type GaAs 0.2 m thick, doping concentration 2x1016 cm-3)
Sputter: 0.2 m thick TiW alloy
Sputter: 0.1 m thick aluminum
Photolithography: Mask 1
Etch: Reactive ion etch Al in Cl2/BCl3
Etch: Reactive ion etch TiW alloy in CF4
Strip resist
*Etch: High pressure plasma etch TiW alloy in CF4
Implant: Silicon, Dose = 1x1015 cm-3, energy = 30 keV
*Plasma enhanced CVD: Si3N4, 0.2 m thick
Anneal; N2, 800 oC, 10 seconds
Strip: nitride
Photolithography: Mask 2
*Evaporate: 0.1 m AuGe alloy
Evaporate: 0.05 m Ni
*Strip resist using solvent and ultrasonic agitation
Anneal: N2, 500 oC, 30 seconds
Photolithography: Mask 3
*Implant: hydrogen, dose = 3x1014 cm-2, energy = 60 keV
Add interconnect to complete

5) Consider using a square single crystal silicon membrane as an accelerometer. The dimensions
of the membrane are: a=1000 m and t=10 m. Note that the pressure that the membrane
will experience is mA/a2, where A is the acceleration and m is the mass of the membrane.
For an acceleration of 20g, (196 m/sec2),
a. Find the maximum deflection in m.
b. Find the maximum longitudinal stress in Pa.
c. Is this more sensitive or less sensitive than a cantilever of similar dimensions?
 EE 5171 Fall, 2004
Final Exam

1) For a particular process, one needs to form an n-well that is one micron deep. This is
done by implanting silicon with phosphorus at a dose of 1013 cm-2 at a very low energy.
The surface of the wafer is sealed to prevent any loss of phosphorus and an anneal is
done at 1100 oC. Assume that, before the implant, the wafer had a uniform concentration
of 1015 cm-3 of boron and that intrinsic diffusion coefficients can be used.
a. How long should the anneal be done?
b. What is the concentration of phosphorus at the surface after the anneal?

2) An areal image of a single aperture is given by the following equation:

I = 50 mW/cm2 * (1 m2 x2) / 1 m2 for -1 m < x < 1 m, and
I=0 everywhere else
This image is exposed using a resist whose contrast curve is shown in Figure 8.7a (D0=10
mJ/cm2 and D100=100 mJ/cm2). For a three second exposure,
a. Find the positions (range of x) at which the resist thickness is zero.
b. Find the positions (values of x) at which the resist thickness is half of the original
value.
c. Roughly sketch the resist profile for -2 m < x < 2 m

3) At very small dimensions, TiSi2 does not tend to go through the phase transformation
from C49 to C54. The two materials have a resistivity of 60 -cm and 15 -cm,
respectively. For a 0.1 micron gate length device, the contact length is 0.1 micron, the
distance from the edge of the contact to the edge of the silicide is 0.15 microns, the
thickness of the silicide is 30 nm (300 ) and the source/drain sheet resistance without
the silicide is 500 /. If the transistor and contact width is 1.0 microns, how much of a
resistance reduction is obtained by obtaining the lower resistance phase of the self
aligned silicide. Assume RC=10-7 -cm2. (For comparison, the resistance of the
conducting channel is about 160 .) Hint: do not confuse resistivity and sheet
resistance. Refer to chapter 1 if you dont remember.

4) An accelerometer is made from a single crystal silicon cantilever beam. It is designed to

be used as a sensor for air bag deployment in automobiles. The beam dimensions are
1000 m long, 20 m wide, and 5 m thick. The beam uses a resistor at the base of the
cantilever (maximum stress location) oriented along the <110> direction (maximum
response). Note that the force is the mass times the acceleration. The values that you
need are in Chapter 19 or in Appendix II.
a. If the airbag is to deploy at a 10 g deceleration (1 g = 9.8 m/sec2), what R/R
would one have to sense?
b. What is the maximum deflection corresponding to this deceleration?
5) Consider the self aligned gate GaAs MESFET process listed below. There are five fatal
mistakes in the process. These mistakes will prevent device and/or circuit operation.
Find three of them.
Starting wafer: Semi insulating GaAs
Epitaxial growth: n-type GaAs, ND=1017 cm-3, thickness = 0.2 microns
Mask 1: defines gate electrode
Evaporate Ti/Pt/Au
Liftoff
Deposit SiO2, thickness=0.2 microns
RIE SiO2
Implant Zn, 4x1010 cm-2, 30 keV
Deposit PECVD Si3N4 thickness = 0.1 microns
Anneal, 1250 C, 15 seconds
Strip silicon nitride
Mask 2: Ohmic contact opening
Evaporate AuGe, thickness=0.05 microns
Evaporate Ni, thickness=0.05 microns
Evaporate Au, thickness=0.2 microns
Liftoff
Mask 3: Isolation
Implant hydrogen, 2x108 cm-2, 10 keV
Strip resist

EE 5171 Fall, 2003

Final Exam

1) Assume that one wants to grow a thick (1 micron) thermal oxide on silicon using only
oxygen. The maximum temperature allowed in the furnace is 1200 C.
a. Find amount of oxide grown after 8 hours at one atmosphere of O2, starting from
a bare wafer.
b. After part a was completed, the wafer was inserted into another furnace operating
at 50 atmospheres of oxygen at 1100 C. How much additional time is required
under these conditions to bring the total oxide thickness up to one micron.

2) Manufacturers are now beginning to work with immersion lenses for lithography. Such a
system would allow one to have numerical apertures greater than one. Assume that an
ArF projection aligner could be made with a spatial coherence of 0.5 and a numerical
aperture of 1.2, and that it was used to expose a resist that has a contrast of 3.0.
a. What would you expect the minimum feature size to be?
b. What would be the depth of focus?
c. What you expect the minimum feature size to be if the resist contrast is 4.0?

3) The following lists part of a 0.25 m CMOS process flow. This sequence includes a
lightly doped drain and a self aligned silicide. The select mask produces a photoresist
image that opens up that device for an implant or etch and protects everything else on the
chip. Embedded in this sequence are five major mistakes that will absolutely prevent the
device from working. Find four of them and explain why they are incorrect.

Complete device through well formation, isolation, and channel implants

Strip screen oxide to silicon
Gate oxidation (dry O2, 800 oC, 10 minutes)
Gate mask
Reactive ion etch gate electrode to gate oxide
Resist strip
PMOS transistor select mask
Implant (Phos, 10 keV, 1x1015 cm-2)
Resist strip
NMOS transistor select mask
Implant (As, 10 keV, 1x1014 cm-2)
Resist strip
Deposit aluminum for sidewall spacer (0.2 m)
Etch Reactive ion etch to silicon
NMOS transistor select mask
Implant (As, 20 keV, 1x1015 cm-2)
Anneal (N2, 1000 oC, 5 sec)
Etch gate oxide down to silicon
Sputter Ti (5 m thick)
Anneal (N2, 550 oC, 60 sec)
Etch in aqua regia
Anneal (N2, 750 oC, 60 sec)
Finish wafer with interconnect
 4) For an implanted ohmic contact to n-type silicon, the doping concentration is 3x1021 cm-3.
The barrier height 0.5 eV and you can take the tunneling effective mass of the electron as
equal to the rest mass of an electron.
a. Find the C2 constant for this contact.
b. If the specific contact resistance is 3x10-7 -cm2, find Ao for this contact.

5a) A single crystal silicon cantilever beam of thickness 2 m, length 750 m, and with 100 m
has a p-type piezoresistor at the point of maximum stress on the beam. Calculate R/R for
the piezoresistor if there is a load of 10 N distributed along the length of the beam.