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TOP252-262

TOPSwitch-HX Family

Enhanced EcoSmart, Integrated Off-Line Switcher with


Advanced Feature Set and Extended Power Range

Product Highlights
+
Lower System Cost, Higher Design Flexibility AC DC
Multi-mode operation maximizes efficiency at all loads IN OUT
-
New eSIP-7F and eSIP-7C packages
Low thermal impedance junction-to-case (2 C per watt)
Low height is ideal for adapters where space is limited
D V
Simple mounting using a clip to aid low cost manufacturing
Horizontal eSIP-7F package ideal for ultra low height adapter CONTROL
TOPSwitch-HX C
and monitor applications
Extended package creepage distance from DRAIN pin to
S X F
adjacent pin and to heat sink
No heat sink required up to 35 W using P, G and M packages
with universal input voltage and up to 48 W at 230 VAC PI-4510-100206
Output overvoltage protection (OVP) is user programmable for
Figure 1. Typical Flyback Application.
latching/non-latching shutdown with fast AC reset
Allows both primary and secondary sensing
Heat sink is connected to SOURCE for low EMI
Line undervoltage (UV) detection prevents turn-off glitches
Improved auto-restart delivers <3% of maximum power in
Line overvoltage (OV) shutdown extends line surge limit short circuit and open loop fault conditions
Accurate programmable current limit Accurate hysteretic thermal shutdown function automatically
Optimized line feed-forward for line ripple rejection recovers without requiring a reset
132 kHz frequency (254Y-258Y and all E/L packages) reduces Fully integrated soft-start for minimum start-up stress
transformer and power supply size Extended creepage between DRAIN and all other pins
Half frequency option for video applications improves field reliability
Frequency jittering reduces EMI filter cost

Output Power Table


230 VAC 15%4 85-265 VAC 230 VAC 15% 85-265 VAC
Product5 Open Open Product5 Open Open
Adapter1 Peak3 Adapter 1
Peak 3
Adapter 1
Adapter1
Frame2 Frame2 Frame2 Frame2
TOP252PN/GN 21 W 13 W TOP252EN/EG 10 W 21 W 6W 13 W
9W 15 W 6W 10 W TOP253EN/EG 21 W 43 W 13 W 29 W
TOP252MN 21 W 13 W
TOP254EN/YN/EG 30 W 62 W 20 W 43 W
TOP253PN/GN 38 W 25 W TOP255EN/YN/EG 40 W 81 W 26 W 57 W
15 W 25 W 9W 15 W
TOP253MN 43 W 29 W TOP255LN 40 W 81 W 26 W 57 W
TOP256EN/YN/EG 60 W 119 W 40 W 86 W
TOP254PN/GN 47 W 30 W
16 W 28 W 11 W 20 W TOP256LN 60 W 88 W 40 W 64 W
TOP254MN 62 W 40 W TOP257EN/YN/EG 85 W 157 W 55 W 119 W
TOP255PN/GN 54 W 35 W TOP257LN 85 W 105 W 55 W 78 W
19 W 30 W 13 W 22 W TOP258EN/YN/EG 105 W 195 W 70 W 148 W
TOP255MN 81 W 52 W TOP258LN 105 W 122 W 70 W 92 W
TOP256PN/GN 63 W 40 W TOP259EN/YN/EG 128 W 238 W 80 W 171 W
21 W 34 W 15 W 26 W TOP259LN 128 W 162 W 80 W 120 W
TOP256MN 98 W 64 W
TOP260EN/YN/EG 147 W 275 W 93 W 200 W
TOP257PN/GN 70 W 45 W TOP260LN 147 W 190 W 93 W 140 W
25 W 41 W 19 W 30 W
TOP257MN 119 W 78 W TOP261EN/YN/EG 177 W 333 W 118 W 254 W
TOP261LN 177 W 244 W 118 W 177 W
TOP258PN/GN 77 W 50 W
29 W 48 W 22 W 35 W TOP262EN6 177 W 333 W 118 W 254 W
TOP258MN 140 W 92 W TOP262LN6 177 W 244 W 118 W 177 W

Table 1. Output Power Table. (for notes see page 2).

www.powerint.com June 2013


TOP252-262

EcoSmart Energy Efficient Y Package Option for TOP259-261


Energy efficient over entire load range In order to improve noise-immunity on large TOPSwitch-HX
No-load consumption Y package parts, the F pin has been removed (TOP259-261YN
Less than 200 mW at 230 VAC are fixed at 66 kHz switching frequency) and replaced with a
Standby power for 1 W input SIGNAL GROUND (G) pin. This pin acts as a low noise path for
>600 mW output at 110 VAC input the C pin capacitor and the X pin resistor. It is only required for
>500 mW output at 265 VAC input the TOP259-261YN package parts.

Description
TOPSwitch-HX cost effectively incorporates a 700 V power +
MOSFET, high voltage switched current source, PWM control, AC DC
IN OUT
oscillator, thermal shutdown circuit, fault protection and other -
control circuitry onto a monolithic device.

Notes for Table 1: D V


1. Minimum continuous power in a typical non-ventilated CONTROL
TOPSwitch-HX C
enclosed adapter measured at +50 C ambient. Use of an
external heat sink will increase power capability.
S X G
2. Minimum continuous power in an open frame design at
+50 C ambient.
3. Peak power capability in any design at +50 C ambient.
4. 230 VAC or 110/115 VAC with doubler. PI-4973-122607

5. Packages: P: DIP-8C, G: SMD-8C, M: SDIP-10C,


Figure 2. Typical Flyback Application TOP259YN, TOP260YN and TOP261YN.
Y: TO-220-7C, E: eSIP-7C, L: eSIP-7F.
See part ordering information.
6. TOP261 and TOP262 have the same current limit set point. In
some applications TOP262 may run cooler than TOP261 due
to a lower RDS(ON) for the larger device.

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TOP252-262

Section List

Functional Block Diagram ........................................................................................................................................ 4


Pin Functional Description ....................................................................................................................................... 6
TOPSwitch-HX Family Functional Description ........................................................................................................ 7
CONTROL (C) Pin Operation..................................................................................................................................... 8
Oscillator and Switching Frequency........................................................................................................................... 8
Pulse Width Modulator ............................................................................................................................................. 9
Maximum Load Cycle............................................................................................................................................... 9
Error Amplifier........................................................................................................................................................... 9
On-Chip Current Limit with External Programmability................................................................................................ 9
Line Undervoltage Detection (UV)............................................................................................................................ 10
Line Overvoltage Shutdown (OV)............................................................................................................................. 11
Hysteretic or Latching Output Overvoltage Protection (OVP)................................................................................... 11
Line Feed-Forward with DCMAX Reduction............................................................................................................... 13
Remote ON/OFF and Synchronization..................................................................................................................... 13
Soft-Start................................................................................................................................................................ 13
Shutdown/Auto-Restart.......................................................................................................................................... 13
Hysteretic Over-Temperature Protection.................................................................................................................. 13
Bandgap Reference................................................................................................................................................ 13
High-Voltage Bias Current Source........................................................................................................................... 13
Typical Uses of FREQUENCY (F) Pin ....................................................................................................................... 15
Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins ........................................... 16
Typical Uses of MULTI-FUNCTION (M) Pin ............................................................................................................ 18
Application Examples ............................................................................................................................................... 21
A High Efficiency, 35 W, Dual Output Universal Input Power Supply...................................................................... 21
A High Efficiency, 150 W, 250-380 VDC Input Power Supply................................................................................... 22
A High Efficiency, 20 W Continuous 80 W Peak, Universal Input Power Supply.................................................... 23
A High Efficiency, 65 W, Universal Input Power Supply............................................................................................ 24
Key Application Considerations ............................................................................................................................... 25
TOPSwitch-HX vs.TOPSwitch-GX........................................................................................................................ . 25
TOPSwitch-HX Design Considerations ................................................................................................................... 26
TOPSwitch-HX Layout Considerations.................................................................................................................... 27
Quick Design Checklist........................................................................................................................................... 31
Design Tools........................................................................................................................................................... 31
Product Specifications and Test Conditions .......................................................................................................... 32
Typical Performance Characteristics ..................................................................................................................... 39
Package Outlines ..................................................................................................................................................... 43
Part Ordering Information ........................................................................................................................................ 47

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TOP252-262

VC
0
CONTROL (C) DRAIN (D)
ZC INTERNAL
1 SUPPLY

SHUNT REGULATOR/ -
ERROR AMPLIFIER + +
SOFT START
- 5.8 V
4.8 V -
+ 5.8 V
INTERNAL UV KPS(UPPER) -
IFB COMPARATOR
+
VI (LIMIT)
CURRENT
LIMIT
ADJUST KPS(LOWER) -
16
ON/OFF
+
SHUTDOWN/
AUTO-RESTART CURRENT LIMIT
VBG + VT COMPARATOR

STOP LOGIC HYSTERETIC


MULTI- SOURCE (S)
FUNCTION (M) THERMAL
SHUTDOWN
CONTROLLED
TURN-ON
GATE DRIVER
STOP SOFT
V OVP OV/ START
UV
LINE DMAX
DCMAX OSCILLATOR
SENSE DCMAX WITH JITTER CLOCK
F REDUCTION S Q
LEADING
R EDGE
BLANKING
F REDUCTION
SOFT START
IFB PWM OFF
KPS(UPPER) IPS(UPPER)
KPS(LOWER) IPS(LOWER)

SOURCE (S)
PI-4508-120307

Figure 3a. Functional Block Diagram (P and G Packages).

VC
0
CONTROL (C) DRAIN (D)
ZC INTERNAL
1 SUPPLY

SHUNT REGULATOR/ -
ERROR AMPLIFIER + +
SOFT START
- 5.8 V
4.8 V -
+ 5.8 V
INTERNAL UV KPS(UPPER) -
IFB COMPARATOR
+
VI (LIMIT)
CURRENT
LIMIT
ADJUST KPS(LOWER) -
16
ON/OFF
+
SHUTDOWN/
EXTERNAL AUTO-RESTART CURRENT LIMIT
CURRENT VBG + VT COMPARATOR
LIMIT (X)
VOLTAGE STOP LOGIC HYSTERETIC
MONITOR (V) THERMAL SOURCE (S)
1V
SHUTDOWN
CONTROLLED
TURN-ON
STOP SOFT GATE DRIVER
V OVP OV/ START
UV
LINE OSCILLATOR DMAX
DCMAX DCMAX
SENSE WITH JITTER
CLOCK
F REDUCTION S Q
LEADING
R EDGE
BLANKING
F REDUCTION
SOFT START
IFB PWM OFF
KPS(UPPER) IPS(UPPER)
KPS(LOWER) IPS(LOWER)

SOURCE (S)
PI-4643-082907

Figure 3b. Functional Block Diagram (M Package).

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TOP252-262

VC
0
CONTROL (C) DRAIN (D)
ZC INTERNAL
1 SUPPLY

SHUNT REGULATOR/ -
ERROR AMPLIFIER + +
SOFT START
- 5.8 V
4.8 V -
+ 5.8 V
INTERNAL UV KPS(UPPER) -
IFB COMPARATOR
+
VI (LIMIT)
CURRENT
LIMIT
ADJUST KPS(LOWER) -
16
ON/OFF
+
SHUTDOWN/
EXTERNAL AUTO-RESTART CURRENT LIMIT
CURRENT VBG + VT COMPARATOR
LIMIT (X)
VOLTAGE STOP LOGIC HYSTERETIC
MONITOR (V) THERMAL SOURCE (S)
1V
SHUTDOWN
CONTROLLED
TURN-ON
STOP SOFT GATE DRIVER
V OVP OV/ START
UV
LINE OSCILLATOR DMAX
DCMAX DCMAX
SENSE WITH JITTER
CLOCK
66k/132k
F REDUCTION S Q
LEADING
R EDGE
FREQUENCY BLANKING
(F)
F REDUCTION
SOFT START
IFB PWM OFF
KPS(UPPER) IPS(UPPER)
KPS(LOWER) IPS(LOWER)

SOURCE (S)
PI-4511-082907

Figure 3c. Functional Block Diagram (TOP254-258 YN Package and all eSIP Packages).

VC
0
CONTROL (C) DRAIN (D)
ZC INTERNAL
1 SUPPLY

SHUNT REGULATOR/ -
ERROR AMPLIFIER + +
SOFT START
- 5.8 V
4.8 V -
+ 5.8 V
INTERNAL UV KPS(UPPER) -
IFB COMPARATOR
+
VI (LIMIT)
CURRENT
LIMIT
ADJUST KPS(LOWER) -
16
ON/OFF
+
SHUTDOWN/
EXTERNAL AUTO-RESTART CURRENT LIMIT
CURRENT VBG + VT COMPARATOR
LIMIT (X)
VOLTAGE STOP LOGIC HYSTERETIC
MONITOR (V) THERMAL SOURCE (S)
1V
SHUTDOWN
CONTROLLED
TURN-ON
STOP SOFT GATE DRIVER
V OVP OV/ START
UV
LINE OSCILLATOR DMAX
DCMAX DCMAX
SENSE WITH JITTER
CLOCK
F REDUCTION S Q
LEADING
R EDGE SOURCE (S)
BLANKING
F REDUCTION
SOFT START
IFB PWM OFF
KPS(UPPER) IPS(UPPER)
KPS(LOWER) IPS(LOWER)

SIGNAL
PI-4974-122607 GROUND (G)

Figure 3d. Functional Block Diagram TOP259YN, TOP260YN, TOP261YN.

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TOP252-262

Pin Functional Description VOLTAGE MONITOR (V) Pin (Y & M package only):
Input for OV, UV, line feed forward with DCMAX reduction, output
DRAIN (D) Pin: overvoltage protection (OVP), remote ON/OFF and device reset.
High-voltage power MOSFET DRAIN pin. The internal start-up A connection to the SOURCE pin disables all functions on this pin.
bias current is drawn from this pin through a switched high-
voltage current source. Internal current limit sense point for MULTI-FUNCTION (M) Pin (P & G packages only):
drain current. This pin combines the functions of the VOLTAGE MONITOR (V)
and EXTERNAL CURRENT LIMIT (X) pins of the Y package into
CONTROL (C) Pin: one pin. Input pin for OV, UV, line feed forward with DCMAX
Error amplifier and feedback current input pin for duty cycle
control. Internal shunt regulator connection to provide internal

PI-4711-021308
bias current during normal operation. It is also used as the
connection point for the supply bypass and auto-restart/ + VUV = IUV RLS + VV (IV = IUV)
VOV = IOV RLS + VV (IV = IOV)
compensation capacitor. For RLS = 4 M
RLS 4 M
VUV = 102.8 VDC
EXTERNAL CURRENT LIMIT (X) Pin (Y, M, E and L package):
VOV = 451 VDC
Input pin for external current limit adjustment and remote
DC DCMAX@100 VDC = 76%
ON/OFF. A connection to SOURCE pin disables all functions on Input D V DCMAX@375 VDC = 41%
this pin. Voltage CONTROL
C
For RIL = 12 k
S X ILIMIT = 61%
E Package (eSIP-7C) Y Package (TO-220-7C)
RIL See Figure 55b for
Note: Y package for TOP259-261 other resistor values
- 12 k
(RIL) to select different
Exposed Pad ILIMIT values.
(Hidden)
Internally
Connected to Figure 5. TOP254-258 Y and All M/E/L Package Line Sense and Externally Set
SOURCE Pin Current Limit.

PI-4983-021308
Tab Internally + VUV = IUV RLS + VV (IV = IUV)
12345 7 Connected to VOV = IOV RLS + VV (IV = IOV)
VXCF S D SOURCE Pin For RLS = 4 M
L Package (eSIP-7F) RLS 4 M
VUV = 102.8 VDC
VOV = 451 VDC
DC DCMAX@100 VDC = 76%
Input D V DCMAX@375 VDC = 41%
12345 7 Voltage
V XCSG D CONTROL
C
Lead Bend
Outward from Drawing For RIL = 12 k
(Refer to eSIP-7F Package S X G ILIMIT = 61%
12345 7 Outline Drawing)
VXCF S D See Figure 55b for
RIL
other resistor values
M Package Y Package (TO-220-7C) - 12 k (RIL) to select different
Note: Y package for TOP254-258 ILIMIT values.
V 1 10 S
X 2 9 S Figure 6. TOP259-261 Y Package Line Sense and External Current Limit.

C 3 8 S
7 S
+
D 5 6 S VUV = IUV RLS + VM (IM = IUV)
VOV = IOV RLS + VM (IM = IOV)
Tab Internally
P and G Package Connected to For RLS = 4 M
SOURCE Pin RLS 4 M VUV = 102.8 VDC
VOV = 451 VDC
M 1 8 S DC
Input DCMAX@100 VDC = 76%
C 2 7 S Voltage DCMAX@375 VDC = 41%
D M
6 S 12345 7 CONTROL
VXCS F D C
D 4 5 S
S
PI-4644-091108 -
PI-4712-120307
Figure 4. Pin Configuration (Top View).
Figure 7. P/G Package Line Sense.

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TOP252-262

Auto-Restart
+ 78
For RIL = 12 k
ILIMIT = 61% Slope = PWM Gain
(constant over load range)

Duty Cycle (%)


For RIL = 19 k
ILIMIT = 37%
DC
See Figure 55b for other
Input
resistor values (RIL) to
Voltage
select different ILIMIT values.
D M
CONTROL
RIL C
CONTROL
Current
S
-
PI-4713-021308

100

To Current Limit Ratio (%)


Figure 8. P/G Package Externally Set Current Limit.

Drain Peak Current


reduction, output overvoltage protection (OVP), external current
55
limit adjustment, remote ON/OFF and device reset. A
connection to SOURCE pin disables all functions on this pin
and makes TOPSwitch-HX operate in simple three terminal
mode (like TOPSwitch-II). 25

FREQUENCY (F) Pin (TOP254-258Y, and all E and L packages): CONTROL


Current
Input pin for selecting switching frequency 132 kHz if connected
to SOURCE pin and 66 kHz if connected to CONTROL pin. Full Frequency Mode
The switching frequency is internally set for fixed 66 kHz
132 Low
operation in the P, G, M package and TOP259YN, TOP260YN
Frequency
and TOP261YN. Variable
Frequency (kHz)

Frequency Mode
66 Mode
SIGNAL GROUND (G) Pin (TOP259YN, TOP260YN &
TOP261YN only): Jitter Multi-Cycle
Return for C pin capacitor and X pin resistor. Modulation

SOURCE (S) Pin: 30


Output MOSFET source connection for high voltage power
return. Primary side control circuit common and reference point. ICD1 IB IC01 IC02 IC03 ICOFF CONTROL
Current
PI-4645-041107

TOPSwitch-HX Family Functional Description Figure 9. Control Pin Characteristics (Multi-Mode Operation).

Like TOPSwitch-GX, TOPSwitch-HX is an integrated switched two terminals, VOLTAGE-MONITOR and EXTERNAL CURRENT
mode power supply chip that converts a current at the control LIMIT (available in M package) or one terminal MULTI-FUNCTION
input to a duty cycle at the open drain output of a high voltage (available in P and G package) have been used to implement
power MOSFET. During normal operation the duty cycle of the some of the new functions. These terminals can be connected
power MOSFET decreases linearly with increasing CONTROL to the SOURCE pin to operate the TOPSwitch-HX in a
pin current as shown in Figure 9. TOPSwitch-like three terminal mode. However, even in this three
terminal mode, the TOPSwitch-HX offers many transparent
In addition to the three terminal TOPSwitch features, such as features that do not require any external components:
the high voltage start-up, the cycle-by-cycle current limiting,
loop compensation circuitry, auto-restart and thermal 1. A fully integrated 17 ms soft-start significantly reduces or
shutdown, the TOPSwitch-HX incorporates many additional eliminates output overshoot in most applications by sweeping
functions that reduce system cost, increase power supply both current limit and frequency from low to high to limit the
performance and design flexibility. A patented high voltage peak currents and voltages during start-up.
CMOS technology allows both the high-voltage power MOSFET 2. A maximum duty cycle (DCMAX) of 78% allows smaller input
and all the low voltage control circuitry to be cost effectively storage capacitor, lower input voltage requirement and/or
integrated onto a single monolithic chip. higher power capability.
3. Multi-mode operation optimizes and improves the power
Three terminals, FREQUENCY, VOLTAGE-MONITOR, and supply efficiency over the entire load range while maintaining
EXTERNAL CURRENT LIMIT (available in Y and E/L packages), good cross regulation in multi-output supplies.

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4. Switching frequency of 132 kHz reduces the transformer size current source connected internally between the DRAIN and
with no noticeable impact on EMI. CONTROL pins. When the CONTROL pin voltage VC reaches
5. Frequency jittering reduces EMI in the full frequency mode at approximately 5.8 V, the control circuitry is activated and the
high load condition. soft-start begins. The soft-start circuit gradually increases the
6. Hysteretic over-temperature shutdown ensures automatic drain peak current and switching frequency from a low starting
recovery from thermal fault. Large hysteresis prevents circuit value to the maximum drain peak current at the full frequency
board overheating. over approximately 17 ms. If no external feedback/supply
7. Packages with omitted pins and lead forming provide large current is fed into the CONTROL pin by the end of the soft-start,
drain creepage distance. the high voltage current source is turned off and the CONTROL
8. Reduction of the auto-restart duty cycle and frequency to pin will start discharging in response to the supply current
improve the protection of the power supply and load during drawn by the control circuitry. If the power supply is designed
open loop fault, short circuit, or loss of regulation. properly, and no fault condition such as open loop or shorted
9. Tighter tolerances on I2f power coefficient, current limit output exists, the feedback loop will close, providing external
reduction, PWM gain and thermal shutdown threshold. CONTROL pin current, before the CONTROL pin voltage has
had a chance to discharge to the lower threshold voltage of
The VOLTAGE-MONITOR (V) pin is usually used for line sensing approximately 4.8 V (internal supply undervoltage lockout
by connecting a 4 MW resistor from this pin to the rectified DC threshold). When the externally fed current charges the
high voltage bus to implement line overvoltage (OV), under- CONTROL pin to the shunt regulator voltage of 5.8 V, current in
voltage (UV) and dual-slope line feed-forward with DCMAX excess of the consumption of the chip is shunted to SOURCE
reduction. In this mode, the value of the resistor determines the through an NMOS current mirror as shown in Figure 3. The
OV/UV thresholds and the DCMAX is reduced linearly with a dual output current of that NMOS current mirror controls the duty
slope to improve line ripple rejection. In addition, it also cycle of the power MOSFET to provide closed loop regulation.
provides another threshold to implement the latched and The shunt regulator has a finite low output impedance ZC that
hysteretic output overvoltage protection (OVP). The pin can sets the gain of the error amplifier when used in a primary
also be used as a remote ON/OFF using the IUV threshold. feedback configuration. The dynamic impedance ZC of the
CONTROL pin together with the external CONTROL pin
The EXTERNAL CURRENT LIMIT (X) pin can be used to reduce capacitance sets the dominant pole for the control loop.
the current limit externally to a value close to the operating peak
current, by connecting the pin to SOURCE through a resistor. When a fault condition such as an open loop or shorted output
This pin can also be used as a remote ON/OFF input. prevents the flow of an external current into the CONTROL pin,
the capacitor on the CONTROL pin discharges towards 4.8 V.
For the P and G package the VOLTAGE-MONITOR and At 4.8 V, auto-restart is activated, which turns the output
EXTERNAL CURRENT LIMIT pin functions are combined on MOSFET off and puts the control circuitry in a low current
one MULTI-FUNCTION (M) pin. However, some of the functions standby mode. The high-voltage current source turns on and
become mutually exclusive. charges the external capacitance again. A hysteretic internal
supply undervoltage comparator keeps VC within a window of
The FREQUENCY (F) pin in the TOP254-258 Y and E/L packages typically 4.8 V to 5.8 V by turning the high-voltage current
set the switching frequency in the full frequency PWM mode to source on and off as shown in Figure 11. The auto-restart
the default value of 132 kHz when connected to SOURCE pin. A circuit has a divide-by-sixteen counter, which prevents the
half frequency option of 66 kHz can be chosen by connecting output MOSFET from turning on again until sixteen discharge/
this pin to the CONTROL pin instead. Leaving this pin open is charge cycles have elapsed. This is accomplished by enabling
not recommended. In the P, G and M packages and the the output MOSFET only when the divide-by-sixteen counter
TOP259-261 Y packages, the frequency is set internally at reaches the full count (S15). The counter effectively limits
66 kHz in the full frequency PWM mode. TOPSwitch-HX power dissipation by reducing the auto-restart
duty cycle to typically 2%. Auto-restart mode continues until
CONTROL (C) Pin Operation output voltage regulation is again achieved through closure of
The CONTROL pin is a low impedance node that is capable of the feedback loop.
receiving a combined supply and feedback current. During
normal operation, a shunt regulator is used to separate the Oscillator and Switching Frequency
feedback signal from the supply current. CONTROL pin voltage The internal oscillator linearly charges and discharges an
VC is the supply voltage for the control circuitry including the internal capacitance between two voltage levels to create a
MOSFET gate driver. An external bypass capacitor closely triangular waveform for the timing of the pulse width modulator.
connected between the CONTROL and SOURCE pins is This oscillator sets the pulse width modulator/current limit latch
required to supply the instantaneous gate drive current. The at the beginning of each cycle.
total amount of capacitance connected to this pin also sets the
auto-restart timing as well as control loop compensation. The nominal full switching frequency of 132 kHz was chosen to
When rectified DC high voltage is applied to the DRAIN pin minimize transformer size while keeping the fundamental EMI
during start-up, the MOSFET is initially off, and the CONTROL frequency below 150 kHz. The FREQUENCY pin (available only
pin capacitor is charged through a switched high voltage in TOP254-258 Y and E, L packages), when shorted to the
CONTROL pin, lowers the full switching frequency to 66 kHz

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TOP252-262

packages). Duty cycle is reduced from DCMAX through the

PI-4530-041107
fOSC + reduction of the on-time when IC is increased beyond IB. This
Switching operation is identical to the PWM control of all other TOPSwitch
Frequency families. TOPSwitch-HX only operates in this mode if the
fOSC -
cycle-by-cycle peak drain current stays above kPS(UPPER)*ILIMIT(set),
where kPS(UPPER) is 55% (typical) and ILIMIT(set) is the current limit
4 ms externally set via the X or M pin.

Variable Frequency PWM mode: When peak drain current is


VDRAIN
lowered to kPS(UPPER)* ILIMIT(set) as a result of power supply load
reduction, the PWM modulator initiates the transition to variable
Time frequency PWM mode, and gradually turns off frequency jitter.
In this mode, peak drain current is held constant at kPS(UPPER)*
Figure 10. Switching Frequency Jitter (Idealized VDRAIN Waveforms). ILIMIT(set) while switching frequency drops from the initial full
frequency of fOSC (132 kHz or 66 kHz) towards the minimum
(half frequency), which may be preferable in some cases such frequency of fMCM(MIN) (30 kHz typical). Duty cycle reduction is
as noise sensitive video applications or a high efficiency accomplished by extending the off-time.
standby mode. Otherwise, the FREQUENCY pin should be
connected to the SOURCE pin for the default 132 kHz. In the Low Frequency PWM mode: When switching frequency
M, P and G packages and the TOP259-261 Y package option, reaches fMCM(MIN) (30 kHz typical), the PWM modulator starts to
the full frequency PWM mode is set at 66 kHz, for higher transition to low frequency mode. In this mode, switching
efficiency and increased output power in all applications. frequency is held constant at fMCM(MIN) and duty cycle is reduced,
similar to the full frequency PWM mode, through the reduction
To further reduce the EMI level, the switching frequency in the of the on-time. Peak drain current decreases from the initial
full frequency PWM mode is jittered (frequency modulated) by value of kPS(UPPER)* ILIMIT(set) towards the minimum value of
approximately 2.5 kHz for 66 kHz operation or 5 kHz for kPS(LOWER)*ILIMIT(set), where kPS(LOWER) is 25% (typical) and ILIMIT(set) is
132 kHz operation at a 250 Hz (typical) rate as shown in the current limit externally set via the X or M pin.
Figure 10. The jitter is turned off gradually as the system is
entering the variable frequency mode with a fixed peak drain Multi-Cycle-Modulation mode: When peak drain current is
current. lowered to kPS(LOWER)*ILIMIT(set), the modulator transitions to
multi-cycle-modulation mode. In this mode, at each turn-on,
Pulse Width Modulator the modulator enables output switching for a period of TMCM(MIN)
The pulse width modulator implements multi-mode control by at the switching frequency of fMCM(MIN) (4 or 5 consecutive pulses
driving the output MOSFET with a duty cycle inversely at 30 kHz) with the peak drain current of kPS(LOWER)*ILIMIT(set), and
proportional to the current into the CONTROL pin that is in stays off until the CONTROL pin current falls below IC(OFF). This
excess of the internal supply current of the chip (see Figure 9). mode of operation not only keeps peak drain current low but
The feedback error signal, in the form of the excess current, is also minimizes harmonic frequencies between 6 kHz and
filtered by an RC network with a typical corner frequency of 30 kHz. By avoiding transformer resonant frequency this way,
7 kHz to reduce the effect of switching noise in the chip supply all potential transformer audible noises are greatly suppressed.
current generated by the MOSFET gate driver.
Maximum Duty Cycle
To optimize power supply efficiency, four different control The maximum duty cycle, DCMAX, is set at a default maximum
modes are implemented. At maximum load, the modulator value of 78% (typical). However, by connecting the VOLTAGE-
operates in full frequency PWM mode; as load decreases, the MONITOR or MULTI-FUNCTION pin (depending on the
modulator automatically transitions, first to variable frequency package) to the rectified DC high voltage bus through a resistor
PWM mode, then to low frequency PWM mode. At light load, with appropriate value (4 MW typical), the maximum duty cycle
the control operation switches from PWM control to multi-cycle- can be made to decrease from 78% to 40% (typical) when input
modulation control, and the modulator operates in multi-cycle- line voltage increases from 88 V to 380 V, with dual gain slopes.
modulation mode. Although different modes operate differently
to make transitions between modes smooth, the simple Error Amplifier
relationship between duty cycle and excess CONTROL pin The shunt regulator can also perform the function of an error
current shown in Figure 9 is maintained through all three PWM amplifier in primary side feedback applications. The shunt
modes. Please see the following sections for the details of the regulator voltage is accurately derived from a temperature-
operation of each mode and the transitions between modes. compensated bandgap reference. The CONTROL pin dynamic
impedance ZC sets the gain of the error amplifier. The
Full Frequency PWM mode: The PWM modulator enters full CONTROL pin clamps external circuit signals to the VC voltage
frequency PWM mode when the CONTROL pin current (IC) level. The CONTROL pin current in excess of the supply current
reaches IB. In this mode, the average switching frequency is is separated by the shunt regulator and becomes the feedback
kept constant at fOSC (66 kHz for P, G and M packages and current Ifb for the pulse width modulator.
TOP259-261 Y, pin selectable 132 kHz or 66 kHz for Y and E/L

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TOP252-262

~
~
~
~
VUV

~
~
~
~
VLINE

~
~
0V

S15 S14 S13 S12 S0 S15 S14 S13 S12 S0 S15 S14 S13 S12 S0 S15 S15 5.8 V

~
~
~
~
~
~
VC 4.8 V

0V

~
~

~
~
VDRAIN

~
~
0V

VOUT
0V

~
~

~
~
~
~

1 2 3 2 4
Note: S0 through S15 are the output states of the auto-restart counter PI-4531-121206

Figure 11. Typical Waveforms for (1) Power Up (2) Normal Operation (3) Auto-Restart (4) Power Down.

On-Chip Current Limit with External Programmability on. The leading edge blanking time has been set so that, if a
The cycle-by-cycle peak drain current limit circuit uses the power supply is designed properly, current spikes caused by
output MOSFET ON-resistance as a sense resistor. A current primary-side capacitances and secondary-side rectifier reverse
limit comparator compares the output MOSFET on-state drain recovery time should not cause premature termination of the
to source voltage VDS(ON) with a threshold voltage. High drain switching pulse.
current causes VDS(ON) to exceed the threshold voltage and turns
the output MOSFET off until the start of the next clock cycle. The current limit is lower for a short period after the leading
The current limit comparator threshold voltage is temperature edge blanking time. This is due to dynamic characteristics of
compensated to minimize the variation of the current limit due the MOSFET. During startup and fault conditions the controller
to temperature related changes in RDS(ON) of the output MOSFET. prevents excessive drain currents by reducing the switching
The default current limit of TOPSwitch-HX is preset internally. frequency.
However, with a resistor connected between EXTERNAL
CURRENT LIMIT (X) pin (Y, E/L and M packages) or MULTI- Line Undervoltage Detection (UV)
FUNCTION (M) pin (P and G package) and SOURCE pin (for At power up, UV keeps TOPSwitch-HX off until the input line
TOP259-261 Y, the X pin is connected to the SIGNAL GROUND voltage reaches the undervoltage threshold. At power down,
(G) pin), current limit can be programmed externally to a lower UV prevents auto-restart attempts after the output goes out of
level between 30% and 100% of the default current limit. By regulation. This eliminates power down glitches caused by slow
setting current limit low, a larger TOPSwitch-HX than necessary discharge of the large input storage capacitor present in
for the power required can be used to take advantage of the applications such as standby supplies. A single resistor
lower RDS(ON) for higher efficiency/smaller heat sinking connected from the VOLTAGE-MONITOR pin (Y, E/L and M
requirements. TOPSwitch-HX current limit reduction initial packages) or MULTI-FUNCTION pin (P and G packages) to the
tolerance through the X pin (or M pin) has been improved rectified DC high voltage bus sets UV threshold during power
significantly compare with previous TOPSwitch-GX. With a up. Once the power supply is successfully turned on, the UV
second resistor connected between the EXTERNAL CURRENT threshold is lowered to 44% of the initial UV threshold to allow
LIMIT (X) pin (Y, E/L and M packages) or MULTI-FUNCTION (M) extended input voltage operating range (UV low threshold). If
pin (P and G package) and the rectified DC high voltage bus, the UV low threshold is reached during operation without the
the current limit is reduced with increasing line voltage, allowing power supply losing regulation, the device will turn off and stay
a true power limiting operation against line variation to be off until UV (high threshold) has been reached again. If the
implemented. When using an RCD clamp, this power limiting power supply loses regulation before reaching the UV low
technique reduces maximum clamp voltage at high line. This threshold, the device will enter auto-restart. At the end of each
allows for higher reflected voltage designs as well as reducing auto-restart cycle (S15), the UV comparator is enabled. If the
clamp dissipation. UV high threshold is not exceeded, the MOSFET will be
disabled during the next cycle (see Figure 11). The UV feature
The leading edge blanking circuit inhibits the current limit can be disabled independent of the OV feature.
comparator for a short time after the output MOSFET is turned

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TOP252-262

Line Overvoltage Shutdown (OV) clamp network, bias winding return or power traces from other
The same resistor used for UV also sets an overvoltage converters. If the line sensing features are used, then the sense
threshold, which, once exceeded, will force TOPSwitch-HX to resistors must be placed within 10 mm of the V-pin to minimize
stop switching instantaneously (after completion of the current the V-pin node area. The DC bus should then be routed to the
switching cycle). If this condition lasts for at least 100 ms, the line sense resistors. Note that external capacitance must not
TOPSwitch-HX output will be forced into off state. Unlike with be connected to the V-pin as this may cause misoperation of
TOPSwitch-GX, however, when the line voltage is back to the V pin related functions.
normal with a small amount of hysteresis provided on the OV
threshold to prevent noise triggering, the state machine sets to Hysteretic or Latching Output Overvoltage Protection (OVP)
S13 and forces TOPSwitch-HX to go through the entire auto- The detection of the hysteretic or latching output overvoltage
restart sequence before attempting to switch again. The ratio protection (OVP) is through the trigger of the line overvoltage
of OV and UV thresholds is preset at 4.5, as can be seen in threshold. The V-pin or M-pin voltage will drop by 0.5 V, and
Figure 12. When the MOSFET is off, the rectified DC high the controller measures the external attached impedance
voltage surge capability is increased to the voltage rating of the immediately after this voltage drops. If IV or IM exceeds IOV(LS)
MOSFET (700 V), due to the absence of the reflected voltage (336 mA typical) longer than 100 ms, TOPSwitch-HX will latch
and leakage spikes on the drain. The OV feature can be into a permanent off state for the latching OVP. It only can be
disabled independent of the UV feature. reset if V V or VM goes below 1 V or VC goes below the power-
up-reset threshold (VC(RESET)) and then back to normal.
In order to reduce the no-load input power of TOPSwitch-HX
designs, the V-pin (or M-pin for P Package) operates at very low If IV or IM does not exceed IOV(LS) or exceeds no longer than
currents. This requires careful layout considerations when 100 ms, TOPSwitch-HX will initiate the line overvoltage and the
designing the PCB to avoid noise coupling. Traces and hysteretic OVP. Their behavior will be identical to the line
components connected to the V-pin should not be adjacent to overvoltage shutdown (OV) that has been described in detail in
any traces carrying switching currents. These include the drain, the previous section.

Voltage Monitor and External Current Limit Pin Table*


Figure Number 16 17 18 19 20 21 22 23 24 25 26 27 28
Three Terminal Operation 3
Line Undervoltage 3 3 3 3 3 3
Line Overvoltage 3 3 3 3 3 3
Line Feed-Forward (DCMAX) 3 3 3 3 3
Output Overvoltage Protection 3 3
Overload Power Limiting 3
External Current Limit 3 3 3 3 3
Remote ON/OFF 3 3 3
Device Reset 3
*This table is only a partial list of many VOLTAGE MONITOR and EXTERNAL CURRENT LIMIT Pin Configurations that are possible.

Table 2. VOLTAGE MONITOR (V) Pin and EXTERNAL CURRENT LIMIT (X) Pin Configuration Options.

Multi-Function Pin Table*


Figure Number 29 30 31 32 33 34 35 36 37 38 39 40
Three Terminal Operation 3
Line Undervoltage 3 3 3 3
Line Overvoltage 3 3 3 3
Line Feed-Forward (DCMAX) 3 3 3
Output Overvoltage Protection 3 3
Overload Power Limiting 3
External Current Limit 3 3 3 3
Remote ON/OFF 3 3 3
Device Reset 3
*This table is only a partial list of many MULTI-FUNCTIONAL Pin Configurations that are possible.

Table 3. MULTI-FUNCTION (M) Pin Configuration Options.

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TOP252-262

M Pin

X Pin V Pin

IREM(N) IUV IOV IOV(LS)


(Enabled)
Output
MOSFET (Non-Latching) (Latching)
Switching
(Disabled)

Disabled when supply I


output goes out of
regulation
ILIMIT (Default)

Current
Limit

DCMAX (78%)

Maximum
Duty Cycle

VBG
Pin Voltage

I
-250 -200 -150 -100 -50 0 25 50 75 100 125 336

X and V Pins (Y, E, L and M Packages) and M Pin (P and G Packages) Current (A)
Note: This figure provides idealized functional characteristics with typical performance values. Please refer to the parametric
table and typical performance characteristics sections of the data sheet for measured data. For a detailed description of
each functional pin operation refer to the Functional Description section of the data sheet.
PI-4646-071708

Figure 12. MULTI-FUNCTION (P and G package). VOLTAGE MONITOR and EXTERNAL CURRENT LIMIT (Y, E/L and M package) Pin Characteristics.

The circuit examples shown in Figures 41, 42 and 43 show a The primary sensed OVP protection circuit shown in Figures 41,
simple method for implementing the primary sensed over- 42 and 43 is triggered by a significant rise in output voltage (and
voltage protection. therefore bias winding voltage). If the power supply is operating
under heavy load or low input line conditions when an open
During a fault condition resulting from loss of feedback, output loop occurs, the output voltage may not rise significantly.
voltage will rapidly rise above the nominal voltage. The increase Under these conditions, a latching shutdown will not occur until
in output voltage will also result in an increase in the voltage at load or line conditions change. Nevertheless, the operation
the output of the bias winding. A voltage at the output of the provides the desired protection by preventing significant rise in
bias winding that exceeds of the sum of the voltage rating of the the output voltage when the line or load conditions do change.
Zener diode connected from the bias winding output to the Primary side OVP protection with the TOPSwitch-HX in a typical
V-pin (or M-pin) and V-pin (or M-pin) voltage, will cause a current application will prevent a nominal 12 V output from rising above
in excess of IV or IM to be injected into the V-pin approximately 20 V under open loop conditions. If greater
(or M-pin), which will trigger the OVP feature. accuracy is required, a secondary sensed OVP circuit is
recommended.

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TOP252-262

Line Feed-Forward with DCMAX Reduction Soft-Start


The same resistor used for UV and OV also implements line voltage The 17 ms soft-start sweeps the peak drain current and
feed-forward, which minimizes output line ripple and reduces switching frequency linearly from minimum to maximum value
power supply output sensitivity to line transients. Note that for the by operating through the low frequency PWM mode and the
same CONTROL pin current, higher line voltage results in smaller variable frequency mode before entering the full frequency
operating duty cycle. As an added feature, the maximum duty mode. In addition to start-up, soft-start is also activated at each
cycle DCMAX is also reduced from 78% (typical) at a voltage slightly restart attempt during auto-restart and when restarting after
lower than the UV threshold to 36% (typical) at the OV threshold. being in hysteretic regulation of CONTROL pin voltage (VC), due
DCMAX of 36% at high line was chosen to ensure that the power to remote OFF or thermal shutdown conditions. This effectively
capability of the TOPSwitch-HX is not restricted by this feature minimizes current and voltage stresses on the output MOSFET,
under normal operation. TOPSwitch-HX provides a better fit to the the clamp circuit and the output rectifier during start-up. This
ideal feed-forward by using two reduction slopes: -1% per mA for all feature also helps minimize output overshoot and prevents
bus voltage less than 195 V (typical for 4 MW line impedance) and saturation of the transformer during start-up.
-0.25% per mA for all bus voltage more than 195 V. This dual
slope line feed-forward improves the line ripple rejection Shutdown/Auto-Restart
significantly compared with the TOPSwitch-GX. To minimize TOPSwitch-HX power dissipation under fault
conditions, the shutdown/auto-restart circuit turns the power
Remote ON/OFF supply on and off at an auto-restart duty cycle of typically 2% if
TOPSwitch-HX can be turned on or off by controlling the an out of regulation condition persists. Loss of regulation
current into the VOLTAGE-MONITOR pin or out from the interrupts the external current into the CONTROL pin. VC
EXTERNAL CURRENT LIMIT pin (Y, E/L and M packages) and regulation changes from shunt mode to the hysteretic auto-
into or out from the MULTI-FUNCTION pin (P and G package, restart mode as described in CONTROL pin operation section.
see Figure 12). In addition, the VOLTAGE-MONITOR pin has a When the fault condition is removed, the power supply output
1 V threshold comparator connected at its input. This voltage becomes regulated, VC regulation returns to shunt mode, and
threshold can also be used to perform remote ON/OFF control. normal operation of the power supply resumes.

When a signal is received at the VOLTAGE-MONITOR pin or the Hysteretic Over-Temperature Protection
EXTERNAL CURRENT LIMIT pin (Y, E/L and M packages) or the Temperature protection is provided by a precision analog circuit
MULTI-FUNCTION pin (P and G package) to disable the output that turns the output MOSFET off when the junction temperature
through any of the pin functions such as OV, UV and remote exceeds the thermal shutdown temperature (142 C typical).
ON/OFF, TOPSwitch-HX always completes its current switching When the junction temperature cools to below the lower
cycle before the output is forced off. hysteretic temperature point, normal operation resumes, thus
providing automatic recovery. A large hysteresis of 75 C
As seen above, the remote ON/OFF feature can also be used as (typical) is provided to prevent overheating of the PC board due
a standby or power switch to turn off the TOPSwitch-HX and to a continuous fault condition. VC is regulated in hysteretic
keep it in a very low power consumption state for indefinitely mode, and a 4.8 V to 5.8 V (typical) triangular waveform is
long periods. If the TOPSwitch-HX is held in remote off state for present on the CONTROL pin while in thermal shutdown.
long enough time to allow the CONTROL pin to discharge to the
Bandgap Reference
internal supply undervoltage threshold of 4.8 V (approximately
All critical TOPSwitch-HX internal voltages are derived from a
32 ms for a 47 F CONTROL pin capacitance), the CONTROL
temperature-compensated bandgap reference. This voltage
pin goes into the hysteretic mode of regulation. In this mode,
reference is used to generate all other internal current
the CONTROL pin goes through alternate charge and discharge
references, which are trimmed to accurately set the switching
cycles between 4.8 V and 5.8 V (see CONTROL pin operation
frequency, MOSFET gate drive current, current limit, and the line
section above) and runs entirely off the high voltage DC input,
OV/UV/OVP thresholds. TOPSwitch-HX has improved circuitry
but with very low power consumption (160 mW typical at
to maintain all of the above critical parameters within very tight
230 VAC with M or X pins open). When the TOPSwitch-HX is
remotely turned on after entering this mode, it will initiate a absolute and temperature tolerances.
normal start-up sequence with soft-start the next time the
High-Voltage Bias Current Source
CONTROL pin reaches 5.8 V. In the worst case, the delay from
This high-voltage current source biases TOPSwitch-HX from the
remote on to start-up can be equal to the full discharge/charge
DRAIN pin and charges the CONTROL pin external capacitance
cycle time of the CONTROL pin, which is approximately 125 ms
during start-up or hysteretic operation. Hysteretic operation
for a 47 F CONTROL pin capacitor. This reduced
occurs during auto-restart, remote OFF and over-temperature
consumption remote off mode can eliminate expensive and
shutdown. In this mode of operation, the current source is
unreliable in-line mechanical switches. It also allows for
switched on and off, with an effective duty cycle of approxi-
microprocessor controlled turn-on and turn-off sequences that
mately 35%. This duty cycle is determined by the ratio of
may be required in certain applications such as inkjet and laser
CONTROL pin charge (IC) and discharge currents (ICD1 and ICD2).
printers.
This current source is turned off during normal operation when
the output MOSFET is switching. The effect of the current
source switching will be seen on the DRAIN voltage waveform
as small disturbances and is normal.

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TOP252-262

Y, E/L and M Package


CONTROL (C)
TOPSwitch-HX
200 A

(Negative Current Sense - ON/OFF,


Current Limit Adjustment)
VBG + VT
EXTERNAL CURRENT LIMIT (X)

VOLTAGE MONITOR (V) (Voltage Sense)


1V
VREF
(Positive Current Sense - Undervoltage,
Overvoltage, ON/OFF, Maximum Duty
Cycle Reduction, Output Over-
voltage Protection)

400 A

PI-4714-071408

Figure 13a. VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pin Input Simplified Schematic.

P and G Package
CONTROL (C)
TOPSwitch-HX
200 A

(Negative Current Sense - ON/OFF,


Current Limit Adjustment)
VBG + VT
MULTI-FUNCTION (M)

VREF
(Positive Current Sense - Undervoltage,
Overvoltage, Maximum Duty Cycle Reduction,
Output Overvoltage Protection)

400 A

PI-4715-071408

Figure 13b. MULTI-FUNCTION (M) Pin Input Simplified Schematic.

14
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TOP252-262

Typical Uses of FREQUENCY (F) Pin

+ +

DC D DC D
Input Input
Voltage CONTROL Voltage CONTROL
C C

S F S F

- -
PI-2654-071700 PI-2655-071700

Figure 14. Full Frequency Operation (132 kHz). Figure 15. Half Frequency Operation (66 kHz).

15
www.powerint.com Rev. H 06/13
TOP252-262

Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins

TOP252-258M TOP254-258Y
+ +
TOP259-261Y
D C X V

S S S S S VXCS F D

DC DC VXCSG D
Input Input
D S C
Voltage Voltage
D V D V
C S D
CONTROL CONTROL
C C
CS D

S X F S X G
- -
PI-4716-020508 PI-4984-020708

Figure 16a. Three Terminal Operation (VOLTAGE MONITOR and EXTERNAL Figure 16b. Three Terminal Operation (VOLTAGE MONITOR and EXTERNAL
CURRENT LIMIT Features Disabled. FREQUENCY Pin Tied to CURRENT LIMIT Features Disabled for TOP259-261 Y Packages.
SOURCE or CONTROL Pin) for TOP254-258 Y Packages.

+ + VUV = IUV RLS + VV (IV = IUV)


eSIP L Package eSIP E Package VOV = IOV RLS + VV (IV = IOV)

For RLS = 4 M
VXC FS D VXC FS D RLS 4 M VUV = 102.8 VDC
VOV = 451 VDC
DC DC
Input Input DCMAX@100 VDC = 76%
Voltage C S D
Voltage DCMAX@375 VDC = 41%
C S D
D V D V
CONTROL CONTROL
C C

S X F S
- -
PI-4956-071708 PI-4717-120307

Figure 16c. Three Terminal Operation (VOLTAGE MONITOR and EXTERNAL Figure 17. Line-Sensing for Undervoltage, Overvoltage and Line Feed-Forward.
CURRENT LIMIT Features Disabled. FREQUENCY Pin Tied to
SOURCE or CONTROL Pin) for TOP252-262 L and E Packages.

VUV = IUV RLS + VV (IV = IUV)


VOV = IOV RLS + VV (IV = IOV)
+ VUV = IUV RLS + VV (IV = IUV)
+
VOV = IOV RLS + VV (IV = IOV) For RLS = 4 M
VUV = 102.8 VDC
For RLS = 4 M VOV = 451 VDC
VUV = 102.8 VDC Sense Output Voltage
RLS 4 M RLS 4 M
VOV = 451 VDC
DC DC ROVP
Sense Output Voltage VROVP
Input Input DCMAX @ 100 VDC = 76%
Voltage DCMAX @ 100 VDC = 76% Voltage DCMAX @ 375 VDC = 41%
DCMAX @ 375 VDC = 41%
D V D V
Reset 10 k CONTROL CONTROL
QR C C
ROVP >3k

S S
- -
PI-4756-121007 PI-4719-120307

Figure 18. Line-Sensing for Undervoltage, Overvoltage, Line Feed-Forward and Figure 19. Line-Sensing for Undervoltage, Overvoltage, Line Feed-Forward and
Latched Output Overvoltage Protection. Hysteretic Output Overvoltage Protection.

16
Rev. H 06/13 www.powerint.com
TOP252-262

Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins (cont.)

+ VUV = RLS IUV + VV (IV = IUV) +


VOV = IOV RLS + VV (IV = IOV)
4 M 4 M
For Values Shown
For Values Shown
VUV = 103.8 VDC
VOV = 457.2 VDC
RLS RLS

DC DC
Input 40 k Input 55 k
Voltage Voltage
1N4148
D V D V

CONTROL CONTROL
C C
6.2 V

S
- S -
PI-4720-120307 PI-4721-120307

Figure 20. Line Sensing for Undervoltage Only (Overvoltage Disabled). Figure 21. Line-Sensing for Overvoltage Only (Undervoltage Disabled). Maximum
Duty Cycle Reduced at Low Line and Further Reduction with
Increasing Line Voltage.

+ For RIL = 12 k + ILIMIT = 100% @ 100 VDC


ILIMIT = 61% ILIMIT = 53% @ 300 VDC
RLS 2.5 M
For RIL = 19 k TOP259-261YN would
ILIMIT = 37% use the G pin as the
return for RIL.
DC See Figure 55b for other DC
Input D resistor values (RIL). Input D
Voltage CONTROL
Voltage CONTROL
C C

TOP259-261YN would
S X use the G pin as the S X
return for RIL.
RIL RIL
6 k
- -
PI-4722-021308 PI-4723-011008

Figure 22. External Set Current Limit. Figure 23. Current Limit Reduction with Line Voltage.

+ QR can be an optocoupler
+ QR can be an optocoupler
output or can be replaced by output or can be replaced
a manual switch. by a manual switch.

TOP259-261YN would For RIL = 12 k


use the G pin as the ILIMIT = 61%
DC return for QR. DC
Input D Input D For RIL = 19 k
Voltage CONTROL Voltage CONTROL ILIMIT = 37%
C C
TOP259-261YN would
S X S X use the G pin as the
return for QR.
QR ON/OFF RIL
47 K QR ON/OFF
- - 16 k
PI-2625-011008 PI-4724-011008

Figure 24. Active-on (Fail Safe) Remote ON/OFF. Figure 25. Active-on Remote ON/OFF with Externally Set Current Limit.

17
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TOP252-262

Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins (cont.)

PI-4726-021308
+ VUV = IUV RLS + VV (IV = IUV) + VUV = IUV x RLS + VV (IV = IUV)
VOV = IOV RLS + VV (IV = IoV) VOV = IOV x RLS + VV (IV = IoV)
For RLS = 4 M
RLS 4 M DCMAX@100 VDC = 76% RLS 4 M
DCMAX@375 VDC = 41% VUV = 102.8 VDC
VOV = 451 VDC
QR can be an optocoupler
DC output or can be replaced DC DCMAX @ 100 VDC = 76%
Input D V Input D V DCMAX @ 375 VDC = 41%
by a manual switch.
Voltage CONTROL Voltage CONTROL
C For RIL = 12 k C
ILIMIT = 61% For RIL = 12 k
TOP259-261YN would TOP259-261YN would
S X ILIMIT = 61%
use the G pin as the use the G pin as the S X
return for QR. RIL return for RIL. See Figure 55b for
QR ON/OFF RIL other resistor values
- 16 k - 12 k (RIL) to select different
ILIMIT values.
PI-4725-011008

Figure 26. Active-on Remote ON/OFF with Line-Sense and External Figure 27. Line Sensing and Externally Set Current Limit.
Current Limit.

+ VUV = IUV RLS + VV (IV = IUV)


VOV = IOV RLS + VV (IV = IOV)

For RLS = 4 M
RLS 4 M VUV = 102.8 VDC
VOV = 451 VDC
DC
Sense Output Voltage
Input
Voltage DCMAX @ 100 VDC = 76%
DCMAX @ 375 VDC = 41%
D V
Reset 10 k CONTROL
QR C

S
-
PI-4756-121007

Figure 28. Line-Sensing for Undervoltage, Overvoltage, Line Feed-Forward and


Latched Output Overvoltage Protection with Device Reset.

Typical Uses of MULTI-FUNCTION (M) Pin

+ +
VUV = IUV RLS + VM (IM = IUV)
VOV = IOV RLS + VM (IM = IOV)
D C
M For RLS = 4 M
RLS 4 M VUV = 102.8 VDC
S S S S
VOV = 451 VDC
DC DC
Input Input DCMAX @ 100 VDC = 76%
Voltage Voltage DCMAX @ 375 VDC = 41%
D M D M
D S C
CONTROL CONTROL
C C

S
- S -
PI-4727-061207 PI-4728-120307

Figure 29. Three Terminal Operation (MULTI-FUNCTION Features Disabled). Figure 30. Line Sensing for Undervoltage, Overvoltage and Line Feed-Forward.

18
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TOP252-262

Typical Uses of MULTI-FUNCTION (M) Pin (cont.)

VUV = IUV RLS + VM (IM = IUV)


VOV = IOV RLS + VM (IM = IOV)
+ VUV = IUV RLS + VM (IM = IUV)
+
VOV = IOV RLS + VM (IM = IOV) For RLS = 4 M
VUV = 102.8 VDC
For RLS = 4 M VOV = 451 VDC
VUV = 102.8 VDC Sense Output Voltage
RLS 4 M RLS 4 M
VOV = 451 VDC
DC DC ROVP
Sense Output Voltage VROVP
Input Input
Voltage DCMAX @ 100 VDC = 76% Voltage
DCMAX @ 375 VDC = 41% DCMAX @ 100 VDC = 76%
D M D M
DCMAX @ 375 VDC = 41%
CONTROL CONTROL
C C
ROVP >3k

S S
- -
PI-4729-120307 PI-4730-120307

Figure 31. Line Sensing for Undervoltage, Overvoltage, Line Feed-Forward and Figure 32. Line Sensing for Undervoltage, Overvoltage, Line Feed-Forward and
Latched Output Overvoltage Protection. Hysteretic Output Overvoltage Protection.

+ VUV = RLS IUV + VM (IM = IUV) + VOV = IOV RLS + VM (IM = IOV)
4 M For Values Shown 4 M For Values Shown
VUV = 103.8 VDC VOV = 457.2 VDC
RLS RLS

DC DC
Input 40 k Input 55 k
Voltage Voltage 1N4148
D M D M
CONTROL CONTROL
C C
6.2 V

S S
- -
PI-4731-120307 PI-4732-120307

Figure 33. Line Sensing for Undervoltage Only (Overvoltage Disabled). Figure 34. Line Sensing for Overvoltage Only (Undervoltage Disabled). Maximum
Duty Cycle Reduced at Low Line and Further Reduction with
Increasing Line Voltage.

+ +
For RIL = 12 k ILIMIT = 100% @ 100 VDC
ILIMIT = 61% ILIMIT = 53% @ 300 VDC
RLS 2.5 M
For RIL = 19 k
ILIMIT = 37%
DC DC
Input See Figures 55b for other Input
Voltage resistor values (RIL) to Voltage
select different ILIMIT values.
D M D M
CONTROL RIL 6 k CONTROL
RIL C C

S S
- -
PI-4733-021308 PI-4734-092107

Figure 35. Externally Set Current Limit (Not Normally Required See M Pin Figure 36. Current Limit Reduction with Line Voltage (Not Normally Required
Operation Description). See M Pin Operation Description).

19
www.powerint.com Rev. H 06/13
TOP252-262

Typical Uses of MULTI-FUNCTION (M) Pin (cont.)

+ +
QR can be an optocoupler QR can be an optocoupler
output or can be replaced output or can be replaced
by a manual switch. by a manual switch.

For RIL = 12 k
DC DC ILIMIT = 61%
Input Input
Voltage Voltage For RIL = 19 k

D M D M ILIMIT = 37%
RIL
CONTROL CONTROL
QR C C
ON/OFF ON/OFF QR
47 k S 16 k S
- -
PI-2519-040501 PI-4735-092107

Figure 37. Active-on (Fail Safe) Remote ON/OFF. Figure 38. Active-on Remote ON/OFF with Externally Set Current Limit
(see M Pin Operation Description).

+ QR can be an optocoupler
+ VUV = IUV RLS + VM (IM = IUV)
output or can be replaced VOV = IOV RLS + VM (IM = IOV)
by a manual switch.
For RLS = 4 M
RLS 4 M VUV = 102.8 VDC
VOV = 451 VDC
ON/OFF QR DC
DC 7 k Sense Output Voltage
Input Input
Voltage Voltage DCMAX @ 100 VDC = 76%
RMC 24 k RMC = 2RIL DCMAX @ 375 VDC = 41%
D M D M
CONTROL Reset 10 k CONTROL
RIL 12 k C QR C

S S
- -
PI-4736-060607 PI-4757-120307

Figure 39. Active-off Remote ON/OFF with Externally Set Current Limit Figure 40. Line-Sensing for Undervoltage, Overvoltage, Line Feed-Forward and
(see M Pin Operation Description). Latched Output Overvoltage Protection with Device Reset.

20
Rev. H 06/13 www.powerint.com
TOP252-262

Application Examples winding. Zener VR2 will break down and current will flow into
the M pin of the TOPSwitch initiating a hysteretic overvoltage
A High Efficiency, 35 W, Dual Output - Universal Input protection with automatic restart attempts. Resistor R5 will limit
Power Supply the current into the M pin to < 336 mA, thus setting hysteretic
The circuit in Figure 41 takes advantage of several of the OVP. If latching OVP is desired, the value of R5 can be reduced
TOPSwitch-HX features to reduce system cost and power to 20 W.
supply size and to improve efficiency. This design delivers
35 W total continuous output power from a 90 VAC to 265 VAC The output voltage is controlled using the amplifier TL431.
input at an ambient of 50 C in an open frame configuration. A Diode D9, capacitor C20 and resistor R16 form the soft finish
nominal efficiency of 84% at full load is achieved using circuit. At startup, capacitor C20 is discharged. As the output
TOP258P. With a DIP-8 package, this design provides 35 W voltage starts rising, current flows through the optocoupler diode
continuous output power using only the copper area on the inside U2A, resistor R13 and diode D9 to charge capacitor C20.
circuit board underneath the part as a heat sink. The different This provides feedback to the circuit on the primary side. The
operating modes of the TOPSwitch-HX provide significant current in the optocoupler diode U2A gradually decreases as the
improvement in the no-load, standby, and light load performance capacitor C20 becomes charged and the control amplifier IC U3
of the power supply as compared to the previous generations of becomes operational. This ensures that the output voltage
the TOPSwitch. increases gradually and settles to the final value without any
overshoot. Resistor R16 ensures that the capacitor C20 is
Resistors R3 and R4 provide line sensing, setting line UV at maintained charged at all times after startup, which effectively
100 VDC and line OV at 450 VDC. isolates C20 from the feedback circuit after startup. Capacitor
C20 discharges through R16 when the supply shuts down.
Diode D5, together with resistors R6, R7, capacitor C6 and TVS
VR1, forms a clamp network that limits the drain voltage of the Resistors R20, R21 and R18 form a voltage divider network.
TOPSwitch after the integrated MOSFET turns off. TVS VR1 The output of this divider network is primarily dependent on the
provides a defined maximum clamp voltage and typically only divider circuit formed using R20 and R21 and will vary to some
conducts during fault conditions such as overload. This allows extent for changes in voltage at the 15 V output due to the
the RCD clamp (R6, R7, C6 and D5) to be sized for normal connection of resistor R18 to the output of the divider network.
operation, thereby maximizing efficiency at light load. Should Resistor R19 and Zener VR3 improve cross regulation in case
the feedback circuit fail, the output of the power supply may only the 5 V output is loaded, which results in the 12 V output
exceed regulation limits. This increased voltage at output will operating at the higher end of the specification.
also result in an increased voltage at the output of the bias

C6 C7 R11 C12
3.9 nF 2.2 nF 33 470 pF
1 kV 250 VAC 100 V

D7 C13 C14 C15


R6 T1 SB560 680 F 680 F L2 220 F
22 k 2 EER28 7 25 V 25 V 3.3 H 25 V +12 V,
2W 2A
D1 D2 VR1 C16 C18
P6KE200A 470 pF R12 L3 RTN
1N4937 1N4007 33 3.3 H 220 F
100 V 10 V
3 11 +5 V,
2.2 A
R7 D8
20 SB530
4 9
1/2 W RTN
C10 C17
6 2200 F
10 F
D5 R10 50 V C11 10 V
D3 D4 R3 D6
2.0 M FR106 FR106 4.7 2.2 nF R19
1N4937 1N4007 250 VAC
5 10
L1 R4
6.8 mH 2.0 M VR3
R14 BZX55B8V2
C4 R13 22 8.2 V
R1 R2 100 F 330 C19 2%
1 M 1 M 400 V VR2 1.0 F
R5 1N5250B 50 V
5.1 k 20 V
C3 R15
220 nF 1 k
F1 275 VAC
3.15 A
U2B U2A
TOPSwitch-HX PS2501- PS2501-
RT1 O D M U1
L 10 t 1-H-A 1-H-A R18 R20
CONTROL TOP258PN 196 k 12.4 k
E C 1% 1%
R16 R17
10 k 10 k
N S R8 D9
C8 6.8 1N4148
90 - 265 C21
VAC 100 nF
50 V C9 220 nF
47 F 50 V
16 V C20
10 F U3 R21
50 V TL431 10 k
2% 1%
PI-4747-020508

Figure 41. 35 W Dual Output Power Supply using TOP258PN.

21
www.powerint.com Rev. H 06/13
TOP252-262

A High Efficiency, 150 W, 250 380 VDC Input dissipated by VR1 and VR3, the leakage energy instead being
Power Supply dissipated by R1 and R2. However, VR1 and VR3 are essential
The circuit shown in Figure 42 delivers 150 W (19 V @ 7.7 A) at to limit the peak drain voltage during start-up and/or overload
84% efficiency using a TOP258Y from a 250 VDC to 380 VDC conditions to below the 700 V rating of the TOPSwitch-HX
input. A DC input is shown, as typically at this power level a MOSFET. The schematic shows an additional turn-off snubber
power factor correction stage would precede this supply, circuit consisting of R20, R21, R22, D5 and C18. This reduces
providing the DC input. Capacitor C1 provides local decoupling, turn-off losses in the TOPSwitch-HX.
necessary when the supply is remote from the main PFC output
capacitor. The secondary is rectified and smoothed by D2, D3 and C5,
C6, C7 and C8. Two windings are used and rectified with
The flyback topology is still usable at this power level due to the separate diodes D2 and D3 to limit diode dissipation. Four
high output voltage, keeping the secondary peak currents low capacitors are used to ensure their maximum ripple current
enough so that the output diode and capacitors are reasonably specification is not exceeded. Inductor L1 and capacitors C15
sized. In this example, the TOP258YN is at the upper limit of its and C16 provide switching noise filtering.
power capability.
Output voltage is controlled using a TL431 reference IC and
Resistors R3, R6 and R7 provide output power limiting, R15, R16 and R17 to form a potential divider to sense the
maintaining relatively constant overload power with input voltage. output voltage. Resistor R12 and R24 together limit the
Line sensing is implemented by connecting a 4 MW resistor from optocoupler LED current and set overall control loop DC gain.
the V pin to the DC rail. Resistors R4 and R5 together form the Control loop compensation is achieved using components C12,
4 MW line sense resistor. If the DC input rail rises above C13, C20 and R13. Diode D6, resistor R23 and capacitor C19
450 VDC, then TOPSwitch-HX will stop switching until the form a soft finish network. This feeds current into the control
voltage returns to normal, preventing device damage. pin prior to output regulation, preventing output voltage
overshoot and ensuring startup under low line, full load
Due to the high primary current, a low leakage inductance conditions.
transformer is essential. Therefore, a sandwich winding with a
copper foil secondary was used. Even with this technique, the Sufficient heat sinking is required to keep the TOPSwitch-HX
leakage inductance energy is beyond the power capability of a device below 110 C when operating under full load, low line
simple Zener clamp. Therefore, R1, R2 and C3 are added in and maximum ambient temperature. Airflow may also be
parallel to VR1 and VR3, two series TVS diodes being used to required if a large heat sink area is not acceptable.
reduce dissipation. During normal operation, very little power is

2.2 nF R14 C14


250 VAC 22 47 pF
R1 R2 C4 0.5 W 1 kV
250 - 380 68 k 68 k C5-C8 C15-C16
VDC 2W 2W 820 F 820 F +19 V,
25 V L1 25 V 7.7 A
F1 RT1 O 1 13,14
C3
4A 5t 3.3 H
R6 R4 4.7 nF
4.7 M 2.0 M 1 kV D2
MBR20100CT
11
D1 12
BYV26C D3 RTN
R7 R5 4 MBR20100CT
4.7 M 2.0
VR1, VR3
P6KE100A 9,10
7
C1 D4
22 F 1N4148 R18 C17
5 22 47 pF
400 V R20 0.5 W 1 kV C20
1.5 k T1 R8 R12 1.0 F
2W EI35 4.7 240 50 V
0.125 W
C9
D5 10 F R24
1N4937 VR2 50 V 30
R21 1N5258B 0.125 W R16
R19 R23
1.5 k 4.7 36 V 31.6 k
15 k U2
2W 0.125 W 1%
PC817A
TOPSwitch-HX R11 R17
C12
U1 1 k 4.7 nF 562
D V TOP258YN 0.125 W 50 V
R22 1%
CONTROL
1.5 k C U2
2W PC817B C13
R13 100 nF
56 k
S X F R10 0.125 W 50 V
6.8 D6
C11 C19 1N4148
100 nF 10 F
R3 C18 50 V C10
47 F 50 V U3 R15
8.06 k 120 pF
1% 10 V TL431 4.75 k
1 kV 2% 1%
PI-4795-092007

Figure 42. 150 W, 19 V Power Supply using TOP258YN.

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Rev. H 06/13 www.powerint.com
TOP252-262

A High Efficiency, 20 W continuous 80 W Peak, Universal TOPSwitch-HX and R20, C9, R22 and VR5. Should the bias
Input Power Supply winding output voltage across C13 rise due to output overload
The circuit shown in Figure 43 takes advantage of several of or an open loop fault (opto coupler failure), then VR5 conducts
TOPSwitch-HX features to reduce system cost and power triggering the latching shutdown. To prevent false triggering
supply size and to improve power supply efficiency while due to short duration overload, a delay is provided by R20, R22
delivering significant peak power for a short duration. This and C9.
design delivers continuous 20 W and peak 80 W at 32 V from
an 90 VAC to 264 VAC input. A nominal efficiency of 82% at full To reset the supply following a latching shutdown, the V pin
load is achieved using TOP258MN. The M-package part has an must fall below the reset threshold. To prevent the long reset
optimized current limit to enable design of power supplies delay associated with the input capacitor discharging, a fast AC
capable of delivering high power for a short duration. reset circuit is used. The AC input is rectified and filtered by
D13 and C30. While the AC supply is present, Q3 is on and Q1
Resistor R12 sets the current limit of the part. Resistors R11 is off, allowing normal device operation. However when AC is
and R14 provide line feed forward information that reduces the removed, Q1 pulls down the V pin and resets the latch. The supply
current limit with increasing DC bus voltage, thereby maintaining will then return to normal operation when AC is again applied.
a constant overload power level with increasing line voltage.
Resistors R1 and R2 implement the line undervoltage and Transistor Q2 provides an additional lower UV threshold to the
overvoltage function and also provide feed forward compensation level programmed via R1, R2 and the V pin. At low input AC
for reducing line frequency ripple at the output. The overvoltage voltage, Q2 turns off, allowing the X pin to float and thereby
feature inhibits TOPSwitch-HX switching during a line surge disabling switching.
extending the high voltage withstand to 700 V without device
damage. A simple feedback circuit automatically regulates the output
voltage. Zener VR3 sets the output voltage together with the
The snubber circuit comprising of VR7, R17, R25, C5 and D2 voltage drop across series resistor R8, which sets the DC gain
limits the maximum drain voltage and dissipates energy stored in of the circuit. Resistors R10 and C28 provide a phase boost to
the leakage inductance of transformer T1. This clamp configuration improve loop bandwidth.
maximizes energy efficiency by preventing C5 from discharging
below the value of VR7 during the lower frequency operating Diodes D6 and D7 are low-loss Schottky rectifiers, and
modes of TOPSwitch-HX. Resistor R25 damps high frequency capacitor C20 is the output filter capacitor. Inductor L3 is a
ringing for reduced EMI. common mode choke to limit radiated EMI when long output
cables are used and the output return is connected to safety
A combined output overvoltage and over power protection earth ground. Example applications where this occurs include
circuit is provided via the latching shutdown feature of PC peripherals, such as inkjet printers.
C8 R19 C26
1 nF 68 100 pF
250 VAC 0.5 W 1 kV
C20 C31 32 V
330 F 22 F
50 V L2 50 V L3 625 mA, 2.5 APK
1 10
3.3 H
D6-D7
D8 D9 VR7 2 STPS3150 RTN
R25 9
1N4007 1N4007 BZY97C150
C3 100 47 H
120 F 150 V 5
400 V C29
to R11
3
NC
C13
10 F 220 nF
R1 C10
RT1 2 M 3.6 M R17 C5 50 V 50 V
D11 D10 1 nF
1N4007 1N4007 10 1 k 10 nF 4 250 VAC
0.5 W 1 kV
T1 D5
EF25 LL4148 R10
56 R8
L1 1.5 k
5.3 mH D2
R2 R14 FR107 C28
D13 2 M 3.6 M 330 nF
1N4007 50 V
R23 R24 VR3
1N5255B
1 M 1 M 28 V
U2A
VR5 R20 PC817D
R3 1N5250B C9
R22 1 F 130 k
2 M 20 V
C1 D V 2 M 100 V
F1 R21
220 nF 3.15 A CONTROL R9
275 VAC 1 M 2 k
R4 0.125 W
2 M
C
90 - 264 PI-4833-092007
VAC S X
R15
1 k R6
R12 TOPSwitch-HX
Q1 U4 C6 6.8
7.5 k 100 nF
C30 2N3904 1% TOP258MN
50 V
100 nF
400 V Q2
Q3 C7
2N3904
2N3904 47 F
R26 16 V
68 k R18
39 k

Figure 43. 20 W Continuous, 80 W Peak, Universal Input Power Supply using TOP258MN.

23
www.powerint.com Rev. H 06/13
TOP252-262

A High Efficiency, 65 W, Universal Input Power Supply The secondary output from the transformer is rectified by diode
The circuit shown in Figure 44 delivers 65 W (19 V @ 3.42 A) at D2 and filtered by capacitors C13 and C14. Ferrite Bead L3 and
88% efficiency using a TOP260EN operating over an input capacitors C15 form a second stage filter and effectively reduce
voltage range of 90 VAC to 265 VAC. the switching noise to the output.

Capacitors C1 and C6 and inductors L1 and L2 provide Output voltage is controlled using a LM431 reference IC.
common mode and differential mode EMI filtering. Capacitor C2 Resistor R19 and R20 form a potential divider to sense the
is the bulk filter capacitor that ensures low ripple DC input to the output voltage. Resistor R16 limits the optocoupler LED current
flyback converter stage. Capacitor C4 provides decoupling for and sets the overall control loop DC gain. Control loop
switching currents reducing differential mode EMI. compensation is achieved using C18 and R21. The components
connected to the control pin on the primary side C8, C9 and
In this example, the TOP260EN is used at reduced current limit R15 set the low frequency pole and zero to further shape the
to improve efficiency. control loop response. Capacitor C17 provides a soft finish
during startup. Optocoupler U2 is used for isolation of the
Resistors R5, R6 and R7 provide power limiting, maintaining feedback signal.
relatively constant overload power with input voltage. Line
sensing is implemented by connecting a 4 MW impedance from Diode D4 and capacitor C10 form the bias winding rectifier and
the V pin to the DC rail. Resistors R3 and R4 together form the filter. Should the feedback loop break due to a defective
4 MW line sense resistor. If the DC input rail rises above component, a rising bias winding voltage will cause the Zener
450 VDC, then TOPSwitch-HX will stop switching until the VR2 to break down and trigger the over voltage protection
voltage returns to normal, preventing device damage. which will inhibit switching.

This circuit features a high efficiency clamp network consisting An optional secondary side over voltage protection feature
of diode D1, zener VR1, capacitor C5 together with resistors R8 which offers higher precision (as compared to sensing via the
and R9. The snubber clamp is used to dissipate the energy of bias winding) is implemented using VR3, R18 and U3. Excess
the leakage reactance of the transformer. At light load levels, voltage at the output will cause current to flow through the
very little power is dissipated by VR1 improving efficiency as optocoupler U3 LED which in turn will inject current in the V-pin
compared to a conventional RCD clamp network. through resistor R13, thereby triggering the over voltage
protection feature.

C6 C12
2.2 nF 1 nF R16
250 VAC 100 V 33
C5 VR1 C13 C14 L3 C15
2.2 nF BZY97C180 T1 470 F 470 F Ferrite 47 F
1 kV 25 V 25 V Bead 25 V 19 V, 3.42 A
180 V 4 RM10 FL1

D2
3KBP08M MBR20100CT
BR1 5 FL2
R8 R9 RTN
100 1 k
C10 VR2
6 22 F R10 VR3
1N5248B
R3 R5 3 50 V 73.2 k 18 V BZX79-C22
2.0 M 5.1 M 22 V
C11
D1 100 nF
DL4937 50 V
2
D4 BAV19WS R11
L1 2 M
12 mH R16 R18
R4 R6
2.0 M 6.8 M 680 47
R12
C2 D5 5.1 k U3B
R1 R2 120 F BAV19WS C7 PC357A
2.2 M 2.2 M 400 V 100 nF U3A
C4
100 nF D3 25 V PC357A
400 V BAV19WS
C1 U2A
F1 330 nF LTY817C
U2B
4A 275 VAC TOPSwitch-HX R13 LTY817C
U1 5.1
D V TOP260EN
L R14
CONTROL D6 R19
100 1N4148
E C 68.1 k
C18
100 nF
N R15
S X F
6.8 C16
90 - 265 R21
VAC C8 1 F 1 k
R7 100 nF C9 50 V
C3 15 k 47 F
470 pF 50 V
1% 16 V C17 U4
250 VAC 33 F LM431
35 V 2% R20
L2 10 k
Ferrite Bead

PI-4998-021408

Figure 44. 65 W, 19 V Power Supply Using TOP260EN.

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Rev. H 06/13 www.powerint.com
TOP252-262

Key Application Considerations

TOPSwitch-HX vs. TOPSwitch-GX


features eliminate the need for additional discrete components.
Table 4 compares the features and performance differences Other features increase the robustness of design, allowing cost
between TOPSwitch-HX and TOPSwitch-GX. Many of the new savings in the transformer and other power components.

TOPSwitch-HX vs. TOPSwitch-GX


Function TOPSwitch-GX TOPSwitch-HX TOPSwitch-HX Advantages

EcoSmart Linear frequency reduction to Multi-mode operation with Improved efficiency over load (e.g. at 25% load
30 kHz (@ 132 kHz) for linear frequency reduction to point)
duty cycles < 10% 30 kHz (@ 132 kHz) and Improved standby efficiency
multi-cycle modulation
Improved no-load consumption
(virtually no audible noise)

Output Overvoltage Not available User programmable primary Protects power supply output during open loop fault
Protection (OVP) or secondary hysteretic or Maximum design flexibility
latching OVP

Line Feed-Forward with Duty Linear reduction Dual slope reduction with Improved line ripple rejection
Cycle Reduction lower, more accurate onset Smaller DC bus capacitor
point

Switching Frequency DIP-8 132 kHz 66 kHz Increased output power for given MOSFET size due
Package to higher efficiency

Lowest MOSFET On 3.0 W (TOP246P) 1.8 W (TOP258P) Increased output power in designs without external
Resistance in DIP-8 Package heat sink

I2f Trimming Not available -10% / +20% Increased output power for given core size
Reduced over-load power

Auto-restart Duty Cycle 5.6% 2% Reduced delivered average output power during
open loop faults

Frequency Jitter 4 kHz @ 132 kHz 5 kHz @ 132 kHz Reduced EMI filter cost
2 kHz @ 66 kHz 2.5 kHz @ 66 kHz

Thermal Shutdown 130 C to 150 C 135 C to 150 C Increased design margin

External Current Limit 30%-100% of ILIMIT 30%-100% of ILIMIT, additional Reduced tolerances when current limit is set
trim at 0.7 ILIMIT externally

Line UV Detection Threshold 50 mA (2 MW sense 25 mA (4 MW sense Reduced dissipation for lower no-load consumption
impedance) impedance)

Soft-Start 10 ms duty cycle and current 17 ms sweep through Reduced peak current and voltage component
limit ramp multi-mode characteristic stress at startup
Smooth output voltage rise

Table 4. Comparison Between TOPSwitch-GX and TOPSwitch-HX.

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TOP252-262

TOPSwitch-HX Design Considerations sinking, air circulation, etc.). The higher DCMAX of TOPSwitch-HX,
along with an appropriate transformer turns ratio, can allow the
Power Table use of a 80 V Schottky diode for higher efficiency on output
The data sheet power table (Table 1) represents the maximum voltages as high as 15 V (see Figure 41).
practical continuous output power based on the following
conditions: Bias Winding Capacitor
1. 12 V output. Due to the low frequency operation at no-load, a 10 mF bias
2. Schottky or high efficiency output diode. winding capacitor is recommended.
3. 135 V reflected voltage (VOR) and efficiency estimates.
4. A 100 VDC minimum for 85-265 VAC and 250 VDC mini- Soft-Start
mum for 230 VAC. Generally, a power supply experiences maximum stress at
5. Sufficient heat sinking to keep device temperature 100 C. start-up before the feedback loop achieves regulation. For a
6. Power levels shown in the power table for the M/P package period of 17 ms, the on-chip soft-start linearly increases the
device assume 6.45 cm2 of 610 g/m2 copper heat sink area drain peak current and switching frequency from their low
in an enclosed adapter, or 19.4 cm2 in an open frame. starting values to their respective maximum values. This
causes the output voltage to rise in an orderly manner, allowing
The provided peak power depends on the current limit for the time for the feedback loop to take control of the duty cycle.
respective device. This reduces the stress on the TOPSwitch-HX MOSFET, clamp
circuit and output diode(s), and helps prevent transformer
TOPSwitch-HX Selection saturation during start-up. Also, soft-start limits the amount of
Selecting the optimum TOPSwitch-HX depends upon required output voltage overshoot and, in many applications, eliminates
maximum output power, efficiency, heat sinking constraints, the need for a soft-finish capacitor.
system requirements and cost goals. With the option to
externally reduce current limit, an Y, E/L or M package EMI
TOPSwitch-HX may be used for lower power applications The frequency jitter feature modulates the switching frequency
where higher efficiency is needed or minimal heat sinking is over a narrow band as a means to reduce conducted EMI peaks
available. associated with the harmonics of the fundamental switching
frequency. This is particularly beneficial for average detection
Input Capacitor mode. As can be seen in Figure 45, the benefits of jitter increase
The input capacitor must be chosen to provide the minimum with the order of the switching harmonic due to an increase in
DC voltage required for the TOPSwitch-HX converter to frequency deviation. Devices in the P, G or M package and
maintain regulation at the lowest specified input voltage and TOP259-261YN operate at a nominal switching frequency of
maximum output power. Since TOPSwitch-HX has a high 66 kHz. The FREQUENCY pin of devices in the TOP254-258 Y
DCMAX limit and an optimized dual slope line feed forward for and E packages offer a switching frequency option of 132 kHz or
ripple rejection, it is possible to use a smaller input capacitor. 66 kHz. In applications that require heavy snubber on the drain
For TOPSwitch-HX, a capacitance of 2 mF per watt is possible node for reducing high frequency radiated noise (for example,
for universal input with an appropriately designed transformer. video noise sensitive applications such as VCRs, DVDs, monitors,
TVs, etc.), operating at 66 kHz will reduce snubber loss, resulting
Primary Clamp and Output Reflected Voltage VOR in better efficiency. Also, in applications where transformer size is
A primary clamp is necessary to limit the peak TOPSwitch-HX not a concern, use of the 66 kHz option will provide lower EMI
drain to source voltage. A Zener clamp requires few parts and and higher efficiency. Note that the second harmonic of 66 kHz
takes up little board space. For good efficiency, the clamp is still below 150 kHz, above which the conducted EMI
Zener should be selected to be at least 1.5 times the output specifications get much tighter. For 10 W or below, it is possible
reflected voltage VOR, as this keeps the leakage spike conduction to use a simple inductor in place of a more costly AC input
time short. When using a Zener clamp in a universal input common mode choke to meet worldwide conducted EMI limits.
application, a VOR of less than 135 V is recommended to allow
for the absolute tolerances and temperature variations of the Transformer Design
Zener. This will ensure efficient operation of the clamp circuit It is recommended that the transformer be designed for
and will also keep the maximum drain voltage below the rated maximum operating flux density of 3000 Gauss and a peak flux
breakdown voltage of the TOPSwitch-HX MOSFET. A high VOR density of 4200 Gauss at maximum current limit. The turns
is required to take full advantage of the wider DCMAX of ratio should be chosen for a reflected voltage (VOR) no greater
TOPSwitch-HX. An RCD clamp provides tighter clamp voltage than 135 V when using a Zener clamp or 150 V (max) when
tolerance than a Zener clamp and allows a VOR as high as 150 using an RCD clamp with current limit reduction with line
V. RCD clamp dissipation can be minimized by reducing the voltage (overload protection). For designs where operating
external current limit as a function of input line voltage (see current is significantly lower than the default current limit, it is
Figures 23 and 36). The RCD clamp is more cost effective than recommended to use an externally set current limit close to the
the Zener clamp but requires more careful design (see Quick operating peak current to reduce peak flux density and peak
Design Checklist). power (see Figures 22 and 35). In most applications, the tighter
current limit tolerance, higher switching frequency and soft-start
Output Diode features of TOPSwitch-HX contribute to a smaller transformer
The output diode is selected for peak inverse voltage, output when compared to TOPSwitch-GX.
current, and thermal conditions in the application (including heat

26
Rev. H 06/13 www.powerint.com
TOP252-262

80 Primary Side Connections

PI-2576-010600
70 Use a single point (Kelvin) connection at the negative terminal of
the input filter capacitor for the TOPSwitch-HX SOURCE pin
60 and bias winding return. This improves surge capabilities by
Amplitude (dBV)

50 returning surge currents from the bias winding directly to the


40
input filter capacitor. The CONTROL pin bypass capacitor
should be located as close as possible to the SOURCE and
30 CONTROL pins, and its SOURCE connection trace should not
20 be shared by the main MOSFET switching currents. All
SOURCE pin referenced components connected to the
-10
MULTI-FUNCTION (M-pin), VOLTAGE MONITOR (V-pin) or
0 EXTERNAL CURRENT LIMIT (X-pin) pins should also be located
-10
EN55022B (QP) closely between their respective pin and SOURCE. Once again,
EN55022B (AV)
the SOURCE connection trace of these components should not
-20 be shared by the main MOSFET switching currents. It is very
0.15 1 10 30
critical that SOURCE pin switching currents are returned to the
Frequency (MHz) input capacitor negative terminal through a separate trace that
Figure 45a. Fixed Frequency Operation Without Jitter.
is not shared by the components connected to CONTROL,
MULTI-FUNCTION, VOLTAGE MONITOR or EXTERNAL
CURRENT LIMIT pins. This is because the SOURCE pin is also
80
PI-2577-010600 the controller ground reference pin. Any traces to the M, V, X or
70 TOPSwitch-HX (with jitter) C pins should be kept as short as possible and away from the
60 DRAIN trace to prevent noise coupling. VOLTAGE MONITOR
resistors (R1 and R2 in Figures 46, 47, 48, R3 and R4 in
Amplitude (dBV)

50 Figure 49, and R14 in Figure 50) should be located close to the
40 M or V pin to minimize the trace length on the M or V pin side.
Resistors connected to the M, V or X pin should be connected
30
as close to the bulk cap positive terminal as possible while
20 routing these connections away from the power switching
-10 circuitry. In addition to the 47 F CONTROL pin capacitor, a
high frequency bypass capacitor in parallel may be used for
0
better noise immunity. The feedback optocoupler output
EN55022B (QP)
-10 EN55022B (AV) should also be located close to the CONTROL and SOURCE
-20 pins of TOPSwitch-HX and away from the drain and clamp
0.15 1 10 30 component traces.
Frequency (MHz) Y Capacitor
Figure 45b. TOPSwitch-HX Full Range EMI Scan (132 kHz With Jitter) With The Y capacitor should be connected close to the secondary
Identical Circuitry and Conditions.
output return pin(s) and the positive primary DC input pin of the
transformer.
Standby Consumption
Frequency reduction can significantly reduce power loss at light Heat Sinking
or no load, especially when a Zener clamp is used. For very low The tab of the Y package (TO-220C) and E package (eSIP-7C)
secondary power consumption, use a TL431 regulator for and L package (eSIP-7F) are internally electrically tied to the
feedback control. A typical TOPSwitch-HX circuit automatically SOURCE pin. To avoid circulating currents, a heat sink
enters MCM mode at no load and the low frequency mode at attached to the tab should not be electrically tied to any primary
light load, which results in extremely low losses under no-load ground/source nodes on the PC board. When using a P (DIP-8),
or standby conditions. G (SMD-8) or M (DIP-10) package, a copper area underneath
the package connected to the SOURCE pins will act as an
High Power Designs effective heat sink. On double sided boards, topside and bottom
The TOPSwitch-HX family contains parts that can deliver up to side areas connected with vias can be used to increase the
333 W. High power designs need special considerations. effective heat sinking area. In addition, sufficient copper area
Guidance for high power designs can be found in the Design should be provided at the anode and cathode leads of the
Guide for TOPSwitch-HX (AN-43). output diode(s) for heat sinking. In Figures 46 to 50 a narrow
trace is shown between the output rectifier and output filter
TOPSwitch-HX Layout Considerations capacitor. This trace acts as a thermal relief between the rectifier
and filter capacitor to prevent excessive heating of the capacitor.
The TOPSwitch-HX has multiple pins and may operate at
high power levels. The following guidelines should be
carefully followed.

27
www.powerint.com Rev. H 06/13
TOP252-262

Isolation Barrier

Optional PCB slot for external C2 Y1-


heatsink in contact with R4 Capacitor
C6
SOURCE pins T1

Input Filter R3 C10 R9 Output

VR1
Capacitor
Rectifier
D1
J1
D3 Output Filter
+ Transformer C7 Capacitor
S D
HV S
U1
- C1 S C
L1
S M
JP1

C3 C4
R8 C5
C8
R1 R2
D2 J2

R14
R13
R11
R6

R7

JP2 U3
R8 R10
Maximize hatched copper C9
areas ( ) for optimum U2
VR2
heat sinking R12

DC
- +
Out PI-4753-070307

Figure 46. Layout Considerations for TOPSwitch-HX Using P Package.

Isolation Barrier

C2
Y1-
Optional PCB slot for external Capacitor
heatsink in contact with R6 C6 T1
SOURCE pins
Input Filter R5 R12 Output
VR1

Capacitor Rectifier
J1 D1
+ D3 Output Filter
HV Transformer C7 Capacitor
-
S D
S
S U1 C L1
C1 S X
S V

JP1
R7 C4
C5 C9 R13
R8
C3 R14
D2 C8
R1 R2 U3
R9
R10

R3 R4 R15
R11

JP2 J2
VR2 R16
Maximize hatched copper U2
areas ( ) for optimum R17
heat sinking

- DC +
Out PI-4752-070307

Figure 47. Layout Considerations for TOPSwitch-HX Using M Package.

28
Rev. H 06/13 www.powerint.com
TOP252-262

Isolation Barrier

C2
Y1-
R4 Capacitor
C6
T1
Input Filter R3

VR1
Capacitor R12 Output
C10 Rectifier
D1
J1 HS1 Output Filter
+ Transformer
D3 Capacitor
HV D
- U1
S C7
F
C L1
C1 V
X

JP1
C4
R7 R10
R13
R1 R2 C5 C9
R8 D2 U3
C8

R14
JP2 J2

R16
R3 R4
R11
R9

R15
U2
R17
VR2 R12

- DC +
Out
PI-4751-070307

Figure 48. Layout Considerations for TOPSwitch-HX Using TOP254-258 Y Package.

Isolation Barrier

C6 Y1-
R7 Capacitor
C7
T1
D5
Input Filter R6 R12 Output Filter
VR1 C16
Capacitor Capacitor

J1 C4 HS1 D8
+ Transformer
HV D
- S G U5
C
X V
C8
C17 L3
R3 R4 C9
JP1 R22 D6 C10 R20
R11 R14 U4 C21 C18
R8
R21
R9
R10

R15

JP2
R5 R17
U2
VR2 R13 J2

- DC +
Out
PI-4977-021408

Figure 49. Layout Considerations for TOPSwitch-HX Using TOP259-261 Y Package.

29
www.powerint.com Rev. H 06/13
TOP252-262

Isolation Barrier

Y1-
Capacitor
Input Filter C6 R7
C7
Capacitor T1 C16 R12
J1 HS1 R6 D5
C4
+
D8
HV
-
Output
H52 Rectifier
U1 VR1 Transformer
C8 S D Output Filter
C17 Capacitor
F R8
C R22
X
R4
V L3
R3
R11 C10 C18
D6
R5 R14 U4
C9 C19
R10 C21
VR2 R20

R9
R17 J2
U2
JP2 R13
R15 R21

- DC +
Out PI-4975-022108

Figure 50a. Layout Considerations for TOPSwitch-HX Using E Package and Operating at 66 kHz.

Isolation Barrier

Y1-
Input Filter C6 R7 Capacitor
C7
Capacitor T1 C16 R12
R6
J1 HS1 D5
C4
+ D8
HV H52 Output
-
Rectifier

U1 VR1 Transformer Output Filter


C8 S
D Capacitor
C9 C17
F R22
C L3
X
R4
V
R3
R11 C10 C18
R8 D6
R5 U4
R14
R10 C21 C19
R20
VR2
R9
R17 J2
U2
JP2 R13
R15 R21

- DC +
Out PI-4976-011410

Figure 50b. Layout Considerations for TOPSwitch-HX Using E Package and Operating at 132 kHz.

30
Rev. H 06/13 www.powerint.com
TOP252-262

Isolation Barrier

Y1-
C6 Capacitor
C7 R12
T1 C16
Input Filter C4 R6
R7
Capacitor VR1
J1 D8
+ HS2
HV Output
- Transformer Rectifier
R22 D5
JP1 X F D Output Filter
Y C S C17
Capacitor
C8
U1
R8
R14
R11

L3
R3
R4
R5

C9
C10 C18
D6
HS1 U4
R10 C19
C21
R20
VR2
R9 J2
Note: Components U1, R8, C8, C9 and R22 R17
U2
are under heat sink HS1. JP2 R13
R15 R21

- DC +
Out PI-5216-091508

Figure 50c. Layout Considerations for TOPSwitch-HX Using L Package and Operating at 132 kHz.

Quick Design Checklist

In order to reduce the no-load input power of TOPSwitch-HX drain current waveforms at start-up for any signs of trans-
designs, the V-pin (or M-pin for P Package) operates at very former saturation and excessive leading edge current spikes.
low current. This requires careful layout considerations when TOPSwitch-HX has a leading edge blanking time of 220 ns
designing the PCB to avoid noise coupling. Traces and to prevent premature termination of the ON-cycle. Verify that
components connected to the V-pin should not be adjacent to the leading edge current spike is below the allowed current
any traces carrying switching currents. These include the drain, limit envelope (see Figure 53) for the drain current waveform
clamp network, bias winding return or power traces from other at the end of the 220 ns blanking period.
converters. If the line sensing features are used, then the sense 3. Thermal check At maximum output power, both minimum
resistors must be placed within 10 mm of the V-pin to minimize and maximum voltage and ambient temperature; verify that
the V pin node area. The DC bus should then be routed to the temperature specifications are not exceeded for
line sense resistors. Note that external capacitance must not TOPSwitch-HX, transformer, output diodes and output
be connected to the V-pin as this may cause misoperation of capacitors. Enough thermal margin should be allowed for
the V pin related functions. the part-to-part variation of the RDS(ON) of TOPSwitch-HX, as
specified in the data sheet. The margin required can either
As with any power supply design, all TOPSwitch-HX designs be calculated from the values in the parameter table or it can
should be verified on the bench to make sure that components be accounted for by connecting an external resistance in
specifications are not exceeded under worst-case conditions. series with the DRAIN pin and attached to the same heat
The following minimum set of tests is strongly recommended: sink, having a resistance value that is equal to the difference
between the measured RDS(ON) of the device under test and
1. Maximum drain voltage Verify that peak VDS does not the worst case maximum specification.
exceed 675 V at highest input voltage and maximum
overload output power. Maximum overload output power Design Tools
occurs when the output is overloaded to a level just before
the power supply goes into auto-restart (loss of regulation). Up-to-date information on design tools can be found at the
2. Maximum drain current At maximum ambient temperature, Power Integrations website: www.powerint.com
maximum input voltage and maximum output load, verify

31
www.powerint.com Rev. H 06/13
TOP252-262

Absolute Maximum Ratings(2)


DRAIN Peak Voltage............................................ -0.3 V to 700 V VOLTAGE MONITOR Pin Voltage............................ -0.3 V to 9 V
DRAIN Peak Current: TOP252.......................................... 0.68 A CURRENT LIMIT Pin Voltage............................... -0.3 V to 4.5 V
DRAIN Peak Current: TOP253.......................................... 1.37 A MULTI-FUNCTION Pin Voltage................................ -0.3 V to 9 V
DRAIN Peak Current: TOP254.......................................... 2.08 A FREQUENCY Pin Voltage .......................................-0.3 V to 9 V
DRAIN Peak Current: TOP255.......................................... 2.72 A Storage Temperature .......................................-65 C to 150 C
DRAIN Peak Current: TOP256.......................................... 4.08 A Operating Junction Temperature.......................-40 C to 150 C
DRAIN Peak Current: TOP257.......................................... 5.44 A Lead Temperature(1).........................................................260 C
DRAIN Peak Current: TOP258.......................................... 6.88 A
DRAIN Peak Current: TOP259.......................................... 7.73 A Notes:
DRAIN Peak Current: TOP260.......................................... 9.00 A 1. 1/16 in. from case for 5 seconds.
DRAIN Peak Current: TOP261........................................ 11.10 A 2. Maximum ratings specified may be applied one at a time
DRAIN Peak Current: TOP262........................................ 11.10 A without causing permanent damage to the product.
CONTROL Voltage.................................................. -0.3 V to 9 V Exposure to Absolute Maximum Rating conditions for
CONTROL Current......................................................... 100 mA extended periods of time may affect product reliability.

Thermal Impedance
Thermal Impedance: Y Package: Notes:
(qJA) ............................................ 80 C/W(1) 1. Free standing with no heat sink.

(qJC) .............................................. 2 C/W(2) 2. Measured at the back surface of tab.

P, G and M Packages: 3. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.

(qJA) ...........................70 C/W(3); 60 C/W(4). 4. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.

(qJC) ........................................... .11 C/W(5) 5. Measured on the SOURCE pin close to plastic interface.
E/L Package:
(qJA) ............................................105 C/W(1)

(qJC) .............................................. 2 C/W(2)

Conditions
SOURCE = 0 V; TJ = -40 to 125 C
Parameter Symbol Min Typ Max Units
See Figure 54
(Unless Otherwise Specified)
Control Functions
FREQUENCY Pin
Connected to SOURCE
TOP252-258Y 119 132 145
TOP255-262L
TOP252-262E
Switching Frequency
in Full Frequency fOSC TJ = 25 C FREQUENCY Pin kHz
Connected to CONTROL
Mode (average)
TOP252-258Y 59.4 66 72.6
TOP255-262L
TOP252-262E
TOP252-258P/G/M
59.4 66 72.6
TOP259-261Y
Frequency Jitter 132 kHz Operation 5
Df kHz
Deviation 66 kHz Operation 2.5
Frequency Jitter
fM 250 Hz
Modulation Rate
IV IV(DC) or IM IM(DC) or
75 78 83
Maximum Duty Cycle DCMAX IC = ICD1 VV, VM = 0 V %
IV or IM = 95 mA 30
Soft-Start Time tSOFT TJ = 25 C 17 ms
TOP252-255 -31 -25 -20
PWM Gain DCreg TJ = 25 C TOP256-258 -27 -22 -17 %/mA
TOP259-262 -25 -20 -15
PWM Gain
See Note A -0.01 %/mA/C
Temperature Drift
TOP252-255 0.9 1.5 2.1
External Bias Current IB 66 kHz Operation TOP256-258 1.0 1.6 2.2 mA
TOP259-262 1.1 1.7 2.4

32
Rev. H 06/13 www.powerint.com
TOP252-262

Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 C Min Typ Max Units
(Unless Otherwise Specified)

Control Functions (cont.)


TOP252-255 1.0 1.6 2.2
External Bias Current IB 132 kHz Operation TOP256-258 1.3 1.9 2.5 mA
TOP259-262 1.6 2.2 2.9
TOP252-255 4.4 5.8
66 kHz Operation TOP256-258 4.7 6.1
CONTROL Current at TOP259-262 5.1 6.5
IC(OFF) mA
0% Duty Cycle TOP252-255 4.6 6.0
132 kHz Operation TOP256-258 5.1 6.5
TOP259-262 6.0 7.4
Dynamic Impedance ZC IC = 4 mA; TJ = 25 C, See Figure 52 10 18 22 W
Dynamic Impedance
0.18 %/C
Temperature Drift
CONTROL Pin Internal
7 kHz
Filter Pole
Upper Peak Current to TJ = 25 C
kPS(UPPER) 50 55 60 %
Set Current Limit Ratio See Note B
Lower Peak Current to TJ = 25 C
kPS(LOWER) 25 %
Set Current Limit Ratio See Note B
Multi-Cycle-
Modulation Switching fMCM(MIN) TJ = 25 C 30 kHz
Frequency
Minimum Multi-Cycle-
TMCM(MIN) TJ = 25 C 135 ms
Modulation On Period
Shutdown/Auto-Restart
Control Pin VC = 0 V -5.0 -3.5 -1.0
IC(CH) TJ = 25 C mA
Charging Current VC = 5 V -3.0 -1.8 -0.6
Charging Current
See Note A 0.5 %/C
Temperature Drift
Auto-Restart
Upper Threshold VC(AR)U 5.8 V
Voltage
Auto-Restart Lower
VC(AR)L 4.5 4.8 5.1 V
Threshold Voltage
Multi-Function (M), Voltage Monitor (V) and External Current Limit (X) Inputs
Auto-Restart
VC(AR)hyst 0.8 1.0 V
Hysteresis Voltage
Auto-Restart Duty
DC(AR) 2 4 %
Cycle
Auto-Restart
f(AR) 0.5 Hz
Frequency
Line Undervoltage Threshold 22 25 27 mA
Threshold Current and IUV TJ = 25 C
Hysteresis (M or V Pin) Hysteresis 14 mA
Line Overvoltage Threshold 107 112 117 mA
Threshold Current and IOV TJ = 25 C
Hysteresis (M or V Pin) Hysteresis 4 mA

33
www.powerint.com Rev. H 06/13
TOP252-262

Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 C Min Typ Max Units
(Unless Otherwise Specified)

Multi-Function (M), Voltage Monitor (V) and External Current Limit (X) Inputs
Output Overvoltage
Latching Shutdown IOV(LS) TJ = 25 C 269 336 403 mA
Threshold Current
VV(TH) or
V or M Pin Reset Voltage TJ = 25 C 0.8 1.0 1.6 V
VM(TH)
Remote ON/OFF Threshold -35 -27 -20
Negative Threshold
IREM (N) TJ = 25 C mA
Current and Hysteresis
(M or X Pin) Hysteresis 5

V or M Pin Short Circuit IV(SC) or


TJ = 25 C VV, VM = VC 300 400 500 mA
Current IM(SC)
X or M Pin Short Circuit IX(SC) or Normal Mode -260 -200 -140
VX, VM = 0 V mA
Current IM(SC) Auto-Restart Mode -95 -75 -55
IV or IM = IUV 2.10 2.8 3.20
V or M Pin Voltage
VV or VM TOP252-TOP257 2.79 3.0 3.21 V
(Positive Current) IV or IM = IOV
TOP258-TOP262 2.83 3.0 3.25
V or M Pin Voltage
VV(hyst) or
Hysteresis (Positive IV or IM = IOV 0.2 0.5 V
VM(hyst)
Current)

X or M Pin Voltage IX or IM = -50 mA 1.23 1.30 1.37


VX or VM V
(Negative Current) IX or IM = -150 mA 1.15 1.22 1.29
Maximum Duty Cycle
IV(DC) or
Reduction Onset IC IB, TJ = 25 C 18.9 22.0 24.2 mA
Threshold Current
IM(DC)

IV(DC) < IV <48 mA or


-1.0
Maximum Duty Cycle IM(DC) < IM <48 mA
TJ = 25 C %/mA
Reduction Slope
IV or IM 48 mA -0.25

X, V or M Pin
0.6 1.0
Remote OFF DRAIN Floating
ID(RMT) VDRAIN = 150 V mA
Supply Current V or M Pin Shorted to
1.0 1.6
CONTROL
From Remote ON to Drain 66 kHz 3.0
Remote ON Delay tR(ON) Turn-On ms
See Note B 132 kHz 1.5

Minimum Time Before Drain 66 kHz 3.0


Remote OFF
tR(OFF) Turn-On to Disable Cycle ms
Setup Time
See Note B 132 kHz 1.5
Frequency Input
FREQUENCY Pin
VF See Note B 2.9 V
Threshold Voltage
FREQUENCY Pin
IF TJ = 25 C VF = VC 10 55 90 mA
Input Current

34
Rev. H 06/13 www.powerint.com
TOP252-262

Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 C Min Typ Max Units
(Unless Otherwise Specified)

Circuit Protection
TOP252PN/GN/MN
di/dt = 45 mA/ms 0.400 0.43 0.460
TJ = 25 C
TOP252EN
di/dt = 90 mA/ms 0.400 0.43 0.460
TJ = 25 C
TOP253PN/GN
di/dt = 80 mA/ms 0.697 0.75 0.803
TJ = 25 C
TOP253MN
di/dt = 90 mA/ms 0.790 0.85 0.910
TJ = 25 C
TOP253EN
di/dt = 180 mA/ms 0.790 0.85 0.910
TJ = 25 C
TOP254PN/GN
di/dt = 105 mA/ms 0.93 1.00 1.07
TJ = 25 C
TOP254MN
di/dt = 135 mA/ms 1.209 1.30 1.391
TJ = 25 C
TOP254YN/EN
di/dt = 270 mA/ms 1.209 1.30 1.391
TJ = 25 C
TOP255PN/GN
di/dt = 120 mA/ms 1.069 1.15 1.231
TJ = 25 C
TOP255MN
di/dt = 175 mA/ms 1.581 1.70 1.819
TJ = 25 C
TOP255LN
di/dt = 350 mA/ms 1.581 1.70 1.819
TJ = 25 C
Self Protection
TOP255YN/EN
Current Limit ILIMIT di/dt = 350 mA/ms 1.581 1.70 1.819 A
TJ = 25 C
(See Note C)
TOP256PN/GN
di/dt = 140 mA/ms 1.255 1.35 1.445
TJ = 25 C
TOP256MN
di/dt = 220 mA/ms 1.953 2.10 2.247
TJ = 25 C
TOP256LN
di/dt = 435 mA/ms 1.953 2.10 2.247
TJ = 25 C
TOP256YN/EN
di/dt = 530 mA/ms 2.371 2.55 2.729
TJ = 25 C
TOP257PN/GN
di/dt = 155 mA/ms 1.395 1.50 1.605
TJ = 25 C
TOP257MN
di/dt = 265 mA/ms 2.371 2.55 2.729
TJ = 25 C
TOP257LN
di/dt = 530 mA/ms 2.371 2.55 2.729
TJ = 25 C
TOP257YN/EN
di/dt = 705 mA/ms 3.162 3.40 3.638
TJ = 25 C
TOP258PN/GN
di/dt = 170 mA/ms 1.534 1.65 1.766
TJ = 25 C
TOP258MN
di/dt = 310 mA/ms 2.790 3.00 3.210
TJ = 25 C
TOP258LN
di/dt = 620 mA/ms 2.790 3.00 3.210
TJ = 25 C

35
www.powerint.com Rev. H 06/13
TOP252-262

Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 C Min Typ Max Units
(Unless Otherwise Specified)

Circuit Protection (cont.)


TOP258YN/EN di/dt = 890 mA/ms 3.999 4.30 4.601
TJ = 25 C
TOP259LN di/dt = 720 mA/ms 3.236 3.48 3.724
TJ = 25 C
TOP259YN/EN di/dt = 1065 mA/ms 4.790 5.15 5.511
TJ = 25 C
TOP260LN di/dt = 870 mA/ms 3.906 4.20 4.494
TJ = 25 C
Self Protection
TOP260YN/EN
Current Limit ILIMIT di/dt = 1240 mA/ms 5.580 6.00 6.420 A
TJ = 25 C
(See Note C)
TOP261LN di/dt = 1065 mA/ms 4.808 5.17 5.532
TJ = 25 C
TOP261YN/EN di/dt = 1530 mA/ms 6.882 7.40 7.918
TJ = 25 C
TOP262LN di/dt = 1065 mA/ms 4.808 5.17 5.532
TJ = 25 C
TOP262EN di/dt = 1530 mA/ms 6.882 7.40 7.918
TJ = 25 C
0.70
Initial Current Limit IINIT See Note B ILIMIT(MIN) A

TJ = 25 C, IX or IM - 165 mA 0.9 I2f I2f 1.2 I2f


Power Coefficient PCOEFF A2kHz
See Note D IX or IM - 117 mA 0.9 I2f I2f 1.2 I2f
Leading Edge
tLEB TJ = 25 C, See Figure 53 220 ns
Blanking Time
Current Limit Delay tIL(D) 100 ns
Thermal Shutdown
135 142 150 C
Temperature
Thermal Shutdown
75 C
Hysteresis
Power-Up Reset
VC(RESET) Figure 54 (S1 Open Condition) 1.75 3.0 4.25 V
Threshold Voltage
Output
TOP252 TJ = 25 C 19.1 22.00
ID = 50 mA TJ = 100 C 28.8 33.40
TOP253 TJ = 25 C 8.8 10.10
ID = 100 mA TJ = 100 C 13.1 15.20
TOP254 TJ = 25 C 5.4 6.25
ID = 150 mA TJ = 100 C 8.35 9.70
ON-State TOP255 TJ = 25 C 4.1 4.70
RDS(ON) W
Resistance ID = 200 mA TJ = 100 C 6.3 7.30
TOP256 TJ = 25 C 2.8 3.20
ID = 300 mA TJ = 100 C 4.1 4.75
TOP257 TJ = 25 C 2.0 2.30
ID = 400 mA TJ = 100 C 3.1 3.60
TOP258 TJ = 25 C 1.7 1.95
ID = 500 mA TJ = 100 C 2.5 2.90

36
Rev. H 06/13 www.powerint.com
TOP252-262

Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 C Min Typ Max Units
(Unless Otherwise Specified)

Output (cont.)
TOP259 TJ = 25 C 1.45 1.70
ID = 600 mA TJ = 100 C 2.25 2.60
TOP260 TJ = 25 C 1.20 1.40
ON-State ID = 700 mA TJ = 100 C 1.80 2.10
RDS(ON) W
Resistance TOP261 TJ = 25 C 1.05 1.20
ID = 800 mA TJ = 100 C 1.55 1.80
TOP262 TJ = 25 C 0.90 1.05
ID = 900 mA TJ = 100 C 1.35 1.55
TJ 85 C, See Note E 18
DRAIN Supply Voltage V
36
OFF-State Drain VV, VM = Floating, IC = 4 mA,
IDSS 470 mA
Leakage Current VDS = 560 V, TJ = 125 C
VV, VM = Floating, IC = 4 mA,
Breakdown
BVDSS TJ = 25 C 700 V
Voltage
See Note F

Rise Time tR Measured in a Typical Flyback 100 ns

Fall Time tF Converter Application 50 ns


Supply Voltage Characteristics
TOP252-255 0.6 1.2 2.0
66 kHz
Output TOP256-258 0.9 1.4 2.3
Operation
MOSFET TOP259-262 1.1 1.6 2.5
ICD1 Enabled
Control Supply/ VX, VV, VM = TOP252-255 0.8 1.3 2.2
132 kHz mA
Discharge Current 0V TOP256-258 1.1 1.6 2.5
Operation
TOP259-262 1.5 2.2 2.9
Output MOSFET Disabled
ICD2 0.3 0.6 1.3
VX, VV, VM = 0 V
NOTES:
A. For specifications with negative values, a negative temperature coefficient corresponds to an increase in magnitude with increas-
ing temperature, and a positive temperature coefficient corresponds to a decrease in magnitude with increasing temperature.

B. Guaranteed by characterization. Not tested in production.

C. For externally adjusted current limit values, please refer to Figures 55a and 55b (Current Limit vs. External Current Limit Resis-
tance) in the Typical Performance Characteristics section. The tolerance specified is only valid at full current limit.

D. I2f calculation is based on typical values of ILIMIT and fOSC, i.e. ILIMIT(TYP)2 fOSC, where fOSC = 66 kHz or 132 kHz depending on package
/ F pin connection. See fOSC specification for detail.

E. The TOPSwitch-HX will start up at 18 VDC drain voltage. The capacitance of electrolytic capacitors drops significantly at tempera-
tures below 0 C. For reliable start up at 18 V in sub zero temperatures, designers must ensure that circuit capacitors meet
recommended capacitance values.

F. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up to but not
exceeding minimum BVDSS.

37
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TOP252-262

t2
t1
HV
90% 90%

DRAIN t1
D=
VOLTAGE t2

10%
0V

PI-2039-033001

Figure 51. Duty Cycle Measurement.

PI-4758-061407
tLEB (Blanking Time)
120 1.3
PI-4737-061207
1.2

DRAIN Current (normalized)


CONTROL Pin Current (mA)

100 1.1
1.0
80 0.9
0.8
0.7 IINIT(MIN)
60
0.6
0.5
40 0.4
Dynamic 1
= 0.3
Impedance Slope
20 0.2
0.1
0 0
5 6 7 8 9 0 1 2 3 4 5 6 7 8
CONTROL Pin Voltage (V) Time (s)
Figure 52. CONTROL Pin I-V Characteristic. Figure 53. Drain Current Operating Envelope.

P or G Package (M Pin)

TOP254-258 Y, all E, L or M Packages (X and V Pins) 0-300 k

S1 470 S5
5W 0-300 k
5-50 V M
0-60 k
5-50 V

40 V TOPSwitch-HX
V D
TOP259-261 Y (X and V Pins)
470 CONTROL
C C 0-300 k
S2
F X S D
S4
0-15 V CONTROL
S3 5-50 V C
47 F 0.1 F
0-60 k
G X S

NOTES: 1. This test circuit is not applicable for current limit or output characteristic measurements.
2. For P, G and M packages, short all SOURCE pins together.

PI-4738-071408

Figure 54. TOPSwitch-HX General Test Circuit.

38
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TOP252-262

Typical Performance Characteristics

PI-4754-120307
1.1 1.1

1 1
Maximum
0.9 0.9
Normalized Current Limit

0.8 0.8

Normalized di/dt
0.7 0.7
Typical

0.6 0.6

0.5 0.5
Minimum
0.4 0.4

0.3 0.3
Notes:
1. Maximum and Minimum levels are
0.2 based on characterization. 0.2
O O
2. T J = 0 C to 125 C.
0.1 0.1

0 0
-200 -150 -100 -50 0
IX or IM ( A )

Figure 55a. Normalized Current Limit vs. X or M Pin Current.

PI-4755-120307
1.1 1.1
Notes:
1 1. Maximum and Minimum levels are 1
based on characterization.
0.9 2. T J = 0 OC to 125 OC. 0.9
3. Includes the variation of X or M pin
0.8 voltage. 0.8
Maximum
Normalized Current Limit

0.7 0.7

Normalized di/dt
0.6 Typical
0.6

0.5 0.5

0.4 0.4

0.3 0.3

0.2 0.2
Minimum
0.1 0.1

0 0
0 5 10 15 20 25 30 35 40 45
RIL ( k )

Figure 55b. Normalized Current Limit vs. External Current Limit Resistance.

39
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TOP252-262

Typical Performance Characteristics (cont.)

1.1 1.2

PI-4759-061407
PI-176B-033001
1.0

(Normalized to 25 C)
(Normalized to 25 C)

Output Frequency
Breakdown Voltage

0.8

1.0 0.6

0.4

0.2

0.9 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (C) Junction Temperature (C)
Figure 56. Breakdown Voltage vs. Temperature. Figure 57. Frequency vs. Temperature.

1.2 1.2
PI-4760-061407

PI-4739-061507
1.0 1.0
(Normalized to 25 C)
(Normalized to 25 C)

0.8
Current Limit

0.8
Current Limit

0.6 0.6

0.4 0.4

0.2 0.2

0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150

Junction Temperature (C) Junction Temperature (C)


Figure 58. Internal Current Limit vs. Temperature. Figure 59. External Current Limit vs. Temperature with RIL = 10.5 kW.

1.2 1.2
PI-4762-061407
PI-4761-061407

Under-Voltage Threshold

1.0 1.0
Overvoltage Threshold

(Normalized to 25 C)
(Normalized to 25 C)

0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (C) Junction Temperature (C)
Figure 60. Overvoltage Threshold vs. Temperature. Figure 61. Undervoltage Threshold vs. Temperature.

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TOP252-262

Typical Performance Characteristics (cont.)


VOLTAGE MONITOR Pin Voltage (V)
6 1.6

PI-4740-060607

PI-4741-110907
VX = 1.354 - 1147.5 IX + 1.759 106
5.5

EXTERNAL CURRENT LIMIT


1.4 (IX)2 with -180 A < IX < -25 A

5 1.2

Pin Voltage (V)


4.5 1.0

4 0.8

3.5 0.6

3 0.4

2.5 0.2

2 0
0 100 200 300 400 500 -200 -150 -100 -50 0
VOLTAGE-MONITOR Pin Current (A) EXTERNAL CURRENT LIMIT Pin Current (A)
Figure 62a. VOLTAGE-MONITOR Pin vs. Current. Figure 62b. EXTERNAL CURRENT LIMIT Pin Voltage vs. Current.

6 1.6
PI-4742-021308
MULTI-FUNCTION Pin Voltage (V)

PI-4743-061407
MULTI-FUNCTION Pin Voltage (V)
VM = 1.354 - 1147.5 IM + 1.759 106
1.4 (IM)2 with -180 A < IM < -25 A
5
1.2
4
1.0
3 0.8

2 0.6

See expanded 0.4


1 version
(Figure 63b) 0.2

0 0
-200 -100 0 100 200 300 400 500 -200 -150 -100 -50 0
MULTI-FUNCTION Pin Current (A) MULTI-FUNCTION Pin Current (A)
Figure 63a. MULTI-FUNCTION Pin Voltage vs. Current. Figure 63b. MULTI-FUNCTION Pin Voltage vs. Current (Expanded).

1.2 1.2
PI-4764-061407
PI-4763-072208

Onset Threshold Current

1.0 1.0
(Normalized to 25 C)
(Normalized to 25 C)
CONTROL Current

0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (C) Junction Temperature (C)
Figure 64. Control Current Out at 0% Duty Cycle vs. Temperature. Figure 65. Maximum Duty Cycle Reduction Onset Threshold
Current vs. Temperature.

41
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TOP252-262

Typical Performance Characteristics (cont.)

5 1

PI-4748-071708

PI-4744-072208
VC = 5 V

CONTROL Pin Current (mA)


0.5
4
DRAIN Current (A)

0
3 Scaling Factors:
TOP262 1.82 -0.5
TOP261 1.62
TOP260 1.42
2 TOP259 1,17 -1
TOP258 1.00
TOP257 0.85
TOP256 0.61 -1.5
1 TOP255 0.42
TOP254 0.32 -2
TCASE = 25 C
TOP253 0.20
TCASE = 100 C TOP252 0.10
0 -2.5
0 2 4 6 8 10 12 14 16 18 20 0 20 40 60 80 100
Drain Voltage (V) Drain Pin Voltage (V)
Figure 66. Output Characteristics. Figure 67. IC vs. DRAIN Voltage.

10000 500
PI-4749-071708

PI-4750-071708
Scaling Factors: Scaling Factors:
TOP262 1.82 TOP262 1.82
TOP261 1.62
DRAIN Capacitance (pF)

TOP261 1.62 400


TOP260 1.42 TOP260 1.42
TOP259 1.17 TOP259 1.17 132 kHz
1000 TOP258 1.00
Power (mW)

TOP258 1.00
TOP257 0.85 300 TOP257 0.85
TOP256 0.61 TOP256 0.61
TOP255 0.42 TOP255 0.42
TOP254 0.32 TOP254 0.32
200 TOP253 0.20
100 TOP253 0.20
TOP252 0.10 TOP252 0.10
66 kHz
100

10 0
0 100 200 300 400 500 600 0 100 200 300 400 500 600 700
Drain Pin Voltage (V) Drain Pin Voltage (V)
Figure 68. COSS vs. DRAIN Voltage. Figure 69. DRAIN Capacitance Power.

1.2
Remote OFF DRAIN Supply Current

PI-4745-061407

1.0
(Normalized to 25 C)

0.8

0.6

0.4

0.2

0
-50 -25 0 25 50 75 100 125 150
Junction Temperature (C)
Figure 70. Remote OFF DRAIN Supply Current vs. Temperature.

42
Rev. H 06/13 www.powerint.com
TOP252-262

TO-220-7C (Y Package)

.165 (4.19)
.185 (4.70)
.390 (9.91) .045 (1.14)
.146 (3.71) .420 (10.67) .055 (1.40)
.156 (3.96)
.108 (2.74) REF
+ .234 (5.94)
.261 (6.63)

.461 (11.71) .570 (14.48)


.495 (12.57) REF.
7 TYP. .670 (17.02)
.860 (21.84) REF.
.880 (22.35)
.080 (2.03)
.120 (3.05)

.068 (1.73) MIN PIN 1 & 7 PIN 2 & 4

PIN 1 .024 (.61) .040 (1.02)


.010 (.25) M
.034 (.86) .060 (1.52)
.050 (1.27) BSC .012 (.30) .040 (1.02)
.024 (.61) .060 (1.52)
.150 (3.81) BSC
.190 (4.83)
.210 (5.33)

.050 (1.27)
.050 (1.27) Notes:
1. Controlling dimensions are inches. Millimeter
dimensions are shown in parentheses.
.050 (1.27) 2. Pin numbers start with Pin 1, and continue from left
to right when viewed from the front.
.050 (1.27) 3. Dimensions do not include mold flash or other
protrusions. Mold flash or protrusions shall not
exceed .006 (.15 mm) on any side.
.200 (5.08) .180 (4.58) 4. Minimum metal to metal spacing at the package
body for omitted pin locations is .068 in. (1.73 mm).
.100 (2.54)
5. Position of terminals to be measured at a location
PIN 1 PIN 7 .25 (6.35) below the package body.
6. All terminals are solder plated.
.150 (3.81) .150 (3.81)

Y07C MOUNTING HOLE PATTERN

PI-2644-040110

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TOP252-262

PDIP-8C (P Package)
D S .004 (.10) Notes:
-E- 1. Package dimensions conform to JEDEC specification
MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP)
package with .300 inch row spacing.
2. Controlling dimensions are inches. Millimeter sizes are
shown in parentheses.
3. Dimensions shown do not include mold flash or other
.240 (6.10) protrusions. Mold flash or protrusions shall not exceed
.260 (6.60) .006 (.15) on any side.
4. Pin locations start with Pin 1, and continue counter-clock-
wise to Pin 8 when viewed from the top. The notch and/or
dimple are aids in locating Pin 1. Pin 3 is omitted.
5. Minimum metal to metal spacing at the package body for
Pin 1 the omitted lead location is .137 inch (3.48 mm).
6. Lead width measured at package body.
.367 (9.32) 7. Lead spacing measured with the leads constrained to be
-D-
.387 (9.83) perpendicular to plane T.
.057 (1.45)
.068 (1.73)
(NOTE 6)
.125 (3.18) .015 (.38)
.145 (3.68) MINIMUM

-T-
SEATING .008 (.20)
PLANE .120 (3.05) .015 (.38)
.140 (3.56)

.300 (7.62) BSC


.100 (2.54) BSC .048 (1.22) .137 (3.48) (NOTE 7)
.014 (.36)
.053 (1.35) MINIMUM .300 (7.62) P08C
.022 (.56) T E D S .010 (.25) M .390 (9.91) PI-3933-040110

SDIP-10C (M Package)
Notes:
10 6
-E- 1. Package dimensions conform to JEDEC specification MS-019.
2. Controlling dimensions are inches. Millimeter sizes are shown
in parentheses.
3. Dimensions shown do not include mold flash or other protrusions.
Mold flash or protrusions shall not exceed .006 (.15) on any side.
4. D, E and F are reference datums.
.240 (6.10) 5. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
.260 (6.60)

1 5

.367 (9.32) -D- .300 (7.62)


.387 (9.83) .340 (8.64

.125 (3.18)
.200 (5.08) Max
.145 (3.68)

-F-
SEATING .008 (.20)
PLANE
.120 (3.05) .015 (.38)
.020 (.51) Min
.140 (3.56)

.070 (1.78) BSC .300 BSC


.014 (.36)
.030 (.76) .022 (.56)
.010 (.25) M FDE .300 (7.62) P10C
.040 (1.02) .390 (9.91) PI-4648-101507

44
Rev. H 06/13 www.powerint.com
TOP252-262

SMD-8C (G Package)
Notes:
D S .004 (.10) .046 .060 .060 .046 1. Controlling dimensions are
inches. Millimeter sizes are
-E- shown in parentheses.
.080 2. Dimensions shown do not
include mold flash or other
protrusions. Mold flash or
.086 protrusions shall not exceed
.186 .006 (.15) on any side.
.372 (9.45) 3. Pin locations start with Pin 1,
.240 (6.10)
.388 (9.86) .286 .420 and continue counter-clock-
.260 (6.60)
E S .010 (.25) wise to Pin 8 when viewed
from the top. Pin 3 is omitted.
4. Minimum metal to metal
spacing at the package body
for the omitted lead location
is .137 inch (3.48 mm).
Pin 1 Pin 1 5. Lead width measured at
.137 (3.48) package body.
MINIMUM Solder Pad Dimensions 6. D and E are referenced
.100 (2.54) (BSC) datums on the package
body.
.367 (9.32)
-D-
.387 (9.83)
.057 (1.45)
.125 (3.18) .068 (1.73)
.145 (3.68) (NOTE 5)

.004 (.10)
.032 (.81) .048 (1.22)
.053 (1.35)
.009 (.23) .004 (.10) .036 (0.91) 0 - 8
.037 (.94)
.012 (.30) .044 (1.12) G08C
PI-4015-101507

45
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TOP252-262

eSIP-7C (E Package)

C
2
0.403 (10.24) 0.081 (2.06) 0.264 (6.70)
A
0.397 (10.08) 0.077 (1.96) Ref.
B

Detail A
2
0.325 (8.25) 0.290 (7.37)
Ref. 0.198 (5.04) Ref.
0.320 (8.13)
0.519 (13.18)
Ref.

Pin #1 0.016 (0.41) 0.207 (5.26)


0.140 (3.56)
I.D. Ref. 0.187 (4.75)
0.120 (3.05)

0.070 (1.78) Ref. 0.047 (1.19) 3 4


0.033 (0.84) 6
0.050 (1.27) 0.100 (2.54)
3 0.016 (0.41) 6 0.028 (0.71)
0.011 (0.28) 0.118 (3.00)
0.010 M 0.25 M C A B
0.020 M 0.51 M C
FRONT VIEW SIDE VIEW BACK VIEW

10 Ref. 0.100 (2.54)


All Around

0.021 (0.53) 0.060 (1.52) 0.020 (0.50) 0.050 (1.27)


0.019 (0.48) Ref. 0.050 (1.27)
PIN 1

0.048 (1.22) 0.059 (1.50) 0.155 (3.93)


0.378 (9.60) 0.046 (1.17)
Ref. 0.019 (0.48) Ref.
0.023 (0.58)
PIN 7
END VIEW
0.027 (0.70)
0.059 (1.50)
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994. DETAIL A
2. Dimensions noted are determined at the outermost 0.100 (2.54) 0.100 (2.54)
extremes of the plastic body exclusive of mold flash,
tie bar burrs, gate burrs, and interlead flash, but including MOUNTING HOLE PATTERN
any mismatch between the top and bottom of the plastic (not to scale)
body. Maximum mold protrusion is 0.007 [0.18] per side.
3. Dimensions noted are inclusive of plating thickness.
4. Does not include inter-lead flash or protrusions.
5. Controlling dimensions in inches (mm).

PI-4917-061510

46
Rev. H 06/13 www.powerint.com
TOP252-262

eSIP-7F (L Package)

2 C

0.403 (10.24) 0.081 (2.06)


A
0.397 (10.08) 0.264 (6.70) Ref.
0.077 (1.96)
B

Detail A

0.325 (8.25) 0.290 (7.37)


2 0.198 (5.04) Ref.
0.320 (8.13) 3 Ref. 0.490 (12.45) Ref.
0.016 (0.41) 6
0.011 (0.28)
0.020 M 0.51 M C 0.173 (4.40)
1 7 0.163 (4.15) 7 1
0.084 (2.14)
Pin 1 I.D.
0.089 (2.26)
0.047 (1.19) Ref. 0.079 (2.01)
0.070 (1.78) Ref.
0.050 (1.27) 0.100 (2.54) 3 4
0.129 (3.28) 0.033 (0.84) 6
0.122 (3.08) 0.028 (0.71)
0.010 M 0.25 M C A B

BOTTOM VIEW SIDE VIEW TOP VIEW

Exposed pad hidden Exposed pad up

Notes:
0.021 (0.53) 1. Dimensioning and tolerancing per ASME
0.060 (1.52) Ref.
1 7 0.020 (0.50)
0.019 (0.48) Y14.5M-1994.
2. Dimensions noted are determined at the
outermost extremes of the plastic body
exclusive of mold flash, tie bar burrs, gate
burrs, and interlead flash, but including
0.019 (0.48) Ref. 0.023 (0.58) any mismatch between the top and bottom
0.378 (9.60) 0.048 (1.22) of the plastic body. Maximum mold
Ref. 0.046 (1.17) 0.027 (0.70) protrusion is 0.007 [0.18] per side.
3. Dimensions noted are inclusive of plating
thickness.
END VIEW DETAIL A (Not drawn to scale) 4. Does not include inter-lead flash or
protrusions.
5. Controlling dimensions in inches (mm).

PI-5204-061510

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TOP252-262

Part Ordering Information


TOPSwitch Product Family
HX Series Number
Package Identifier
P Plastic DIP-8C
G Plastic SMD-8C
M Plastic SDIP-10C
Y Plastic TO-220-7C
E Plastic eSIP-7C
L Plastic eSIP-7F
Pin Finish
N Pure Matte Tin (Pb-Free) (P, G, M, E, L and Y Packages)
G Green Mold Compound (Specific E Packages Only)
Tape & Reel and Other Options
Blank Standard Configurations
TOP 258 G N - TL TL G Package (1000 min/mult.)

48
Rev. H 06/13 www.powerint.com
TOP252-262

Revision Notes Date


B Data sheet release. 02/08
C Added L package and TOP262. 07/08
D Changed eSIP-7E to eSIP-7F. Added detail to PI-4917 and PI-5204. 08/08
E Released TOP255-259LN and TOP262EN parts. 10/08
F Added note for TOP256E halogen free part availability. 01/09
Added note for TOP258P and TOP259E halogen free part availability. Updated E & L bend package drawings. Minor text
G 01/10
changes to page 27.
H Added EG parts. Removed Note 7 from Table 1 on page 2. 06/13

49
www.powerint.com Rev. H 06/13
For the latest updates, visit our website: www.powerint.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power
Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES
NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.

Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered
by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A
complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under
certain patent rights as set forth at http://www.powerint.com/ip.htm.

Life Support Policy


POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:

1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii)
whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant
injury or death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or effectiveness.

The PI logo, TOPSwitch, TinySwitch, LinkSwitch, LYTSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS, HiperTFS,
HiperLCS, Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc.
Other trademarks are property of their respective companies. 2013, Power Integrations, Inc.

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Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Power Integrations:
TOP254GN-TL TOP254MN TOP254PN TOP254YN TOP255GN-TL TOP255MN TOP255PN TOP255YN
TOP256GN-TL TOP256MN TOP256PN TOP256YN TOP257GN-TL TOP257MN TOP257PN TOP257YN
TOP258GN-TL TOP258MN TOP258PN TOP258YN TOP254GN TOP255GN TOP256GN TOP257GN TOP258GN
TOP253EN TOP255EN TOP261YN TOP258EN TOP259EN TOP257EN TOP253MN TOP260EN TOP254EN
TOP256EN TOP252MN TOP252PN TOP260YN TOP259YN TOP252EN TOP252GN-TL TOP253PN TOP261EN
TOP253GN-TL TOP255LN TOP256EG TOP256LN TOP257LN TOP258LN TOP259LN TOP262EN TOP252GN
TOP253GN TOP260LN TOP261LN TOP262LN TOP252PG TOP252MG TOP252EG TOP253PG TOP253MG
TOP253EG TOP254PG TOP254MG TOP254EG TOP255PG TOP255MG TOP255EG TOP255LG TOP256PG
TOP256MG TOP256LG TOP257PG TOP257MG TOP257EG TOP257LG TOP258PG TOP258MG TOP258EG
TOP258LG TOP259EG TOP259LG TOP260EG TOP260LG TOP261EG TOP261LG