Mechatronics Test Equipment (I)

Pvt. Ltd., Pune

IMPLEMENTING IDEAS

Supreme Scientific Corporation

Madurai
WE VENTURE VLSI
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CHAPTER 1

Study of Simulation Tools

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 During HDL simulation, the simulator
software verifies the functionality and
timing of your design or portion of your
design.
The simulator interprets VHDL or Verilog
code into circuit functionality and displays
logical results of the described HDL to
determine correct circuit operation.
Simulation allows you to create and verify
complex functions in a relatively small
amount of time.
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 Start the Xilinx ISE by using start
Program files Xilinx ISE (9.1i) project navigator

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 SUPREME SCIENTIFIC
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File New Project

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Enter the Project Name and location then click next

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Select the Device and other category and click next twice and finish

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Click on the symbol of FPGA device and then
right click click on new source

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Select the Verilog Module and give the file name click next and
define ports

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In this case A and B are the input ports and SUM and C_OUT are output
ports. If you have more then 1-bit just click bus and set the MSB,LSB
value click next and finish.

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Writing the behavioural Verilog Code in Verilog Editor. Sample code is
given below for this experiment (FULL ADDER)

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 Check Syntax
Run the Check syntax Process window synthesize double click
check syntax > and remove errors, if present, with proper syntax & coding.

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Click on the symbol of FPGA device and then
right click click on new source

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Select the Test Bench Waveform and give the file name select entity
click next and finish

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Select the desired parameters for simulating your design. In this case
combinational circuit and simulation time click finish

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Assign all input signal using just click on this and save file.

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From the source process window. Click Behavioral simulation from
drop-down menu

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Select the test bench file (.tbw)and click process button double click
the Simulation Behavioral Model

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Verify your design in wave window by seeing behavior of output signal
with respect to input signal.

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EXPERIMENTAL RESULTS USING SIMULATION
TOOLS CAN BE INFERRED FOR:
1) FUNCTIONAL SIMULATION
2) GATE-LEVEL SIMULATION
3) POST-PAR SIMULATION
ON ISE SIMULATOR

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