:

INTERRUPTS

Introduction

The word interrupt has its very literal meaning as used in our everyday life. For e.g., you are
sitting at your table and reading a book, and suddenly the phone rings.So, you leave your table in
order to attend the call.However just before you do so you earmark the page you have
reached. On the phone now ,suppose somebody requests you to leave some important message
with one of your neighbours.So, once you replace the telephone receiver back on the hook,you
move out to your neighbour's place;give him the message and come back to your table. You take
your book anewitum to the earmarked page and continue the reading.

The up interrupt functions exactly in the same way. A program is being executed, similar to your
sitting and reading a book. An interrupt is then applied to the up(the phone rings).The latter /
acknowledges the receipt of that interrupt (you pick up the phone) and then moves to the memory
location as directed by the interrupt. This is very similar to the situation you are confronted with
in the above example, i.e you have to leave a message with a particular neighbour; and in your
mind you know exactly where that particular neighbour resides. Hence you go there to leave the
message.

In the case of the up however, that address should be specified at the time of interrupt. This is
done using a (RST) instruction , i.e Restart. The latter directs the up to the address where it
should restart its operation. This address is known as the"interrupt address vector",and it denotes
the address at which the sendee routine starts. A service routine is a subroutine to which the up
"Jumps" when it receives an interrupt request. The word "sendee" is used to imply that the up
sendees the interrupt by executing the subroutine.

Now, when the jap is interrupted, before it goes to the service routine, it automatically saves the
content of the program counter on the stack, so that the up can return to the main program after
executing the service routine, this is similar to earmarking the page you reached on receiving the
call, so that you may proceed with your reading after coming back.

The 8085 interrupt architecture.

The 8085 up has got 5 interrupt inputs, namely pin 6, 7, 8, 9 and 10. These interrupts are
identified by the names ; TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR respectively. The fact that
we have more than one interrupt pins on the up chip means that we should have a special
mechanism in order to handle the interrupts from several devices that share these interrupt lines;
especially when 2 or more interrupts are activated at the same instant.

This is done by assigning priorities to these interrupt lines at the very time of designing the up
chip. For the 8085, TRAP has the highest priority. So, if two or more of these interrupts are
activated simultaneously, the one with the higher priority is sendced first and then the other
interrupt is serviced; if it is still pending.
Maskable and Unmaskable Interrupt.

Besides having the highest priority, the TRAP is also known to be a non-maskable interrupt. RST
7.5, RST 6.5, and RST 5.5 are maskable interrupt; While INTR is neither of these. The term
maskable means that the user can enable or disable these interrupts using software. So. when the
interrupt is disabled we say that it has been masked. Then even if the interrupt pin is activated,
the jap will not respond. Just compare this with the e.g. we considered in the previous section. If
we place the receiver of the phone on-hook, it means that we are enabling a call to come; but if
the receiver is off-hook, even if somebody wants to phone you, you ' re not going to be
interrupted;and hence you wont even know if somebody wants to talk to you. As if you have
masked the call.

The same applies to the up. However, the TRAP is unmaskable, and hence the user has no control
over this interrupt. TRAP is always enabled. For e.g. on the VMC 85/12 kit the TRAP line is
connected to the RESET key. Hence, the user has no control over this interrupt.

Trap is always enabled. For e.g. on the VMC 85/12 kit the trap line is connected to the RESET
key. Hence, once the RESET key is pressed, the system will always be interrupted irrespective of
what the up is doing. This is an indication of the highest priority and unmaskable nature of
TRAP.

Different Interrupt Activities,

(i) INTR.

The 8085 requires some initializations prior to its identifying an interrupt request and servicing
that interrupt. First, in the main program, we should initialize the stack pointer to some address
found in the user RAM area. Then we should enable the interrupt process by executing the El
(Enable Interrupt) command; and after-wards we can write the procedure we wish to- accomplish
by our main program.

Now, in order to send an interrupt to the up, we should send a +5 v (Logic T ) to the TNTR (pin
TO) of the up,. As soon as the jap senses this signal, it completes the execution of the current
instruction, saves the content of pc on the stack, Disables the interrupt and acknowledges the
interrupt by sending a logic '0' on the INTA (pin 11) line. This signal is then used to latch the
restart address on the data bus of the jap. The restart address (or Interrupt address vector) contains
the beginning of the subroutine service, that should be executed. After completing this routine,
the up returns back to the main program.

If a further +5v signal is sent to the INTR pin, the same sequence of events should occur, i.e the
up is prepared to accept more interrupts.

(ii) RST 7.5, 6.5,5.5

These interrupts should be enabled using the El and SIM instruction. SIM means Set Interrupt
Mask. This instruction reads the content of the accumulator and enables or disables the interrupts
according to the content of the accumulator.
 7 6 5 4 3 2 1 0

X R7.5 MSE 7.5 6.5 5.5

RST 7.5 maski

6.5 mask
0 = enabled
1 = masked
5.5 mask_

Set = bits '9 nored

accepted

1 = RST 7.5 is reset*

0 = Don't care

*This is an additional control on RST 7.5 ie it can be reset during a program.

After the initialization stage, the system is ready to accept any or a combination of these
interrupts. Furthermore, the interrupt address vector in this case is specified by the in-built
software of the system. '*.

RST Vector Location

7.5 003C
6.5 0034
5.5 002C

Note: The user does not have access to the trap and RST 5.5 on the VMC 85/12 kit.

Interrupting the 8085 uP using the INTR line :

The 8085 has five interrupts lines, TRAP being the highest priority interrupt and INTR being the
lowest one. When the up is interrupted via the INTR line, the Interrupt Vector Address can be
any one of the following :-

OOOOH, 0008H, 0010H, 0018H, 0020H, 0028H, 0030H, 0038H

Selection of any one of these locations is done by some hardware arrangements. However, on the
VMC 85/12 kit, only the locations 0010H, 0020H, 0030H and 0038H are user-accessible.
Furthermore, if you consult the memory-map for the VMC 85/12 kit, you will see that these user-
accessible vector locations are all found in the ROM area; which means that we cannot write at
these locations.
All the more so, the instructions found on these ROM locations are as follows :-

0010 JMP 27AE

0020 JMP 27B1
0030 JMP 27B4
0038 JMP 27BA
Note that the locations to which all the above instructions are branching are found in the user
RAM area; so that the user can write his service routine at these locations. Unfortunately, another
problem still exists. The user is allowed to write a program which uses only three bytes of
memory space at the above-mentioned locations (i.e. 27AE. 27B1. 27B4, 27BA); else the
program will be overlapping on the memory locations reserved for the other interrupt vectors.
This should be apparent from above.

However, in practice a service routine takes much more than three bytes, and hence the trick is to
write the service routine at some other address locations (say starting at 2200H), and then to
include a 'JUMP' instruction at the locations reserved by the interrupt vector. For e.g. if we wish
to use the resented vector location 003 8H, we can start our service routine at address 2200H.
Then, we go to address 27BA (reserved for vector location 0038H) and write the instruction

27BA JMP 2200 ; which is a 3- bytes instruction.

In this way, the overlapping problem is avoided and the interrupt will function as required.

So, let us recapitulate:-

When the EMTR line goes high, the up terminates the current instruction, saves current
contents of the Program Counter on the stack, and activates the INTA line to logic '0'.
. " 'The external hardware, latches the code for the appropriate vector location on the data bus.
The address of the selected vector location is loaded in the Program Counter. For the
example considered, the value 0038H is loaded in the PC.
Control is then transferred to location 0038H, where we have the resident instruction "JMP
27BA".
The up executes the latter instruction and thereby transfers control to address 27BAH, where
the user should write the instruction "IMP 2200".
Thus control is now transferred to address 2200H, which is the starting address of the service
routine. The jap then executes the instructions that have been written for the service routine.
After execution of the service routine, control should be returned back to the main program.

The service routine

Quite a lot has been said about the main program and the interrupt process. We shall now
describe the format that the service routine should follow.

You should recall that a service routine is called for every time that particular service is requested
for, by a peripheral. On completion of the service, the initial condition of the up (i.e. prior to the
incoming of the interrupt) should be restored. It is the responsibility of the programmer to ensure
that this is done in the proper way, so that the up can resume its main task. Thus, the service
routines must be written in such a way that they fulfill this requirement. The procedure to be
adopted so as to act accordingly is>

(i) At the very beginning of the routine, save the contents of all the important registers on the
stack. This is done using the "PUSH" instruction. The term "important register" is used to
imply the registers whose contents would be modified by the execution of the service
routine.
 In fact, it is a good programming practice to save the contents of all registers (i.e. A,
B, C, D,'E, H, L), since it is quite difficult at times to pinpoint, before hand, which are the
registers that would be affected by a service routine.

(ii) Write the program required to fulfill the desired service.

(iii) Restore back the contents of all the registers. This is done using the TOP" instruction. It is
very important to note that the "PUSH" and "POP" operation-pair should be used in a LIFO (
Last In First Out) fashion.

e.g. PUSH A
PUSH B
PUSH C

POP C
POP B
POP A

(iv) Finally, the routine should be terminated by a "RET" instruction. This is very important so as
to return control back to the main program.

Interrupting the up using RST 7.5. RST 6.5. or RST 5.5 line

As it was pointed out earlier, the RST 5.5 is not user-accessible on the VMC 85/12 kit. The
discussion will thus be based around RST 7.5 and RST 6.5. Note that the structure of RST 7.5
and RST 6.5 is the same as that of TNTR.

Now, recall that the interrupt vector address for RST 7.5 and RST 6.5 are 003C and 0034
respectively. From the discussion of previous sections, these locations are found in the ROM
area and hence non-accessible. However, the instructions residing at these locations are as
follows:-
0034 JMP 27B7
003C JMP 27BD

Now, suppose that the service routine starts at address 2300H; we just write the instruction "
JMP 2300 " at address 27B7 or 27BD depending on the RST we want to use. Afterwards, on
activating the appropriate interrupt pin on the up, the corresponding service routine will be
executed.

Furthermore, in this case the service routine will have the same structure as the one discussed for
USTTR; except that, in addition, the appropriate interrupt should be enabled using the SIM
instruction code, as described previously.
 Input

Reset
RST 7.5 Interrupt Recognised

'Jl

I)!
Reset
Anv Intcrrunt Rixourii/ed

-The 8085 Interrupts and Vector Locations