11/2/2016

Digital Logic families

Digital Logic families
Book Referred:
Digital Design by M.Morris Mano
• The entire range of digital ICs is fabricated using either
bipolar devices or MOS devices or a combination of the
two.
• Different logic families falling in the first category are
called bipolar families, and these include
– diode logic (DL), resistor transistor logic (RTL), diode
transistor logic (DTL), transistor transistor logic (TTL),
emitter coupled logic (ECL), also known as current mode
logic (CML), and integrated injection logic (I2L).
• The logic families that use MOS devices as their basis
are known as MOS families, and the prominent
members belonging to this category are
– the PMOS family (using P-channel MOSFETs), the NMOS
family (using N-channel MOSFETs) and the CMOS family
(using both N- and P-channel devices).
• The Bi-MOS logic family uses both bipolar and MOS
devices.

A Comparison of Logic Families A Comparison of Logic Families

Parameter CMOS TTL ECL

Basic gate NAND/NOR NAND OR/NOR

Fan-out >50 10 25

Power per gate (mW) 1 @ 1 MHz 1 - 22 4 - 55

Noise immunity Excellent Very good Good

tPD (ns) 1 - 200 1.5 – 33 1-4

+5 V
BASICS AND Gate
AND Gate using Diodes R
A 3-input AND gate. When all inputs are at 0V
· extra inputs can be formed by adding extra diodes.
A
 all diodes are forward biased Output
+5 V
 current will flow through the resistor R Inputs B ABC

R C
if all diodes are identical
 current will be equally divided amongst all diodes.
A
Output
Inputs B ABC If all inputs are at 0V
 the output voltage must be +0.7V above the input voltage of 0 V i.e.
C
0.7 V
 due to positive logic  0.7V  L
Making a positive logic level assumption
0V  0 or L
+5V  1 or H

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+5 V

AND Gate AND Gate R

+5 V
If +5v is applied to all inputs A
Output
R  none of the diodes will conduct Inputs B ABC
 output voltage will be +5V  H
C
A
Output
Thus circuits behaves as an AND gate only when
Inputs B ABC
 all inputs are +5V (logic 1) will the output be +5V (logic 1).
C
Note
If one or more inputs are raised to +5 V • output voltage representing logic 0 is higher than the input logic 0
 causes those diodes to become reverse-biased. level by 0.7 V
 current will still flow through the remaining diode
 output will remain at 0.7 V, i.e. L. But
• voltage at a logic level 1 is 5 V for both input and output.

OR Gate using Diodes Bipolar Transistor Gate

All inputs at 0 V A
 output at 0 V
Output • Consider a bipolar transistor in logic circuits
If any input is at +5 V Inputs B A+B+C
 diode conducts  It is operated in either two states
 output = (input - 0.7 V) C  produces the two logic levels
= 4.3 VLogic 1 H
R
fully conducting state saturated/turned on
0V
 The fundamental Boolean operator, the Inverter or NOT
operator cannot be produced with diodes and resistors alone or

· As a diode has limited functionality in logic circuits

· The transistor plays a more important role fully non-conducting state cut-off state

Voltage Transfer Characteristic

Bipolar Transistor Gate • One of the principal properties of interest in any digital circuit is the
voltage-transfer characteristic.
• The simple but very practical logic inverter – relates the output voltage to the input voltage under steady-state or low frequency
conditions. V
Vcc = 5 V OUT
V BE(ON) =0.7V Active
Cutoff Saturation
V BE(SAT) =0.8V VOH 5.0
BP1
RC 1 k
V CE(SAT) =0.1V Vout 4.0

3.0
Vin RB
2.0

10 k
1.0

VOL BP2
1.0 2.0 3.0 4.0 5.0
VIN

VIL VIH

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• HIGH-level input voltage, VIH This is the minimum voltage level that
• HIGH-level output voltage, VOH. This is the minimum voltage on the
Characteristic Parameters
• LOW-level input voltage, VIL. This is the maximum voltage level
applied at the input that is recognized as a legal LOW level for the
specified family.
– For the standard TTL family, an input voltage of 0.8 V is a legal LOW logic
state.
• LOW-level output voltage, VOL. This is the maximum voltage on the
output pin of a logic function when the input conditions establish logic
LOW at the output for the specified family.
– In the case of the standard TTL family of devices, the LOW-level output
voltage can be as high as 0.4V and still be treated as a legal LOW logic
state.
Characteristic Parameters
• LOW-level output current, IOL. This is the maximum current
flowing into the output pin of a logic function when the input
conditions are such that the output is in the logic LOW state.
– It tells about the current sinking capability of the output.
– The magnitude of IOL determines the number of inputs the logic function can
drive when its output is in the logic LOW state.
• LOW-level input current, IIL. The LOW-level input current is the
maximum current flowing into (taken as positive) or out of (taken
as negative) the input of a logic function when the voltage
applied at the input equals the maximum LOW-level output
voltage specified for the family.
– In the case of bipolar logic families such as TTL, the circuit design is such
that this current flows out of the input pin and is therefore specified as
negative.
– In the case of CMOS logic families, it could be either positive or negative.
In this case, only an absolute value is specified.
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Characteristic Parameters
needs to be applied at the input to be recognized as a legal HIGH
level for the specified family.
– For the standard TTL family, a 2 V input voltage is a legal HIGH logic state.
output pin of a logic function when the input conditions establish
logic HIGH at the output for the specified family.
– In the case of the standard TTL family of devices, the HIGH level output voltage
can be as low as 2.4V and still be treated as a legal HIGH logic state.
Characteristic Parameters
• HIGH-level input current, IIH - This is the current flowing into (taken as
positive) or out of (taken as negative) an input when a HIGH-level input
voltage equal to the minimum HIGH-level output voltage specified for the
family is applied.
– In the case of bipolar logic families such as TTL, the circuit design is such
that this current flows into the input pin and is therefore specified as
positive.
– In the case of CMOS logic families, it could be either positive or negative,
and only an absolute value is specified in this case.
• HIGH-level output current, IOH. This is the maximum current flowing out of an
output when the input conditions are such that the output is in the logic HIGH
state. It is normally shown as a negative number.
– It tells about the current sourcing capability of the output.
– The magnitude of IOH determines the number of inputs the logic function
can drive when its output is in the logic HIGH state.
• For example, for the standard • For example, for the standard TTL
TTL family, the minimum family, the minimum guaranteed IOL is
guaranteed IOH is −400 A, which 16 mA, which can drive 10 standard
can drive 10 standard TTL
inputs with each requiring 40 TTL inputs with each requiring 1.6mA
A(IIH) in the HIGH state. in the LOW state.
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Characteristics Fan out

• The feature to be concerned of IC logic families:

– fan-out
• The no. of standard loads can be connected to the output of
the gate without degrading its normal operation
– Power dissipation
• The power needed by the gate
• It is the product of supply voltage VCC and supply current
ICC and expressed in mW.
– Propagation delay
• The average transition-delay time for the signal to propagate
from input to output when the binary signal changes in value • Fan out = IOH/IlH or IOL/IIL
– Noise margin • The fan-out of standard TTL is 10.
• This means that the output of a TTL gate can be
• The unwanted signals are referred to as noise connected to no more than 10 inputs of other gates
• Noise margin is the maximum noise added to an input signal in the same logic family.
of a digital circuit that does not cause an undesirable change • Otherwise. the gate may not be able to drive or sink
in the circuit output the amount of current needed from the inputs that
are connected to it.

Power dissipation Input Data to Clock Timing

• Setup time (tsu) – the time required for the
synchronous inputs of a flip-flop to be stable
before the clock active edge.
• Hold time (th) – the time that the synchronous
inputs of a flip-flop must remain stable after the
clock active edge.

Metrics Metrics
Logic Levels Positive Logic • Between the two levels the transistor is in the active
VIL maximum allowed voltage at input for a logic low level region,
VIH minimum allowed voltage at input for a logic high level – output level is not uniquely determined
– where because of the loose control on the transistor
VOH 5.0 V parameters.

HIGH NMH • Hence this is a forbidden region

V IH  V IL
LS
1.5 V VIH
• The difference between VIH and VIL is the Transition
TW Width.
• From diagram,
TW  V IH  V IL
0.7 V VIL
LOW NML VOL 0.1 V
VIH = 1.5 V
Input Output
VIL = 0.7 V  1 . 5  0 .7
VOH =5.0 V
VOL= 0.1 V  0 .8 V

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Metrics Propagation Delay

• Logic Swing is defined as the difference between the For in the inverter circuit the turn-on delay time tPHL is measured as the
output is changing from a high voltage level to a low voltage level.
two output voltage levels
LS  VOH  VOL 
tf
t PHL  t d 
 5 . 0  0 .1 2
4.2
 0.73   2.8 ns
 4 .9 V 2

For the turn-off delay time tPLH is measured as the output is changing
• Noise Margins from a low voltage level to a high voltage level.

NM H  VOH  V IH NM L  V IL  VOL tr
 t PLH  t s 
 5.0  1.5  0.7  0.1 2
 3.5 V  0.6 V 15
 24   31 ns
2

Propagation Delay TRANSISTOR-TRANSISTOR LOGIC

Thus the average propagation delay time is defined as:

t PHL  t PLH
tp 
2
2.8  31

2
 17 ns

TTL Gate with Totem-Pole Output

Types of TTL family
• Three different types of output configuration:
1. Totem-pole output
2. Open-collector output
3. Three-state output

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Table explaining the operation of the

TTL NAND gate circuit, assuming two
inputs, A and B
Open-collector TTL NAND Gate
The output stage does not have the active pull-up transistor. An
external pull-up resistor needs to be connected from the open
collector terminal of the pull-down transistor to the VCC terminal.
The pull-up resistor is typically 10 k.

A B I Q Q Q4 Q Y O/P
CQ1 1 2 3
0 0 + ON OFF OFF ON 1

0 1 + ON OFF OFF ON 1

1 0 + ON OFF OFF ON 1

1 1 － OFF ON ON OFF 0

• Low level- 0.2 V

• High level -2.4 to 5 V

Difference between Open-Collector TTL and Applications of open collector TTL gate
totem pole TTL 1. Wired-AND of Two Open-Collector
• Missing a transistor internally, so you must
provide an external pull-up resistor.
• The advantage of open collector outputs is that
the outputs of different gates can be wired
together, resulting in ANDing of their outputs.
• The outputs of totem-pole TTL devices cannot
be tied together. Although a common tied
output may end up producing an ANDing of
individual outputs, such a connection is
impractical.

2. Open-Collector Gates Forming a Common Bus Three-state TTL Gate

Line

In this case
Y=?

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Symbols for MOSFETs Using NMOS transistors

Various series of the CMOS Logic family

CMOS Complementary MOSFETs
CMOS Series Prefix Example

Original CMOS 40 4009

Pin compatible with TTL 74C 74H04
High-speed and pin compatible with TTL 74HC 74HC04
High-speed and electrically compatible with TTL 74HCT 74HCT04
Very High-speed and pin compatible with TTL 74VHC 74VHC04
Very High-speed and electrically compatible with TTL 74VHCT 74VHCT04
Advanced High-speed and pin compatible with TTL 74AHC 74AHC04
Advanced High-speed and electrically compatible with TTL 74AHCT 74AHCT04
Fast and electrically compatible with TTL 74FCT 74 FCT 04
Fast and electrically compatible with TTL with TTL VOH 74FCT-T 74 FCT04T

CMOS NAND Gates 2-input NOR gate

• Use 2n transistors for n-input gate A B Q1 Q2 Q3 Q4 Y

0 0 OFF ON OFF ON 1

0 1 OFF ON ON OFF 0

1 0 ON OFF OFF ON 0

1 1 ON OFF ON OFF 0

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BiCMOS Logic BiCMOS inverter

• The BiCMOS logic family integrates bipolar and
CMOS devices on a single chip with the objective
of deriving the advantages individually present in
bipolar and CMOS logic families.
• While bipolar logic families such as TTL and ECL
have the advantages of faster switching speed
and larger output drive current capability, CMOS
logic scores over bipolar counterparts when it
comes to lower power dissipation, higher noise
margin and larger packing density.

BiCMOS two-input NAND

• When the input is LOW, N-
channel MOSFETs Q2 and Q3
are OFF.
• P-channel MOSFET Q1 and N-
channel MOSFET Q4 are ON.
• This leads transistors Q5 and
Q6 to be in the ON and OFF
states respectively.
• Transistor Q6 is OFF because it
does not get the required
forward-biased base-emitter
voltage owing to a conducting
Q4.
• Conducting Q5 drives the
output to a HIGH state,
sourcing a large drive current
to the load.

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