Remote Image Processing

on FPGAs
Period: 1st July – Present
Name: Xinyuan Qian
Introduction
Introduce myself
- education background, research interest
Internship process
- what I have done in Heriot-Watt
Future Work
- things I need to do before finish the
internship
 Xinyuan Qian
• Nanjing University of Aeronautics and Astronautics, China
(2010 - 2012)
BEng in Information Engineering

• University of Edinburgh, Scotland (2012 - 2014)

BEng in Electronics and Electrical Engineering (First Class)

• University of Edinburgh, Scotland ( Start from Sept 2014)

Msc in Signal Processing and Communications
Research Interest
• Real-time Video Processing Publications:
• Embedded Systems

Practical applications:
BEng Project:
Real-time Video Processing on Raspberry Pi
£35

inp u t
ut t p
ou
Internship Content

Rathlin Project
– Remote Image Processing on FPGAs

Zedboard
- Fast response times
- Offers flexibility and rapid
prototyping capabilities
What I am trying to do

Dataflow VHDL FPGA

1. Compiling Dataflow to VHDL
Supported Software:
•Eclipse – LUNA (with Orcc installed)
- ‘Orcc’ is a compiler that compile ‘CAL’ (a dataflow
language) to other languages
•Vivado HLS 14.7
•Xilinx ISE 14.7
 Compiling Dataflow to VHDL

Dataflow RVC-CAL Dataflow Graph made in Eclipse

Orcc 1
(HLS)
C++ VHDL
Vivado 2
(HLS)
VHDL 3
Xilinx ISE

FPGA Hardware
 Problems overcame
 Collaborated with ‘Orcc’ development team

1. Raising issues and

problems, and discuss
for solutions on GitHub

2. Help the
establishment of
website
 Added Linux compalibility to the Orcc compiler
HLS backend
Mean shift: A visual tracking algorithm

The dataflow version is implemented in CAL language

CPU vs FPGA Trade off
 CPU
- lots of memory
- threads
- dynamic scheduling
 FPGA
- streaming applications
- very little memory
- finite device space

Virtex 6 FPGA, Orcc (HLS), Xilinx ISE 14.7

Results submitted:

GlobalSIP 2014 Atlanta, USA

2. Video Processing on Zedboard

Dataflow VHDL FPGA

Video Processing on Zedboard
Future work

Dataflow VHDL FPGA

 Conclusions
 Compiling computer vision tracking algorithm to FPGAs
(Mean shift)
 Exporting CPU/FPGA trade offs of dataflow optimizations
 GlobalSIP
- ‘Profile Driven Dataflow Optimisation of Mean Shift Visual Tracking’
 Collaborations
- Robert Stewart, Deepayan Bhowmik on Mean shift
- Mariem and other Orcc developers on VHDL backend
 Dataflow program on Zedboard
Thank You!