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ZZZ1

LA-6741P
DA60000JE10

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Brazos PCM10 LA6741 Schematics Document

AMD APU Ontario-FT1+ FCH Hudson-M1

2010-11-30
3 3

REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics,Ltd.


Issued Date 2010/05/06 Deciphered Date Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Tuesday, November 30, 2010 Sheet 1 of 36
A B C D E
A B C D E

Compal Confidential
Model Name : Brazos
File Name : LA6741
DDR3-SO-DIMM X2
1 Single Channel BANK 0, 1, 2, 3
1

page 7,8
DDR3-800/1066(1.5V)
DDR3-800/1066(1.35V)
LVDS Conn. AMD FUSION APU
page 11 Ontario FT1
BGA-413 PCI-Express
page4~6

HDMI
page 9 MINI Card LAN(10/100)
WLAN RTL8105E-VC-GR
page 19 page 18

UMI*8
2
CRT 2

page 10
RJ45
page 18

Bluetooth CMOS Camera USB conn x3


AMD HUDSON-M1 page 18 page 11 page 24

605-BALL
Internal 3.3V 48MHz USB
S-ATA clock GEN
page12~16

HDA Codec port 0 3.3V 24.576MHz/48Mhz


ALC259-GR HD Audio
page 20 Card Reader
RTS5138
3 S-ATA HDD LPC BUS page 17 3

Conn.page 17
SPK
CONN 3 in 1
page 21
RTC CKT. socket
page 13
EC page 17

ENE KB926D3
Power/B page 22
Power On/Off CKT. page 23
page 24

USB I/O Conn. Int.KBD


DC/DC Interface CKT. Touch Pad page 23
page 24
page 23
page 25
4
BIOS 4
page 23
Power Circuit DC/DC Debug port
page 19
page 26,28,29
30,31,32,33
Security Classification Compal Secret Data Compal Electronics,Ltd.
2010/05/06 Title

CHARGER LED Issued Date Deciphered Date


MB Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
page 27 page 21 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, November 26, 2010 Sheet 2 of 36
A B C D E
A B C D E

DDR3 Voltage Rails


1
FCH SM Bus0 address FCH SM Bus1 address 1

Device HEX Address Device HEX Address


SDDIM I A0 1010 0000 WLAN
+5VS
power SDDIM II A2 1010 0010
plane +3VS
+1.5VS
+5VALW +CPU_CORE
EC SM Bus1 address EC SM Bus2 address
+B +1.5V +NB_CORE
+3VALW +1.8VS Device HEX Address Device HEX Address
+3VL
+0.75VS Smart Battery 16H 0001 011X b APU internal themal sensor 1001 100X b
State +5VL +1.1VALW +1.1VS
+1.0VS
+RTCVCC

S0
2 O O O O POWER CPU SDDIM 2

SOURCE PLAN HDMI LVDS CRT FCH CORE I/II WLAN BATT APU
S1
O O O O
TDP1_AUXP
APU +3VS V
S3
O O O X TDP1_AUXN

LTDP0_AUXP V
S5 S4/AC
O O X X LTDP1_AUXN
APU +3VS
+5VS
S5 S4/ Battery only DAC_SCL
O X X X APU +3VS
V
DAC_SDA +5VS
S5 S4/AC & Battery
don't exist X X X X SIC
V
APU +3VS
SID +3VALW
SVC
APU +1.8VS V
SVD

SMB_FCH_CK0
3
FCH +3VS V 3
@ Reserve SMB_FCH_DA0

SMB_FCH_CK1
CONN@ ME CONNECTOR FCH +3VALW V
SMB_FCH_DA1

8105E@ 100M LAN function SMB_EC_CK1


EC +5VALW V
SMB_EC_DA1

8111E@ GLAN function SMB_EC_CK2


EC +3VS V
SMB_EC_DA2
REAL@ ALC259-GR

VIA@ V1802T

ROM@ not support flash ROM

FROM@ Support flash ROM


4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/05/06 Deciphered Date Title
MB Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, November 26, 2010 Sheet 3 of 36
A B C D E
A B C D E

POWER SEQUENCE
POWER MAP
+3VL
VIN
1
B+ +5VL 1
B+
UP618CQAG +3VALW
+3VL
+5VALW
+3VALW,+5VALW
SUSP#
+1.1VALW
+1.8VS
SY8033BDBC ON/OFFBTN# NOTE1
T1>10ms, +3VALW to RSMRST#
SUSP# T1
EC->FCH EC_RSMRST#
+5VS T2>100ms, RSMRST# to PBTN_OUT#
T2
SI4800BDY EC->FCH PBTN_OUT#
T3>100ns, PBTN_OUT# to SLP_S5#
T3
EN_WOL# FCH->EC FCH_SLP_S5#
T4>10ms, SLP_S5# to SYSON
+3V_LAN T4
EC->PWR SYSON
AP2301GN
SUSP# +1.5V
The same with SLP_S5#
+3VS
FCH->EC FCH_SLP_S3#
SI4800BDY T5>10ms, SYSON to SUSP#
T5
ENVDD EC->PWR SUSP#
2 2
+LCDVDD
+3VS,+5VS,+0.75VS
POK SI4800BDY
+1.8VS
+1.1VALW
RT8209BGQW
EC->PWR +1.1VS_ON
1.1VSON#
+1.1VS +1.1VS
T6>100ms, SUSP# to VR_ON
IRF8113PBF T6
EC->PWR VR_ON
SUSP#
+1.0VS +CPU_CORE
+CPU_CORE_NB NOTE2
STS11N3LLH5
VR_ON PWR->EC VGATE
T7>50ms, VGATE to EC_FCH_PWROK
+CPU_CORE T7
ISL6265AH EC->FCH EC_FCH_PWROK
RTZ +CPU_CORE_NB
EC->FCH KB_RST#
98ms>T7>150ms, EC_FCH_PWROK to APU_PWRGD
T8
FCH->APU APU_PWRGD
SYSON 101ms>T7>113ms, EC_FCH_PWROK to A_RST#
T9
3 FCH->DEVICE A_RST# 3
+1.5V
RT8209BGQW
SUSP# FCH->APU LDT_RST#
+1.5VS
SI4800BDY NOTE1: RSMRST# rise time(10% to 90%)<50ms
fail time<1ms
SUSP
+0.75VS
VDTT11V8 NOTE2: EC_FCH_PWROK rise time(10% to 90%)<50ms
fail time<1ms

4 4

Security Classification Compal Secret Data Compal Electronics,Ltd.


Issued Date 2010/05/06 Deciphered Date Title
Powe map and sequence
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, November 26, 2010 Sheet 4 of 36
A B C D E
5 4 3 2 1

+1.8VS

TEST_33_H C1 1 2 0.1U_0402_16V4Z R5 1 2 51_0402_1%


R74 2 1 1K_0402_5% TEST_35

R1 1 2 1K_0402_5% APU_LDT_STP# U1B TEST_33_L C2 1 2 0.1U_0402_16V4Z R9 1 2 51_0402_1%

R2 2 1K_0402_5% APU_SVC R8 2 150_0402_1%

DISPLAYPORT 1
1 <10> HDMI_TX2+ A8 H3 1

DP MISC
TDP1_TXP0 DP_ZVSS
<10> HDMI_TX2- B8 TDP1_TXN0
R3 1 2 1K_0402_5% APU_SVD G2
DP_BLON ENBKL <12>
<10> HDMI_TX1+ B9 TDP1_TXP1 DP_DIGON H2 ENVDD <12>
R4 1 2 300_0402_5% LDT_RST# <10> HDMI_TX1- A9 H1
TDP1_TXN1 DP_VARY_BL INV_PWM <12>
R6 1 2 300_0402_5% APU_PWRGD <10> HDMI_TX0+ D10 TDP1_TXP2
<10> HDMI_TX0- C10 TDP1_TXN2 TDP1_AUXP B2 HDMI_SCL <10>
D R7 1 2 510_0402_1% TEST_25_L C2 D
TDP1_AUXN HDMI_DAT <10>
<10> HDMI_CLK+ A10 TDP1_TXP3
R333 1 2 1K_0402_5% TEST_36 B10 C1
<10> HDMI_CLK- TDP1_TXN3 TDP1_HPD HDMI_HPD <10>

<12> LVDS_TX2+ B5 LTDP0_TXP0 LTDP0_AUXP A3 LVDS_SCL <12> +5VS

DISPLAYPORT 0
+3VS <12> LVDS_TX2- A5 LTDP0_TXN0 LTDP0_AUXN B3 LVDS_DAT <12> 1A
D6 D3 R10 2 1 100K_0402_5% C3
<12> LVDS_TX1+ LTDP0_TXP1 LTDP0_HPD
C6 10U_0805_10V4Z 1 2
<12> LVDS_TX1- LTDP0_TXN1
DAC_RED C12 CRT_R <11>
R64 1 2 1K_0402_5% APU_ALERT#_R A6 D13 R12 1 2 150_0402_1%
<12> LVDS_TX0+ LTDP0_TXP2 DAC_REDB
B6 A12 U2
<12> LVDS_TX0- LTDP0_TXN2 DAC_GREEN CRT_G <11>
R14 1 2 1K_0402_5% APU_PROCHOT B12 R13 1 2 150_0402_1% 1 9
DAC_GREENB VEN Thermal Pad
D8

VGA DAC
<12> LVDS_CLK+ LTDP0_TXP3 DAC_BLUE A13 CRT_B <11> 2 VIN GND 8
@R16
@ R16 1 2 1K_0402_5% APU_SIC C8 B13 R15 1 2 150_0402_1% +VCC_FAN1 3 7
<12> LVDS_CLK- LTDP0_TXN3 DAC_BLUEB VO GND
<23> EN_FAN1 4 VSET GND 6
@R17
@ R17 1 2 1K_0402_5% APU_SID V2 E1 1 5
<14> CLK_APU CLKIN_H DAC_HSYNC CRT_HSYNC <11> GND
V1 E2 C4
<14> CLK_APU# CLKIN_L DAC_VSYNC CRT_VSYNC <11>
R18 1 2 4.7K_0402_5% HDMI_DAT G996RD1U_TDFN8_3X3

CLK
<14> CLK_APU_DP D2 DISP_CLKIN_H DAC_SCL F2 CRT_DDC_CLK <11>
R19 HDMI_SCL 2
1 2 4.7K_0402_5% <14> CLK_APU_DP# D1 DISP_CLKIN_L DAC_SDA D4 CRT_DDC_DATA <11>
10U_0805_6.3V6M

R21 1 2 4.7K_0402_5% LVDS_DAT <34> APU_SVC J1 D12 R20 1 2 499_0402_1%


SVC DAC_ZVSS
<34> APU_SVD J2 SVD

SER
R22 1 2 4.7K_0402_5% LVDS_SCL R1 TEST_4 PAD T1
APU_SIC TEST4 TEST_5
P3 SIC TEST5 R2 PAD T2
APU_SID P4 R6
SID TEST6 TEST_14
TEST14 T5 PAD T4
<14> LDT_RST#
R23 0_0402_5% 1 2 LDT_RST#_R T3 RESET_L TEST15 E4 TEST_15
<14> APU_PWRGD
R24 0_0402_5% 1 2 APU_PWRGD_R T4 K4 TEST_16 PAD T5

CTRL
@R35
@ R35 0_0402_5% PWROK TEST16 TEST_17
<14> APU_PROCHOT_FCH# 1 2 TEST17 L1 PAD T6
<23> APU_PROCHOT_EC# R45 1 2 0_0402_5% APU_PROCHOT U1 L2 TEST_18
APU_THERMTRIP#_R PROCHOT_L TEST18 TEST_19
U2 M2

TEST
THERMTRIP_L TEST19
<13> APU_ALERT#
R63 0_0402_5%1 2APU_ALERT#_R T2 ALERT_L TEST25_H K1 TEST_25_H
K2 TEST_25_L
APU_TDI TEST25_L TEST_28_H
N2 TDI TEST28_H L5 PAD T7
APU_TDO N1 M5 TEST_28_L PAD T9
R26 TEST_18 APU_TCLK TDO TEST28_L TEST_31 +3VS
2 1 1K_0402_5% P1 M21

JTAG
C TCK TEST31 PAD T8 C
APU_TMS P2 J18 TEST_33_H @ C6
R27 TEST_19 APU_TRST# TMS TEST33_H TEST_33_L
2 1 1K_0402_5% M4 TRST_L TEST33_L J19 1 2

1
DBRDY M3 U15 TEST_34_H PAD T10
R28 TEST_25_H DBREQ# DBRDY TEST34_H TEST_34_L
1 2 510_0402_1% M1 DBREQ_L TEST34_L T15 PAD T11 R32 1000P_0402_50V7K
H4 TEST_35 10K_0402_5%
@R29
@ R29 TEST_35 TEST35 TEST_36
2 1 1K_0402_5% <34> VDDCR_NB_SENSE_H 1 R271 2 0_0402_5% F4 VDDCR_NB_SENSE TEST36 N5 40mil
TEST_37 JFAN
<34> VDDCR_APU_SENSE_H 1 R272 2 0_0402_5% G1 R5 PAD T13 CONN@

2
R30 TEST_15 VDDCR_CPU_SENSE TEST37 +VCC_FAN1
2 1 1K_0402_5% T28 PAD F3 VDDIO_MEM_S_SENSE 1 1
<23> FAN_SPEED1 2 2
@R31
@ R31 2 1 1K_0402_5% APU_LDT_STP# <34> VDDCR_NB_SENSE_L 1 R273 2 0_0402_5% F1 VSS_SENSE 3 3
<34> VDDCR_APU_SENSE_L 1 R274 2 0_0402_5% TEST38 K3 1
B4 T1 C7 4
RSVD_1 DMAACTIVE_L APU_LDT_STP# <14> GND
W11 1000P_0402_50V7K 5
RSVD_2 GND
V5 RSVD_3 2
ACES_85205-03001
ONTARIO-2M161000-1.6G_BGA413

U1 1.6G@ U1 1.5G@ U1 1.2G@ U1 1.0G@

+3VS
5

2N7002DW-T/R7_SOT363-6
@ 1.6G 1.5G 1.2G 1.0G
APU_SIC 4 3 1 R302 2 0_0402_5% SCL3_LV <15> FCH
Q1B @

1 R366 2 1 R364 2 0_0402_5%


B
0_0402_5%
EC_SMB_CK2 <23> EC B

+3VS
+1.8VS +1.8VS

HDT CONNECTOR
2

2N7002DW-T/R7_SOT363-6
@
APU_SID 1 R363 2 0_0402_5%
AMD APU DEBUG PORT
1 6 SDA3_LV <15> FCH

2
Q1A @
JP1 CONN@
1 R367 2 1 R365 2 0_0402_5% R33 1 2 APU_TCLK R34 2 1 1K_0402_5%
0_0402_5% EC_SMB_DA2 <23> EC 1 2
1K_0402_5% 3 4 APU_TMS R36 2 1 1K_0402_5%

1
3 4
5 6 APU_TDI R37 2 1 1K_0402_5%
5 6
7 8 APU_TDO
0_0402_5% 7 8
APU_TRST# R38 1 2 APU_TRST#_R 9 10 APU_PWRGD
9 10
+3VS 2 1 11 12 LDT_RST#
R39 10K_0402_5% 11 12 +1.8VS
2 1 13 14 DBRDY
R40 10K_0402_5% 13 14
2 1 15 16 DBREQ# R42 1 2 300_0402_5%
15 16
1

R41 10K_0402_5%
R70 17 18 J108_PLLTST0 R43 1 2 0_0402_5% TEST_19
17 18
2

10K_0402_5%
R25 19 20 J108_PLLTST1 R44 1 2 0_0402_5% TEST_18
19 20
1K_0402_5%
2 2
B
1

SAMTE_ASP-136446-07-B
E

APU_THERMTRIP#_R 3 1 APU_THERMTRIP# <15>


C

Q212
A A
MMBT3904_NL_SOT23-3

1 R368 2 0_0402_5%
@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/05/06 Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DISPLAY,CLK,JTAG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, December 03, 2010 Sheet 5 of 36
5 4 3 2 1
5 4 3 2 1

<8,9> DDR_D[0..63]
<8,9> DDR_DM[0..7]
<8,9> DDR_DQS#[0..7]
<8,9> DDR_DQS[0..7]
<8,9> DDR_MA[0..15]

U1E
DDR_MA0 R17 B14 DDR_D0
DDR_MA1 M_ADD0 M_DATA0 DDR_D1
H19 M_ADD1 M_DATA1 A15
DDR_MA2 J17 A17 DDR_D2
DDR_MA3 M_ADD2 M_DATA2 DDR_D3
H18 M_ADD3 M_DATA3 D18
D DDR_MA4 H17 A14 DDR_D4 D
DDR_MA5 M_ADD4 M_DATA4 DDR_D5
G17 M_ADD5 M_DATA5 C14
DDR_MA6 H15 C16 DDR_D6
DDR_MA7 M_ADD6 M_DATA6 DDR_D7
G18 M_ADD7 M_DATA7 D16
DDR_MA8 F19
DDR_MA9 M_ADD8 DDR_D8
E19 M_ADD9 M_DATA8 C18
DDR_MA10 T19 A19 DDR_D9
DDR_MA11 M_ADD10 M_DATA9 DDR_D10
F17 M_ADD11 M_DATA10 B21 <14> UMI_C_TXP[0..3]
DDR_MA12 E18 D20 DDR_D11
M_ADD12 M_DATA11 <14> UMI_C_TXN[0..3]
DDR_MA13 W17 A18 DDR_D12
DDR_MA14 M_ADD13 M_DATA12 DDR_D13
E16 M_ADD14 M_DATA13 B18
DDR_MA15 G15 A21 DDR_D14
M_ADD15 M_DATA14

DDR SYSTEM MEMORY


C20 DDR_D15
M_DATA15
<8,9> DDR_BS0 R18 M_BANK0
T18 C23 DDR_D16
<8,9> DDR_BS1 M_BANK1 M_DATA16
F16 D23 DDR_D17
<8,9> DDR_BS2 M_BANK2 M_DATA17
F23 DDR_D18
M_DATA18 <14> UMI_C_RXP[0..3]
DDR_DM0 D15 F22 DDR_D19
M_DM0 M_DATA19 <14> UMI_C_RXN[0..3]
DDR_DM1 B19 C22 DDR_D20
DDR_DM2 M_DM1 M_DATA20 DDR_D21
D21 M_DM2 M_DATA21 D22
DDR_DM3 H22 F20 DDR_D22
DDR_DM4 M_DM3 M_DATA22 DDR_D23
P23 M_DM4 M_DATA23 F21
DDR_DM5 V23
DDR_DM6 M_DM5 DDR_D24
AB20 M_DM6 M_DATA24 H21
DDR_DM7 AA16 H23 DDR_D25
M_DM7 M_DATA25 DDR_D26
M_DATA26 K22
DDR_DQS0 A16 K21 DDR_D27
DDR_DQS#0 M_DQS_H0 M_DATA27 DDR_D28 U1A
B16 M_DQS_L0 M_DATA28 G23
DDR_DQS1 B20 H20 DDR_D29 AA6 AB6
DDR_DQS#1 M_DQS_H1 M_DATA29 DDR_D30 P_GPP_RXP0 P_GPP_TXP0
A20 M_DQS_L1 M_DATA30 K20 Y6 P_GPP_RXN0 P_GPP_TXN0 AC6
DDR_DQS2 E23 K23 DDR_D31
DDR_DQS#2 M_DQS_H2 M_DATA31
E22 AB4 AB3

PCIE I/F
C DDR_DQS3 M_DQS_L2 DDR_D32 P_GPP_RXP1 P_GPP_TXP1 C
J22 M_DQS_H3 M_DATA32 N23 AC4 P_GPP_RXN1 P_GPP_TXN1 AC3
DDR_DQS#3 J23 P21 DDR_D33
DDR_DQS4 M_DQS_L3 M_DATA33 DDR_D34 PCIE_ITX_PRX_P2 C338 1
R22 M_DQS_H4 M_DATA34 T20 <19> PCIE_PTX_C_IRX_P2 AA1 P_GPP_RXP2 P_GPP_TXP2 Y1 2 0.1U_0402_16V7K PCIE_ITX_C_PRX_P2 <19>
DDR_DQS#4 DDR_D35 PCIE_ITX_PRX_N2 C339 1 2 0.1U_0402_16V7K
DDR_DQS5
P22 M_DQS_L4 M_DATA35 T23
DDR_D36
LAN <19> PCIE_PTX_C_IRX_N2 AA2 P_GPP_RXN2 P_GPP_TXN2 Y2 PCIE_ITX_C_PRX_N2 <19> LAN
W22 M_DQS_H5 M_DATA36 M20
DDR_DQS#5 V22 P20 DDR_D37 Y4 V3 PCIE_ITX_PRX_P3 C340 1 2 0.1U_0402_16V7K
M_DQS_L5 M_DATA37 <20> PCIE_PTX_C_IRX_P3 P_GPP_RXP3 P_GPP_TXP3 PCIE_ITX_C_PRX_P3 <20>
DDR_DQS6 DDR_D38 PCIE_ITX_PRX_N3 C341 1 2 0.1U_0402_16V7K
DDR_DQS#6
AC20 M_DQS_H6 M_DATA38 R23
DDR_D39
WLAN <20> PCIE_PTX_C_IRX_N3 Y3 P_GPP_RXN3 P_GPP_TXN3 V4 PCIE_ITX_C_PRX_N3 <20> WLAN
AC21 M_DQS_L6 M_DATA39 T22
DDR_DQS7 AB16 +1.0VS R46 1 2 2K_0402_1% Y14 AA14 R47 1 2 1.27K_0402_1%
DDR_DQS#7 M_DQS_H7 DDR_D40 P_ZVDD_10 P_ZVSS
AC16 M_DQS_L7 M_DATA40 V20
V21 DDR_D41
M_DATA41 DDR_D42
<8> DDR_A_CLK0 M17 M_CLK_H0 M_DATA42 Y23
M16 Y22 DDR_D43 UMI_C_RXP0 AA12 AB12 UMI_TXP0 C9 1 2 0.1U_0402_16V7K UMI_C_TXP0
<8> DDR_A_CLK0# M_CLK_L0 M_DATA43 P_UMI_RXP0 P_UMI_TXP0
M19 T21 DDR_D44 UMI_C_RXN0 Y12 AC12 UMI_TXN0 C10 1 2 0.1U_0402_16V7K UMI_C_TXN0
<8> DDR_A_CLK1 M_CLK_H1 M_DATA44 P_UMI_RXN0 P_UMI_TXN0
M18 U23 DDR_D45
<8> DDR_A_CLK1# M_CLK_L1 M_DATA45
N18 W23 DDR_D46 UMI_C_RXP1 AA10 AC11 UMI_TXP1 C11 1 2 0.1U_0402_16V7K UMI_C_TXP1

UMI I/F
<9> DDR_B_CLK0 M_CLK_H2 M_DATA46 P_UMI_RXP1 P_UMI_TXP1
N19 Y21 DDR_D47 UMI_C_RXN1 Y10 AB11 UMI_TXN1 C12 1 2 0.1U_0402_16V7K UMI_C_TXN1
<9> DDR_B_CLK0# M_CLK_L2 M_DATA47 P_UMI_RXN1 P_UMI_TXN1
<9> DDR_B_CLK1 L18 M_CLK_H3
L17 Y20 DDR_D48 UMI_C_RXP2 AB10 AA8 UMI_TXP2 C13 1 2 0.1U_0402_16V7K UMI_C_TXP2
<9> DDR_B_CLK1# M_CLK_L3 M_DATA48 P_UMI_RXP2 P_UMI_TXP2
AB22 DDR_D49 UMI_C_RXN2 AC10 Y8 UMI_TXN2 C14 1 2 0.1U_0402_16V7K UMI_C_TXN2
M_DATA49 DDR_D50 P_UMI_RXN2 P_UMI_TXN2
<8,9> DDR_RST# L23 M_RESET_L M_DATA50 AC19
N17 AA18 DDR_D51 UMI_C_RXP3 AC7 AB8 UMI_TXP3 C15 1 2 0.1U_0402_16V7K UMI_C_TXP3
<8,9> DDR_EVENT# M_EVENT_L M_DATA51 P_UMI_RXP3 P_UMI_TXP3
AA23 DDR_D52 UMI_C_RXN3 AB7 AC8 UMI_TXN3 C16 1 2 0.1U_0402_16V7K UMI_C_TXN3
M_DATA52 DDR_D53 P_UMI_RXN3 P_UMI_TXN3
M_DATA53 AA20
F15 AB19 DDR_D54 ONTARIO-2M161000-1.6G_BGA413
<8,9> DDR_CKE0 M_CKE0 M_DATA54
E15 Y18 DDR_D55
<8,9> DDR_CKE1 M_CKE1 M_DATA55
AC17 DDR_D56
M_DATA56 DDR_D57
M_DATA57 Y16
W19 AB14 DDR_D58
<8> DDR_A_ODT0 M0_ODT0 M_DATA58
V15 AC14 DDR_D59
<8> DDR_A_ODT1 M0_ODT1 M_DATA59
U19 AC18 DDR_D60
B <9> DDR_B_ODT0 M1_ODT0 M_DATA60 B
W15 AB18 DDR_D61
<9> DDR_B_ODT1 M1_ODT1 M_DATA61
AB15 DDR_D62
M_DATA62 DDR_D63 +1.5V
<8> DDR_A_CS0# T17 M0_CS_L0 M_DATA63 AC15
<8> DDR_A_CS1# W16 M0_CS_L1
<9> DDR_B_CS0# U17 M1_CS_L0 +M_VREF +1.5V
<9> DDR_B_CS1# V16 M1_CS_L1 M_VREF M23

1
U18 R48
<8,9> DDR_RAS# M_RAS_L
<8,9> DDR_CAS# V19 M_CAS_L
V17 M22 R49 1 2 39.2_0402_1% 1K_0402_1%
<8,9> DDR_WE# M_WE_L M_ZVDDIO_MEM_S

2
ONTARIO-2M161000-1.6G_BGA413 +M_VREF 1000P_0402_50V7K
1 1
C428 C172

1
R50
2 2
1K_0402_1%
0.1U_0402_16V4Z

2
+1.5V

DDR_EVENT# R51 2 1 1K_0402_1%

DDR_RST# R69 2 1 1K_0402_1%


@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/05/06 Deciphered Date Title
DDRIII,UMI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, December 03, 2010 Sheet 6 of 36
5 4 3 2 1
5 4 3 2 1

+CPU_CORE

+CPU_CORE

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M
+CPU_CORE

+1.8VS_VDD 次_5A
120次 +1.8VS
1 1 1

180P_0402_50V8J
U1C 2000mA DCR:0.02次
次 C24 + C25 + C26 +

180P_0402_50V8J
11000mA 1 1

TSense/PLL/DP/PCIE/IO
E5 U8 180P_0402_50V8J 1U_0402_6.3V4Z 1U_0402_6.3V4Z L1 1 2
VDDCR_CPU_1 VDD_18_1 FBMA-L11-201209-121LMA50 C929 C930
E6 VDDCR_CPU_2 VDD_18_2 W8
@ @ 2 2 2
F5 VDDCR_CPU_3 VDD_18_3 U6 1 1 1 1 1 1 1
C426 C20 C19 C21 C17 C18 2 2
F7 VDDCR_CPU_4 VDD_18_4 U9
D G6 W6 1U_0402_6.3V4Z D
VDDCR_CPU_5 VDD_18_5 @
G8 VDDCR_CPU_6 VDD_18_6 T7
H5 V7 C939 2 2 2 2 2 2 2
VDDCR_CPU_7 VDD_18_7 +1.8VS

CPU CORE
H7 0.1U_0402_16V4Z 1U_0402_6.3V4Z 10U_0805_6.3V6M
VDDCR_CPU_8
J6 VDDCR_CPU_9 ESR:9ohm(MAX)
J8 VDDCR_CPU_10
L7 VDDCR_CPU_11

330U_D2_2.5VY_R9M
M6 VDDCR_CPU_12
M8 VDDCR_CPU_13
N7 +CPU_CORE
VDDCR_CPU_14 1 1
+CPU_CORE_NB @ C23
R8 VDDCR_CPU_15 +1.8VS_DAC 次_3A
220次 +1.8VS + + C22
10000mA 150mA 次
DCR:0.04次 330U_2.5V_M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M

DAC
E8 W9 1U_0402_6.3V4Z L2 1 2
VDDCR_NB_1 VDD_18_DAC 2 2
E11 VDDCR_NB_2 1 1 1 1 1 1 1 1 1 1
E13 180P_0402_50V8J C28 C27 FBMA-L11-201209-221LMA30T_0805
VDDCR_NB_3 C938 C29 C30 C31 C32 C33 C34 C35
F9 VDDCR_NB_4 @ 10U_0805_6.3V6M
F12 VDDCR_NB_5 2 2 2 ESR:17ohm(MAX) 2 2 2 2 2 2 2
GPU AND NB CORE

G11
G13
VDDCR_NB_6
VDDCR_NB_7
POWER
H9 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VDDCR_NB_8
H12 VDDCR_NB_9 +1.0VS_VDDPL 次_3A
220次 +1.0VS +CPU_CORE
K11 VDDCR_NB_10 200mA 次
DCR:0.04次 1U_0402_6.3V4Z 1U_0402_6.3V4Z
K13 VDDCR_NB_11
DIS PLL

L10 VDDCR_NB_12 VDDPL_10 U11 180P_0402_50V8J 1U_0402_6.3V4Z L3 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z


L12 VDDCR_NB_13 1 1 1 1
L14 C38 C37 FBMA-L11-201209-221LMA30T_0805 1 1 1 1 1 1 1 1 1
VDDCR_NB_14 C936 C36 C39 C40 C41 C42 C43 C44 C45 C46 C47
M11 VDDCR_NB_15
M12 @ 10U_0805_6.3V6M
VDDCR_NB_16 2 2 2 2
M13 VDDCR_NB_17 0.1U_0402_16V4Z 2 2 2 2 2 2 2 2 2
N10 VDDCR_NB_18 +1.0VS_VDD
C
N12 VDDCR_NB_19 次_5A +1.0VS
120次 C
N14 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VDDCR_NB_20 次
DCR:0.02次
PCIE/IO/DDR3 Phy

P11 5500mA0.1U_0402_16V4Z 1U_0402_6.3V4Z


+1.5V VDDCR_NB_21 1U_0402_6.3V4Z 10U_0805_6.3V6M L4 1
P13 VDDCR_NB_22 VDD_10_1 U13 2
W13 FBMA-L11-201209-121LMA50
VDD_10_2
2000mA VDD_10_3 V12 1
C52
1
C53
1
C50
1
C51
1
C48
1
C49
1
+CPU_CORE_NB
G16 VDDIO_MEM_S_1 VDD_10_4 T12
G19 C937 10U_0805_6.3V6M
VDDIO_MEM_S_2 @
E17 VDDIO_MEM_S_3 180P_0402_50V8J 2 2 2 2 2 2 2

180P_0402_50V8J
J16 VDDIO_MEM_S_4 +CPU_CORE_NB
DDR3

180P_0402_50V8J
L16 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1 1
VDDIO_MEM_S_5
L19 VDDIO_MEM_S_6 ESR:9ohm(MAX) C931 C932
N16 VDDIO_MEM_S_7
R16 @ @
DP Phy/IO

VDDIO_MEM_S_8 +3VS 2 2
R19 VDDIO_MEM_S_9 500mA

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M
W18 VDDIO_MEM_S_10
U16 VDDIO_MEM_S_11 VDD_33 A4

10U_0805_6.3V6M
1 1 1
1 1 C55 @
ONTARIO-2M161000-1.6G_BGA413 C167 C54 1U_0402_6.3V4Z C56 + C57 +
0.1U_0402_16V4Z +CPU_CORE_NB
2
2 2 +1.0VS 2 2 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M

U1D 1 1 1 1 1
A7 VSS_1 VSS_50 N13
C58 C59 C60 C61 C62
B7 VSS_2 VSS_51 N20 ESR:9ohm(MAX)
B11 VSS_3 VSS_52 N22 1 2 2 2 2 2
B17 VSS_4 VSS_53 P10 1
B22 P14 + C64
VSS_5 VSS_54 C63 @ 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
C4 VSS_6 VSS_55 R4
D5 R7 +CPU_CORE_NB
VSS_7 VSS_56 220U_D2_4VM_R15 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z
D7 VSS_8 VSS_57 R20
B D9 T6 0.1U_0402_16V4Z 0.1U_0402_16V4Z B
VSS_9 VSS_58 1U_0402_6.3V4Z
D11 VSS_10 VSS_59 T9
D14 VSS_11 VSS_60 T11 1 1 1 1 1 1 1 1 1
B15 T13 C65 C66 C67 C68 C69 C70 C71 C72 C73
VSS_12 VSS_61
D17 VSS_13 VSS_62 U4
D19 VSS_14 VSS_63 U5
2 2 2 2 2 2 2 2 2
E7 VSS_15 VSS_64 U7
GND

E9 VSS_16 VSS_65 U12


E12 U20 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VSS_17 VSS_66 1U_0402_6.3V4Z 1U_0402_6.3V4Z
E20 VSS_18 VSS_67 U22
F8 VSS_19 VSS_68 V8
F11 VSS_20 VSS_69 V9
F13 VSS_21 VSS_70 V11
G4 V13 +1.5V
VSS_22 VSS_71
G5 VSS_23 VSS_72 W1
G7 VSS_24 VSS_73 W2

180P_0402_50V8J
G9 VSS_25 VSS_74 W4

180P_0402_50V8J
G12 VSS_26 VSS_75 W5 1 1
G20 W7 +1.5V
VSS_27 VSS_76 C933 C934
G22 VSS_28 VSS_77 W12
H6 W20 @ @
VSS_29 VSS_78 2 2
H11 VSS_30 VSS_79 Y5 ESR:9ohm(MAX)
H13 VSS_31 VSS_80 Y7
J4 Y9 330U_D2_2.5VY_R9M
VSS_32 VSS_81
J5 VSS_33 VSS_82 Y11 1 1
J7 Y13 C75 @
VSS_34 VSS_83 C74 + 10U_0805_6.3V6M +1.5V
J20 VSS_35 VSS_84 Y15
K10 Y17 1U_0402_6.3V4Z 1U_0402_6.3V4Z
VSS_36 VSS_85 2 10U_0805_6.3V6M 1U_0402_6.3V4Z 0.1U_0402_16V4Z
K14 VSS_37 VSS_86 Y19
2
L4 VSS_38 VSS_87 AA4
L6 VSS_39 VSS_88 AA22 1 1 1 1 1 1 1 1 1
L8 AB2 C78 C79 C80 C81 C82 C83 C84
A VSS_40 VSS_89 C76 C77 A
L11 VSS_41 VSS_90 AB5
L13 VSS_42 VSS_91 AB9
2 2 2 2 2 2 2 2 2
L20 VSS_43 VSS_92 AB13
L22 VSS_44 VSS_93 AB17
M7 AB21 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VSS_45 VSS_94 1U_0402_6.3V4Z
N4 VSS_46 VSS_95 AC5
N6 VSS_47 VSS_96 AC9
N8
N11
VSS_48
VSS_49
VSS_97
VSSBG_DAC
AC13
A11
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/05/06 Deciphered Date Title

ONTARIO-2M161000-1.6G_BGA413 PWR,BYPASS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, November 26, 2010 Sheet 7 of 36
5 4 3 2 1
5 4 3 2 1

+1.5V +1.5V

<6,9> DDR_DQS#[0..7] JDDR1 CONN@


+1.5V R52 +VREF_DQA
<6,9> DDR_D[0..63] +V_DDR3_DIMM_REF 1 2 0_0402_5% 1 VREF_DQ VSS 2
3 4 DDR_D4
DDR_D0 VSS DQ4 DDR_D5
<6,9> DDR_DM[0..7] 5 DQ0 DQ5 6

1
1 1 0.1U_0402_16V4Z DDR_D1 7 8
R53 +V_DDR3_DIMM_REF C86 C85 DQ1 VSS DDR_DQS#0
<6,9> DDR_DQS[0..7] 9 VSS DQS0# 10
1000P_0402_50V7K DDR_DM0 11 12 DDR_DQS0
1K_0402_1% DM0 DQS0
<6,9> DDR_MA[0..15] 13 VSS VSS 14
2 2 DDR_D2 DDR_D6
15 16
2

+V_DDR3_DIMM_REF DDR_D3 DQ2 DQ6 DDR_D7


17 DQ3 DQ7 18
19 VSS VSS 20
1

DDR_D8 21 22 DDR_D12
R54 DDR_D9 DQ8 DQ12 DDR_D13
23 DQ9 DQ13 24
D 25 26 D
1K_0402_1% DDR_DQS#1 VSS VSS DDR_DM1
27 DQS1# DM1 28
DDR_DQS1 29 30 DDR_RST# <6,9>
2

DQS1 RESET#
31 VSS VSS 32
DDR_D10 33 34 DDR_D14
DDR_D11 DQ10 DQ14 DDR_D15
35 DQ11 DQ15 36
Put it between DDR3 +1.5VS shape and GND shape DDR_D16
37 VSS VSS 38
DDR_D20
39 DQ16 DQ20 40
+1.5V DDR_D17 41 42 DDR_D21
0.1U_0402_16V4Z DQ17 DQ21
43 VSS VSS 44
DDR_DQS#2 45 46 DDR_DM2
DDR_DQS2 DQS2# DM2
47 DQS2 VSS 48
1 1 1 1 1 49 50 DDR_D22
DDR_D18 VSS DQ22 DDR_D23
51 DQ18 DQ23 52
C330 C113 C293 @ C328 @ C329 @ DDR_D19 53 54
@ @ DQ19 VSS DDR_D28
0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K 55 VSS DQ28 56
2 2 2 2 2 DDR_D24 DDR_D29
57 DQ24 DQ29 58
DDR_D25 59 60
DQ25 VSS DDR_DQS#3
61 62 Need close to JDDR1
DDR_DM3 VSS DQS3# DDR_DQS3 @
63 DM3 DQS3 64 C264
0.1U_0402_16V4Z 65 66
DDR_D26 VSS VSS DDR_D30 DDR_CKE1
67 DQ26 DQ30 68 1 2
DDR_D27 69 70 DDR_D31
DQ27 DQ31
Layout Note: 71 VSS VSS 72 33P_0402_50V8J
Place near JDDR1

<6,9> DDR_CKE0 73 CKE0 CKE1 74 DDR_CKE1 <6,9>


Layout Note: Place these 4 Caps near Command 75 VDD VDD 76
77 78 DDR_MA15
and Control signals of DIMMA NC A15 DDR_MA14
change two 100U to one 220U <6,9> DDR_BS2 79 BA2 A14 80
81 82
C +1.5V 06/21 DDR_MA12 83
VDD VDD
84 DDR_MA11 C
DDR_MA9 A12/BC# A11 DDR_MA7
85 A9 A7 86
10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0603_6.3V6M 87 88
DDR_MA8 VDD VDD DDR_MA6
89 A8 A6 90
1 DDR_MA5 91 92 DDR_MA4
A5 A4
1 1 1 1 1 1 1 1 1 1 1 1 93 VDD VDD 94
C92 C94 C96 + C87 DDR_MA3 95 96 DDR_MA2
C91 C93 C95 C97 C98 C99 C100 C101 C102 @ DDR_MA1 A3 A2 DDR_MA0
97 A1 A0 98
220U_D2_4VM_R15 99 100
2 2 2 2 2 2 2 2 2 2 2 2 2 VDD VDD
<6> DDR_A_CLK0 101 CK0 CK1 102 DDR_A_CLK1 <6>
<6> DDR_A_CLK0# 103 CK0# CK1# 104 DDR_A_CLK1# <6>
105 VDD VDD 106
DDR_MA10 107 108
A10/AP BA1 DDR_BS1 <6,9>
10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0603_6.3V6M 109 110
<6,9> DDR_BS0 BA0 RAS# DDR_RAS# <6,9>
111 VDD VDD 112
<6,9> DDR_WE# 113 WE# S0# 114 DDR_A_CS0# <6>
<6,9> DDR_CAS# 115 CAS# ODT0 116 DDR_A_ODT0 <6>
117 VDD VDD 118
DDR_MA13 +V_DDR3_DIMM_REF
119 A13 ODT1 120 DDR_A_ODT1 <6>
<6> DDR_A_CS1# 121 S1# NC 122
Layout Note: 123 VDD VDD 124
+DDR_VREF_CA_DIMMA R55
125 126 1 2 0_0402_5%
Place near JDDR1.203 & JDDR1.204 127
TEST VREF_CA
128
DDR_D32 VSS VSS DDR_D36
129 DQ32 DQ36 130 1 1
DDR_D33 131 132 DDR_D37 C89
DQ33 DQ37 1000P_0402_50V7K C90
133 VSS VSS 134
DDR_DQS#4 135 136 DDR_DM4 0.1U_0402_16V4Z
+0.75VS DDR_DQS4 DQS4# DM4 2 2
137 DQS4 VSS 138
139 140 DDR_D38
1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0805_6.3V6M DDR_D34 VSS DQ38 DDR_D39
141 DQ34 DQ39 142
DDR_D35 143 144
DQ35 VSS DDR_D44
145 VSS DQ44 146
B DDR_D40 147 148 DDR_D45 B
DDR_D41 DQ40 DQ45
1 1 1 1 1 1 149 DQ41 VSS 150
C106 C107 C108 C109 C110 151 152 DDR_DQS#5
C105 DDR_DM5 VSS DQS5# DDR_DQS5
153 DM5 DQS5 154
155 VSS VSS 156
2 2 2 2 2 2 DDR_D42 DDR_D46
157 DQ42 DQ46 158
DDR_D43 159 160 DDR_D47
DQ43 DQ47
161 VSS VSS 162
DDR_D48 163 164 DDR_D52
1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0805_6.3V6M DDR_D49 DQ48 DQ52 DDR_D53
165 DQ49 DQ53 166
167 VSS VSS 168
DDR_DQS#6 169 170 DDR_DM6
DDR_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_D54
DDR_D50 VSS DQ54 DDR_D55
175 DQ50 DQ55 176
DDR_D51 177 178
DQ51 VSS DDR_D60
179 VSS DQ60 180
DDR_D56 181 182 DDR_D61
DDR_D57 DQ56 DQ61
183 DQ57 VSS 184
185 186 DDR_DQS#7
DDR_DM7 VSS DQS7# DDR_DQS7
187 DM7 DQS7 188
189 VSS VSS 190
DDR_D58 191 192 DDR_D62
DDR_D59 DQ58 DQ62 DDR_D63
193 DQ59 DQ63 194
195 VSS VSS 196
R56 1 2 10K_0402_5% 197 198
SA0 EVENT# DDR_EVENT# <6,9>
+3VS 199 VDDSPD SDA 200 SMB_FCH_DA0 <9,15>
201 SA1 SCL 202 SMB_FCH_CK0 <9,15>
1 1 203 VTT VTT 204 +0.75VS
1

C103 C104 205 GND1


5.2mmGND2 206
2.2U_0603_6.3V6K 0.1U_0402_16V4Z R57 207 208
A 2 2 10K_0402_5% BOSS1 BOSS2
LCN_DAN06-K4526-0102
DDR3 SO-DIMM A A

Standard Type
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/05/06 Deciphered Date 2010/02/04 Title
DDRIII-SODIMM A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, December 03, 2010 Sheet 8 of 36
5 4 3 2 1
5 4 3 2 1

+1.5V +1.5V
JDDR2 CONN@
+V_DDR3_DIMM_REF R58 1 2 0_0402_5% VREF_DQB 1 2
VREF_DQ VSS1 DDR_D4
3 VSS2 DQ4 4
DDR_D0 5 6 DDR_D5
DDR_D1 DQ0 DQ5
1 1 0.1U_0402_16V4Z 7 DQ1 VSS3 8
C111 C112 9 10 DDR_DQS#0
1000P_0402_50V7K DDR_DM0 VSS4 DQS#0 DDR_DQS0
11 DM0 DQS0 12
<6,8> DDR_DQS#[0..7] 13 VSS5 VSS6 14
2 2 DDR_D2 DDR_D6
15 DQ2 DQ6 16
DDR_D3 17 18 DDR_D7
<6,8> DDR_D[0..63] DQ3 DQ7
19 VSS7 VSS8 20
DDR_D8 21 22 DDR_D12
D DDR_D9 DQ8 DQ12 DDR_D13 D
<6,8> DDR_DM[0..7] 23 DQ9 DQ13 24
25 VSS9 VSS10 26
DDR_DQS#1 27 28 DDR_DM1
<6,8> DDR_DQS[0..7] DDR_DQS1 DQS#1 DM1
29 DQS1 RESET# 30 DDR_RST# <6,8>
<6,8> DDR_MA[0..15] 31 VSS11 VSS12 32
DDR_D10 33 34 DDR_D14
DDR_D11 DQ10 DQ14 DDR_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_D16 39 40 DDR_D20
DDR_D17 DQ16 DQ20 DDR_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_DQS#2 45 46 DDR_DM2
DDR_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_D22
DDR_D18 VSS18 DQ22 DDR_D23
51 DQ18 DQ23 52
DDR_D19 53 54
DQ19 VSS19 DDR_D28
55 VSS20 DQ28 56
DDR_D24 57 58 DDR_D29
DDR_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_DQS#3
DDR_DM3 VSS22 DQS#3 DDR_DQS3
63 DM3 DQS3 64
Need close to JDDR2 65 66
DDR_D26 VSS23 VSS24 DDR_D30
C288 67 DQ26 DQ30 68
@ DDR_D27 69 70 DDR_D31
DDR_CKE0 DQ27 DQ31
Layout Note: 1 2 71 VSS25 VSS26 72
Place near JP3
33P_0402_50V8J
Layout Note: Place these 4 Caps near Command <6,8> DDR_CKE0 73 CKE0 CKE1 74 DDR_CKE1 <6,8>
75 76
and Control signals of DIMMA 77
VDD1 VDD2
78 DDR_MA15
NC1 A15 DDR_MA14
C +1.5V change two 100U to one 220U <6,8> DDR_BS2 79 BA2 A14 80
C
81 82
10U_0603_6.3V6M 06/21 DDR_MA12 83
VDD3 VDD4
84 DDR_MA11
10U_0603_6.3V6M 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0603_6.3V6M DDR_MA9 A12/BC# A11 DDR_MA7
85 A9 A7 86
87 VDD5 VDD6 88
1 DDR_MA8 89 90 DDR_MA6
DDR_MA5 A8 A6 DDR_MA4
1 1 1 1 1 1 1 1 1 1 1 1 91 A5 A4 92
C118 C123 C124 C125 C126 + C114 93 94
C117 C119 C120 C121 C122 C127 C128 DDR_MA3 VDD7 VDD8 DDR_MA2
95 A3 A2 96
220U_D2_4VM_R15 DDR_MA1 97 98 DDR_MA0
2 2 2 2 2 2 2 2 2 2 2 2 2 A1 A0
99 VDD9 VDD10 100
<6> DDR_B_CLK0 101 CK0 CK1 102 DDR_B_CLK1 <6>
<6> DDR_B_CLK0# 103 CK0# CK1# 104 DDR_B_CLK1# <6>
105 VDD11 VDD12 106
10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0603_6.3V6M DDR_MA10 107 108
A10/AP BA1 DDR_BS1 <6,8>
<6,8> DDR_BS0 109 BA0 RAS# 110 DDR_RAS# <6,8>
111 VDD13 VDD14 112
<6,8> DDR_WE# 113 WE# S0# 114 DDR_B_CS0# <6>
<6,8> DDR_CAS# 115 CAS# ODT0 116 DDR_B_ODT0 <6>
117 VDD15 VDD16 118
Layout Note: DDR_MA13 119 120
A13 ODT1 DDR_B_ODT1 <6> +V_DDR3_DIMM_REF
<6> DDR_B_CS1# 121 122
Place near JP3.203 & JP3.204 123
S1# NC2
124
VDD17 VDD18 DDR_VREF_CA_DIMMB R59
125 NCTEST VREF_CA 126 1 2 0_0402_5%
127 VSS27 VSS28 128
DDR_D32 129 130 DDR_D36 1 1
DDR_D33 DQ32 DQ36 DDR_D37 C115 C116
131 DQ33 DQ37 132
+0.75VS 133 134 1000P_0402_50V7K
DDR_DQS#4 VSS29 VSS30 DDR_DM4 0.1U_0402_16V4Z
135 DQS#4 DM4 136
1U_0402_6.3V6K 1U_0402_6.3V6K DDR_DQS4 2 2
137 DQS4 VSS31 138
139 140 DDR_D38
DDR_D34 VSS32 DQ38 DDR_D39
141 DQ34 DQ39 142
DDR_D35 143 144
B DQ35 VSS33 DDR_D44 B
1 1 1 1 1 145 VSS34 DQ44 146
C129 C130 C131 C132 C133 DDR_D40 147 148 DDR_D45
10U_0805_6.3V6M DDR_D41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDR_DQS#5
2 2 2 2 2 DDR_DM5 VSS36 DQS#5 DDR_DQS5
153 DM5 DQS5 154
155 VSS37 VSS38 156
DDR_D42 157 158 DDR_D46
DDR_D43 DQ42 DQ46 DDR_D47
159 DQ43 DQ47 160
1U_0402_6.3V6K 1U_0402_6.3V6K 161 162
DDR_D48 VSS39 VSS40 DDR_D52
163 DQ48 DQ52 164
DDR_D49 165 166 DDR_D53
DQ49 DQ53
167 VSS41 VSS42 168
DDR_DQS#6 169 170 DDR_DM6
DDR_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_D54
DDR_D50 VSS44 DQ54 DDR_D55
175 DQ50 DQ55 176
DDR_D51 177 178
DQ51 VSS45 DDR_D60
179 VSS46 DQ60 180
DDR_D56 181 182 DDR_D61
DDR_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_DQS#7
DDR_DM7 VSS48 DQS#7 DDR_DQS7
187 DM7 DQS7 188
189 VSS49 VSS50 190
SA0 SA1 DDR_D58 191 192 DDR_D62
@ DDR_D59 DQ58 DQ62 DDR_D63
193 DQ59 DQ63 194
R139 1 2 10K_0402_5% 195 196
R60 1 VSS51 VSS52
Compal 2 10K_0402_5% 197 SA0 EVENT# 198 DDR_EVENT# <6,8>
common design 0 1 +3VS 199 200
VDDSPD SDA SMB_FCH_DA0 <8,15>
1 2 201 SA1 SCL 202 SMB_FCH_CK0 <8,15>
1 1 R61 @ 10K_0402_5% 203 204 +0.75VS
VTT1 VTT2
ADM CRB 1 0
C134 C135 R203
1 2
10K_0402_5% 205
5.2mm 206
A 2.2U_0603_6.3V6K G1 G2 A
2 2 0.1U_0402_16V4Z LCN_DAN06-K4526-0101 DDR3 SO-DIMM B
REV Type

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/05/06 Deciphered Date Title
DDRIII-SODIMM B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, December 03, 2010 Sheet 9 of 36
5 4 3 2 1
5 4 3 2 1

+3VS 1 2 R62 0_0402_5%


D D

2
HDMI_CLK- C136 1 2 0.1U_0402_16V7K HDMI_C_CLK- 2N7002DW-T/R7_SOT363-6
<5> HDMI_CLK-
HDMI_CLK+ C137 1 2 0.1U_0402_16V7K HDMI_C_CLK+
<5> HDMI_CLK+
<5> HDMI_DAT 1 6 HDMIDAT_R
HDMI_TX2+ C138 1 2 0.1U_0402_16V7K HDMI_C_TX2+
<5> HDMI_TX2+
HDMI_TX2- C139 1 2 0.1U_0402_16V7K HDMI_C_TX2- Q2A
<5> HDMI_TX2-
2 1
HDMI_TX1+ C140 1 2 0.1U_0402_16V7K HDMI_C_TX1+ R91 @
<5> HDMI_TX1+

5
HDMI_TX1- C141 1 2 0.1U_0402_16V7K HDMI_C_TX1- 0_0402_5%
<5> HDMI_TX1-
HDMI_TX0+ C142 1 2 0.1U_0402_16V7K HDMI_C_TX0+ <5> HDMI_SCL 4 3 HDMICLK_R
<5> HDMI_TX0+
HDMI_TX0- C143 1 2 0.1U_0402_16V7K HDMI_C_TX0-
<5> HDMI_TX0-
Q2B
2N7002DW-T/R7_SOT363-6
2 1
R93 @
0_0402_5%

L5
HDMI_C_CLK+ 4 3 HDMI_CLK+_CONN
4 3

HDMI_C_CLK- 1 2 HDMI_CLK-_CONN HDMI_DET


1 2 +5VS
WCM-2012-670T +3VS

1
0_0402_5%
1

1
R98 100K_0402_5%

1
L6 R1192 C166 @
C HDMI_C_TX0+ 4 3 HDMI_TX0+_CONN R84 @ @ 0.1U_0402_16V4Z C
4 3 1 2
2.2K_0402_5%

2
5

1
C165 @

2
HDMI_C_TX0- 1 2 HDMI_TX0-_CONN 0.1U_0402_16V4Z

OE#
P

2
1 2 2
2 A Y 4 HDMI_HPD <5>
WCM-2012-670T

G
U7 @

1
74AHCT1G125GW_SOT353-5

3
L7 100K_0402_5%
HDMI_C_TX1+ 4 3 HDMI_TX1+_CONN R119 +5VS
4 3

2
HDMI_C_TX1- 1 2 HDMI_TX1-_CONN
1 2
WCM-2012-670T

D11 @ BAT54S-7-F_SOT23-3
L8

1
HDMI_C_TX2+ 4 3 HDMI_TX2+_CONN
4 3 HDMI_DET

HDMI_C_TX2- 1 2 HDMI_TX2-_CONN
1 2 +5VS
WCM-2012-670T

D5
3 PMEG2010ET SOT23
1 +VCC_HDMI 1 2 +5VS_HDMI 1
HDMI_C_CLK+ @ R65 1 2 0_0402_5% HDMI_CLK+_CONN 2
HDMI_C_CLK- @ R66 1 2 0_0402_5% HDMI_CLK-_CONN F1 C144
HDMI_C_TX0+ @ R67 1 2 0_0402_5% HDMI_TX0+_CONN +5VS_HDMI 1.1A_6VDC_FUSE 0.1U_0402_16V4Z
HDMI_C_TX0- @ R68 0_0402_5% HDMI_TX0-_CONN 2
1 2

1
B HDMI_C_TX1+ @ R71 1 2 0_0402_5% HDMI_TX1+_CONN B
HDMI_C_TX1- @ R72 1 2 0_0402_5% HDMI_TX1-_CONN R78 R79 JHDMI CONN@
HDMI_C_TX2+ @ R73 1 2 0_0402_5% HDMI_TX2+_CONN 2.2K_0402_5% 2.2K_0402_5% HDMI_DET 19
HDMI_C_TX2- @ R75 0_0402_5% HDMI_TX2-_CONN HP_DET
1 2 18 +5V
17

2
HDMIDAT_R DDC/CEC_GND
16 SDA
HDMICLK_R 15 SCL
14 Reserved
13 CEC
@R1559
@ R1559 1 2 470_0402_1% HDMI_CLK-_CONN 12 20
CK- GND
11 CK_shield GND 21
HDMI_CLK+_CONN 10 22
@R1560
@ R1560 HDMI_TX0-_CONN CK+ GND
1 2 470_0402_1% 9 D0- GND 23
8 D0_shield
HDMI_TX0+_CONN 7
HDMI_CLK+_CONN @R1561
@ R1561 HDMI_TX1-_CONN D0+
1 2 1 2 470_0402_1% 6 D1-
R80 499_0402_1% 5
HDMI_CLK-_CONN HDMI_TX1+_CONN D1_shield
1 2 4 D1+
R81 499_0402_1% @R1562
@ R1562 1 2 470_0402_1% HDMI_TX2-_CONN 3
HDMI_TX0+_CONN D2-
1 2 2 D2_shield
R82 499_0402_1% HDMI_TX2+_CONN 1
HDMI_TX0-_CONN D2+
1 2
R83 499_0402_1% SUYIN_100042GR019M23DZL
HDMI_TX1+_CONN 1 2
R85 499_0402_1% @ 0_0402_5%
1

HDMI_TX1-_CONN D
1 2 2 R90 1 +3VS
R87 499_0402_1% 2 2 1 +5VS
HDMI_TX2+_CONN 1 2 G R88
R89 499_0402_1% S 0_0402_5%
3

HDMI_TX2-_CONN 1 2 Q10
R92 499_0402_1%
2N7002W-T/R7_SOT323-3
A NEAR CONNECT A

Security Classification Compal Secret Data Compal Electronics,Ltd.


Issued Date 2010/05/06 Deciphered Date 2010/02/04 Title
HDMI Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, December 03, 2010 Sheet 10 of 36
5 4 3 2 1
A B C D E

CRT Connector

D7 D8 D9
1 @ @ @ 1
DAN217_SC59 DAN217_SC59 DAN217_SC59 +CRT_VCC

1
+5VS +R_CRT_VCC
D10
3 W=40mils F2 W=40mils
1 1 2
2

3
1.1A_6VDC_FUSE 1
+3VS PMEG2010ET SOT23
C145
0.1U_0402_16V4Z
2

L11 1 2 CRT_R_2 JCRT CONN@


<5> CRT_R
FBMA-L10-160808-600LMT_2P 6
11
L14 1 2 CRT_G_2 1
<5> CRT_G
FBMA-L10-160808-600LMT_2P 7 NEED CHECK SYMBOL
12
L12 1 2 CRT_B_2 2 06/02
<5> CRT_B
FBMA-L10-160808-600LMT_2P 8

5P_0402_50V8C

5P_0402_50V8C

5P_0402_50V8C

5P_0402_50V8C

5P_0402_50V8C
13
150_0402_1%

150_0402_1%

150_0402_1%
C149 1 1 1 C146 1 C147 1 C148 1 3
R96 C150 C151 9

5P_0402_50V8C
R94 R95 14 G 16
4 17
2

2
2 2 2 2 2 2 G
10
15
5
2 SUYIN_070546FR015S297ZR 2
+CRT_VCC
1

100P_0402_50V8J
1 2 R97 2 1 10K_0402_5%
C153 0.1U_0402_16V4Z
C152
5

U4 2
1 1
OE#
P

2 4 CRT_HSYNC_0 1 2 CRT_HSYNC_1 C156 DAT_R R254 1 2 33_0402_5% DAT


<5> CRT_HSYNC A Y R99 27_0402_5% C155
G

10P_0402_50V8J 10P_0402_50V8J CLK_R R294 1 2 33_0402_5% CLK


74AHCT1G125GW_SOT353-5 2 2
3

+CRT_VCC 1 1

68P_0402_50V8K
C154 C157

1 2 68P_0402_50V8K
C158 0.1U_0402_16V4Z 2 2
5

U5
OE#
P

2 4 CRT_VSYNC_0 1 2 CRT_VSYNC_1
<5> CRT_VSYNC A Y R100 27_0402_5%
G

74AHCT1G125GW_SOT353-5
3

3 3

+CRT_VCC

+3VS
2
R102

0_0402_5%

4.7K_0402_5%
1

R103 R104 R105 R106


1

4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%


2

2
2

DAT 6 1 CRT_DDC_DATA <5>


Q3A
2N7002DW-T/R7_SOT363-6

1 2
5

R86 0_0402_5%
@
CLK 3 4 CRT_DDC_CLK <5>
Q3B
2N7002DW-T/R7_SOT363-6

4 4

1 2

R101 0_0402_5%
@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/05/06 Deciphered Date Title
CRT Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, December 03, 2010 Sheet 11 of 36
A B C D E
5 4 3 2 1

LCD POWER CIRCUIT


+3VALW +3VS
D +LCDVDD D
W=60mils

1
1

1
R107 1 C160
300_0603_5% R108 C159
100K_0402_5% 4.7U_0805_10V4Z
0.1U_0402_16V4Z 2

1 2
2

3
D S
G
Q11 2 2 1 2 Q12
2N7002W-T/R7_SOT323-3 G R109 100K_0402_5% AO3413_SOT23-3
S D

1
1
D +LCDVDD @R114
@ R114 1
2N7002W-T/R7_SOT323-3 <23> EC_INVT_PWM 2 0_0402_5%
ENVDD R110 1 2 0_0402_5% 2
<5> ENVDD Q13
G R115 1 2 0_0402_5% INVTPWM
<5> INV_PWM
S 0.1U_0402_16V4Z

3
1 1 1 1 <5> ENBKL 2 1 EC_ENBKL <23>
@ C161 C343 C162 R116 0_0402_5%
R111

1
100K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 R117
2

10K_0402_5%

2
+LCD_INV
C C

B+
1.5A L18
2 1 +5VS_LVDS_CAM
FBMA-L11-201209-221LMA30T_0805 W=30mils
1 1 1
C168 R113 0_0603_5%
C169 @C171
@ C171 +5VS 2 1
68P_0402_50V8J 0.1U_0603_25V7K 680P_0402_50V7K
2 2 2

2
Rated Current MAX:3000mA C170
47P_0402_50V8J

1
<15> USB20_N1 R120 1 2 0_0402_5% USB20_N1_R
<15> USB20_P1 R121 1 2 0_0402_5% USB20_P1_R

B JLVDS CONN@ B

<5> LVDS_CLK- 1 1 2 2 +LCD_INV


<5> LVDS_CLK+ 3 3 4 4
5 L20 @
5 6 6
<5> LVDS_TX2- 7 7 8 8 +LCDVDD 1 1 2 2
9 +3VS
<5> LVDS_TX2+ 9 10 10
11 11 12 12
<5> LVDS_TX0- 13 13 14 14 4 4 3 3
<5> LVDS_TX0+ 15 15 16 16 1 1
1

17 @ WCM2012F2SF-121T04_0805
17 18 18 +5VS_LVDS_CAM
C431 C714 100K_0402_5%
<5> LVDS_TX1- 19 19 20 20
21 0.1U_0402_16V4Z 0.1U_0402_16V4Z R1191
<5> LVDS_TX1+ 21 22 22 USB20_P1_R 2 2
23 23 24 24
25 USB20_N1_R
<5> LVDS_DAT 26 26
2

25
<5> LVDS_SCL 27 27 28 28
INVTPWM 29 BKOFF#
29 30 30 BKOFF# <23>
31 GND GND 32
D28 @

1
ACES_87242-3001-09 USB20_N1_R 2
R112 1
10K_0402_5% USB20_P1_R 3

PJDLC05_SOT23-3
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/05/06 Deciphered Date Title
LVDS & DVI Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, December 03, 2010 Sheet 12 of 36
5 4 3 2 1
5 4 3 2 1

0.01U_0402_16V7K U6B
SATA_ITX_C_DRX_P0 2 1 C173 SATA_ITX_DRX_P0 AH9 AH28
D <18> SATA_ITX_C_DRX_P0 SATA_TX0P FC_CLK D
SATA_ITX_C_DRX_N0 2 1 C174 SATA_ITX_DRX_N0 AJ9 AG28
<18> SATA_ITX_C_DRX_N0 SATA_TX0N FC_FBCLKOUT
SATA for HDD1 0.01U_0402_16V7K AF26
SATA_DTX_C_IRX_N0 FC_FBCLKIN
<18> SATA_DTX_C_IRX_N0 AJ8 SATA_RX0N
SATA_DTX_C_IRX_P0 AH8 AF28
<18> SATA_DTX_C_IRX_P0 SATA_RX0P FC_OE_L/GPIOD145
FC_AVD_L/GPIOD146 AG29
AH10 SATA_TX1P FC_WE_L/GPIOD148 AG26
AJ10 SATA_TX1N FC_CE1_L/GPIOD149 AF27
FC_CE2_L/GPIOD150 AE29
AG10 SATA_RX1N FC_INT1/GPIOD144 AF29
AF10 SATA_RX1P FC_INT2/GPIOD147 AH27

GPIOD
AG12 SATA_TX2P FC_ADQ0/GPIOD128 AJ27
AF12 SATA_TX2N FC_ADQ1/GPIOD129 AJ26
FC_ADQ2/GPIOD130 AH25
AJ12 SATA_RX2N FC_ADQ3/GPIOD131 AH24

SERIAL ATA
AH12 SATA_RX2P FC_ADQ4/GPIOD132 AG23
FC_ADQ5/GPIOD133 AH23
AH14 SATA_TX3P FC_ADQ6/GPIOD134 AJ22
AJ14 SATA_TX3N FC_ADQ7/GPIOD135 AG21
FC_ADQ8/GPIOD136 AF21
AG14 SATA_RX3N FC_ADQ9/GPIOD137 AH22
AF14 SATA_RX3P FC_ADQ10/GPIOD138 AJ23
FC_ADQ11/GPIOD139 AF23
AG17 SATA_TX4P FC_ADQ12/GPIOD140 AJ24
AF17 SATA_TX4N FC_ADQ13/GPIOD141 AJ25
FC_ADQ14/GPIOD142 AG25
AJ17 SATA_RX4N FC_ADQ15/GPIOD143 AH26
AH17 SATA_RX4P
AJ18 SATA_TX5P

HW MONITOR
AH18 SATA_TX5N FANOUT0/GPIO52 W5
FANOUT1/GPIO53 W6
C AH19 Y9 C
SATA_RX5N FANOUT2/GPIO54
AJ19 SATA_RX5P
FANIN0/GPIO56 W7
FANIN1/GPIO57 V9
1 R122 2 1K_0402_1% SATA_CALRP AB14 W8
SATA_CALRN SATA_CALRP FANIN2/GPIO58
+1.1VS 1 R123 2 931_0402_1% AA14 SATA_CALRN
B6 R129 1 2 10K_0402_5%
10K_0402_5% 2 TEMPIN0/GPIO171
+3VS 1 R124 TEMPIN1/GPIO172 A6 R130 1 2 10K_0402_5%
SATA_LED# AD11 A5 R131 1 2 10K_0402_5%
<24> SATA_LED# SATA_ACT_L/GPIO67 TEMPIN2/GPIO173
TEMPIN3/TALERT_L/GPIO174 B5 APU_ALERT# <5>
TEMP_COMM C7
@
SATA_X1 A3 R281 1 2 10K_0402_5% R125 1 2 10K_0402_5%
VIN0/GPIO175 R136 10K_0402_5%
AD16 SATA_X1 VIN1/GPIO176 B4 1 2
2

A4 R133 1 2 10K_0402_5%
@ R126 VIN2/GPIO177 R182 10K_0402_5%
VIN3/GPIO178 C5 1 2
1M_0402_5% A7 DDR_VID
VIN4/GPIO179 R132 1
VIN5/GPIO180 B7 2 10K_0402_5%
25MHZ_20PF_7A25000012 B8 R127 1 2 10K_0402_5%
1

SATA_X2 VIN6/GBE_STAT3/GPIO181 R128 1


AC16 SATA_X2 VIN7/GBE_LED3/GPIO182 A8 2 10K_0402_5%
Y3 @
1 2

SPI ROM
1 1
@ @ J5 G27
<17> FCH_SPI_DO SPI_DI/GPIO164 NC1
C5 C210 E2 Y2
27P_0402_50V8J <17> FCH_SPI_DI SPI_DO/GPIO163 NC2
27P_0402_50V8J K4
2 2 <17> FCH_SPI_CLK SPI_CLK/GPIO162
<17> FCH_SPI_CS1# K9 SPI_CS1_L/GPIO165
PAD T15 G2 ROM_RST_L/GPIO161
21807-A11-HUDSON-M1_FCBGA605

B B

DDR_VID DDR voltage


DDR_VID
DDR_VID <31>

0 +1.5V
1.5V@
R134 1 2 10K_0402_5%

1 +1.35V

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/05/06 Deciphered Date Title
SATA,SPI,GPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, December 03, 2010 Sheet 13 of 36
5 4 3 2 1
5 4 3 2 1

C176 150P_0402_50V8J

R138 1 2 0_0402_5% 1 2
U6E
PLT_RST# @ R140 2 1 0_0402_5% P1 False W2 +1.8VS +3VS
PCIE_RST_L PCICLK0

PCI CLKS
R150 2 1 33_0402_5% L1 A_RST_L W1 PCICLK1
PCICLK1/GPO36 PCICLK2
PCICLK2/GPO37 W3
UMI_C_RXP0 C177 1 2 0.1U_0402_16V7K UMI_RXP0 AD26 W4 PCICLK3
UMI_TX0P PCICLK3/GPO38

1
UMI_C_RXN0 C178 1 2 0.1U_0402_16V7K UMI_RXN0 AD27 Y1 PCICLK4
UMI_C_RXP1 C179 0.1U_0402_16V7K UMI_RXP1 UMI_TX0N PCICLK4/14M_OSC/GPO39 R135
1 2 AC28 UMI_TX1P
UMI_C_RXN1 C180 1 2 0.1U_0402_16V7K UMI_RXN1 AC29 V2 PAD T16 10K_0402_5%
<6> UMI_C_RXP[0..3] UMI_TX1N PCIRST_L
UMI_C_RXP2 C181 1 2 0.1U_0402_16V7K UMI_RXP2 AB29
<6> UMI_C_RXN[0..3] UMI_TX2P

2
G
UMI_C_RXN2 C182 1 2 0.1U_0402_16V7K UMI_RXN2 AB28

2
UMI_C_RXP3 C183 0.1U_0402_16V7K UMI_RXP3 UMI_TX2N
1 2 AB26 UMI_TX3P AD0/GPIO0 AA1
UMI_C_RXN3 C184 1 2 0.1U_0402_16V7K UMI_RXN3 AB27 AA4 APU_PWRGD 1 R137 2 0_0402_5% APU_PWRGD_Q 3 1
UMI_TX3N AD1/GPIO1 APU_PWRGD_CORE <34>

PCI EXPRESS I/F

D
AD2/GPIO2 AA3
UMI_C_TXP0 AE24 AB1 Q14
D
UMI_C_TXN0 UMI_RX0P AD3/GPIO3 2N7002W-T/R7_SOT323-3 D
AE23 UMI_RX0N AD4/GPIO4 AA5
UMI_C_TXP1 AD25 AB2
UMI_C_TXN1 UMI_RX1P AD5/GPIO5
<6> UMI_C_TXP[0..3] AD24 UMI_RX1N AD6/GPIO6 AB6
UMI_C_TXP2 AC24 AB5
<6> UMI_C_TXN[0..3] UMI_RX2P AD7/GPIO7
UMI_C_TXN2 AC25 AA6
UMI_C_TXP3 UMI_RX2N AD8/GPIO8
AB25 UMI_RX3P AD9/GPIO9 AC2
UMI_C_TXN3 AB24 AC3
UMI_RX3N AD10/GPIO10
AD11/GPIO11 AC4
R149 1 2 590_0402_1% PCIE_CALRP AD29 AC1
R152 1 PCIE_CALRN PCIE_CALRP AD12/GPIO12
+1.1VS 2 2K_0402_1% AD28 PCIE_CALRN AD13/GPIO13 AD1
AD2 +3VALW +3VS +3VS +3VALW +3VS +3VS +3VS +3VS +3VS
AD14/GPIO14
AA28 GPP_TX0P AD15/GPIO15 AC6
AA29 GPP_TX0N AD16/GPIO16 AE2

1
2.2K_0402_5%
Y29 AE1 R142
GPP_TX1P AD17/GPIO17 R141 @ @ R143
@R143 R144 @ R145
@R145 R146 R147 R151 @ R148
Y28 GPP_TX1N AD18/GPIO18 AF8

2.2K_0402_5%
Y26 AE3 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
GPP_TX2P AD19/GPIO19 @ @ @ @
Y27 GPP_TX2N AD20/GPIO20 AF1
W28 AG1

2
GPP_TX3P AD21/GPIO21 CLK_PCI_EC_R
W29 GPP_TX3N AD22/GPIO22 AF2
AD23/GPIO23 AE9 PCI_AD23 <17>
AA22 GPP_RX0P AD24/GPIO24 AD9 PCI_AD24 <17> <15> EC_PWM3

PCI I/F
Y21 GPP_RX0N AD25/GPIO25 AC11 PCI_AD25 <17>
AA25 GPP_RX1P AD26/GPIO26 AF6 PCI_AD26 <17> <15> EC_PWM2
AA24 GPP_RX1N AD27/GPIO27 AF4 PCI_AD27 <17>
W23 AF3 CLK_PCI_DB_R
GPP_RX2P AD28/GPIO28
V24 GPP_RX2N AD29/GPIO29 AH2
W24 AG2 PCICLK1
GPP_RX3P AD30/GPIO30
W25 GPP_RX3N AD31/GPIO31 AH3
AA8 PCICLK2
CBE0_L
CBE1_L AD5
AD8 PCICLK3
CBE2_L
CBE3_L AA10
AE8 PCICLK4
FRAME_L
DEVSEL_L AB9
M23 PCIE_RCLKP/NB_LNK_CLKP IRDY_L AJ3 <15> HDA_SDOUT_R
P23 PCIE_RCLKN/NB_LNK_CLKN TRDY_L AE7
PAR AC5

1
2.2K_0402_5%
R163 2 1 0_0402_5% CLK_APU_DP_R U29 AF5 R154 R155
<5> CLK_APU_DP NB_DISP_CLKP STOP_L
R164 2 1 0_0402_5% CLK_APU_DP#_R U28 AE6 R153 @ R156 R157 R158 R159 R160 R161
<5> CLK_APU_DP# NB_DISP_CLKN PERR_L

2.2K_0402_5%
C AE4 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% C
T17 PAD SERR_L @
T26 NB_HT_CLKP REQ0_L AE11
T18 PAD T27 AH5

2
NB_HT_CLKN REQ1_L/GPIO40
REQ2_L/CLK_REQ8_L/GPIO41 AH4
R166 2 1 0_0402_5% CLK_APU_R V21 AC12
<5> CLK_APU CPU_HT_CLKP REQ3_L/CLK_REQ5_L/GPIO42 T34 PAD
R167 2 1 0_0402_5% CLK_APU#_R T21 AD12
<5> CLK_APU# CPU_HT_CLKN GNT0_L
GNT1_L/GPO44 AJ5
V23 SLT_GFX_CLKP GNT2_L/GPO45 AH6
T23 SLT_GFX_CLKN GNT3_L/CLK_REQ7_L/GPIO46 AB12 T35 PAD
AB11 R248 @ 1 2
R168 1 CLK_PCIE_LAN_R CLKRUN_L
<19> CLK_PCIE_LAN 2 0_0402_5% L29 GPP_CLK0P LOCK_L AD7 10K_0402_5%
R169 1 2 0_0402_5% CLK_PCIE_LAN#_R L28
<19> CLK_PCIE_LAN# GPP_CLK0N
CLOCK GENERATOR

INTE_L/GPIO32 AJ6
R170 1 2 0_0402_5% CLK_PCIE_WAN_R N29 AG6
<20> CLK_PCIE_WLAN GPP_CLK1P INTF_L/GPIO33
R171 1 2 0_0402_5% CLK_PCIE_WAN#_R
<20> CLK_PCIE_WLAN# N28 GPP_CLK1N INTG_L/GPIO34
INTH_L/GPIO35
AG4
AJ4 Net Name Description
M29 GPP_CLK2P
M28 GPP_CLK2N
T25 CLK_PCI_EC_R
0 : Integrated Microcontroller (IMC) Disabled *
GPP_CLK3P CLK_PCI_EC_R 33_0402_5% 2
V25 GPP_CLK3N
LPC LPCCLK0 H24 1 R172 CLK_PCI_EC <23>
CLK_PCI_DB_R 33_0402_5% 2 1 R173
L24
LPCCLK1 H25
J27 LPC_AD0
CLK_PCI_DB <20> 1 : Integrated Microcontroller (IMC) Enabled
GPP_CLK4P LAD0 LPC_AD1 LPC_AD0 <20,23>
L23 GPP_CLK4N LAD1 J26 LPC_AD1 <20,23>
H29 LPC_AD2
LAD2 LPC_AD3 LPC_AD2 <20,23>
P25 GPP_CLK5P LAD3 H28 LPC_AD3 <20,23>
M25 GPP_CLK5N LFRAME_L G28 LPC_FRAME#
LPC_FRAME# <20,23> EC_PWM3 EC_PWM2 ROM TYPE
LDRQ0_L J25
P29 GPP_CLK6P LDRQ1_L/CLK_REQ6_L/GPIO49 AA18 EC_PWM3
P28 GPP_CLK6N SERIRQ/GPIO48 AB19 SERIRQ
SERIRQ <23> 1 0 SPI ROM *
N26 GPP_CLK7P
N27 GPP_CLK7N 1 1 Reserved
ALLOW_LDTSTP/DMA_ACTIVE_L G21 APU_LDT_STP# <5>
CPU

T29 GPP_CLK8P PROCHOT_L H21 APU_PROCHOT_FCH# <5>


T28 GPP_CLK8N LDT_PG K19 APU_PWRGD
APU_PWRGD <5> +RTCVCC EC_PWM2 0 0 Reserved
LDT_STP_L G22
LDT_RST_L J24 LDT_RST# <5>
<18> CLK_SD_48M
R174 2 1 33_0402_5% CLK_SD_48M_R L25 14M_25M_48M_OSC 0 1 LPC ROM

1
B B
C1 FCH_RTCX1
32K_X1 R1554
RTC

XTAL25_IN FCH_RTCX2 120_0402_5%


C190
27P_0402_50V8J
L26 25M_X1 32K_X2 C2
0 : External clock mode.
XTAL25_IN 1 2 D2 CLK_PCI_DB_R
SUSCLK <23>

2
RTCCLK
INTRUDER_ALERT_L B2 1 : Integrated clock mode. *
1

XTAL25_OUT L27 B1 R175 1 2 510_0402_5%


R176 Y1 25M_X2 VDDBT_RTC_G

2
1M_0402_5% 25MHZ_20PF_7A25000012 21807-A11-HUDSON-M1_FCBGA605 2 1
C188 C189 J10 @
0 : Force PCIe interface at Gen I mode.*
2

0.1U_0402_16V7K 1U_0402_6.3V4Z JUMP_43X39


2

XTAL25_OUT 1 2 PCICLK1
1 2
1 R162 2 0_0402_5%
1 : PCIe interface is at Gen II mode.

1
C192 27P_0402_50V8J
+3VS
@
C187 1 2 0.1U_0402_16V7K 0 : Disable the boot fail timer function. *
PCICLK2
5

U9
PLT_RST# 2 B
1 : Enable the boot fail timer function.
P

Y 4 PLT_RST_BUF# <19,20,23>
1 A
G

C191
0 : Disable Debug Straps. *
1

NC7SZ08P5X_NL_SC70-5 18P_0402_50V8J
3

@ R165 2 1 FCH_RTCX1 PCICLK3


100K_0402_5%
X1 1 : Select external Debug Straps.
2

3 4
2

NC OSC R177
2 NC OSC 1 20M_0603_5% 0 : Required setting for integrated clock mode. *
PCICLK4
RTC Battery
1

32.768KHZ_12.5PF_9H03200413 C193
2 1 FCH_RTCX2 1 : Reserved.
+RTCBATT D29
- PBJ1 @ + R178
560_0603_5%
R227
560_0603_5%
2 +CHGRTC
18P_0402_50V8J
0 : Required setting for integrated clock mode.
2 1 1 2 1 2 1 *
A HDA_SDOUT_R A
3 +RTCVCC 1 : Reserved (Hudson-1 does not support
MAXEL_ML1220T10 BAS40-04_SOT23 2 the lower power mode).
C354
SP093MX0000 1
0.1U_0402_16V7K

J3
+CHGRTC 2 1 +3VL
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/05/06 Deciphered Date Title
PAD-OPEN 2x2m
UMI,PCIE,CLK,PCI,LPC,RTC,CPU
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, December 03, 2010 Sheet 14 of 36
5 4 3 2 1
5 4 3 2 1

+3VALW
U6A

USB MISC
J2 A10 PAD T20 GBE_PHY_INTR R179 2 1 10K_0402_5%
PCI_PME_L/GEVENT4_L USBCLK/14M_25M_48M_OSC

ACPI/WAKE UP EVENTS
K1 RI_L/GEVENT22_L
D3 G19 USB_PCOMP 1 R180 2 11.8K_0402_1% GBE_MDIO R181 2 1 10K_0402_5%
SPI_CS3_L/GBE_STAT1/GEVENT21_L USB_RCOMP
<23> FCH_SLP_S3# F1 SLP_S3_L
H1 USB_OC#0 R186 2 1 200K_0402_5%
<23> FCH_SLP_S5# SLP_S5_L
<23> PBTN_OUT# F2 PWR_BTN_L
FCH_PWROK H5 PWR_GOOD

USB 1.1
G6 SUS_STAT_L USB_FSD1P/GPIO186 J10
B3 H11 USB_OC#7 R183 2 1 200K_0402_5%
T29 PAD TEST0 USB_FSD1N
T30 PAD C4 TEST1/TMS
F6 H9 SCL3_LV R187 2 1 10K_0402_5%
D T31 PAD TEST2 USB_FSD0P/GPIO185 D
<23> GATEA20 AD21 GA20IN/GEVENT0_L USB_FSD0N J8
AE21 SDA3_LV R188 2 1 10K_0402_5%
<23> KB_RST# KBRST_L/GEVENT1_L
<23> EC_SCI# K2 LPC_PME_L/GEVENT3_L USB_HSD13P B12
J29 A12 SMB_FCH_CK1 R184 1 2 2.2K_0402_5%
<23> EC_SMI# LPC_SMI_L/GEVENT23_L USB_HSD13N
H2 GEVENT5_L
J1 F11 SMB_FCH_DA1 R185 1 2 2.2K_0402_5%
PAD T24 SYS_RESET_L/GEVENT19_L USB_HSD12P
<19,20> FCH_PCIE_WAKE# H6 WAKE_L/GEVENT8_L USB_HSD12N E11
F3 FCH_PCIE_WAKE# R189 2 1 10K_0402_5%
IR_RX1/GEVENT20_L
<5> APU_THERMTRIP# J6 THRMTRIP_L/SMBALERT_L/GEVENT2_L USB_HSD11P E14
NB_PWRGD AC19 E12
NB_PWRGD USB_HSD11N +3VS
FCH_RSMRST# G1 J12
RSMRST_L USB_HSD10P
USB_HSD10N J14
AD19 CLK_REQ4_L/SATA_IS0_L/GPIO64
AA16 CLK_REQ3_L/SATA_IS1_L/GPIO63 USB_HSD9P A13 USB20_P9 <25>
AB21 B13 USB(USB/B1) SMB_FCH_CK0 R190 1 2 2.2K_0402_5%
SMARTVOLT1/SATA_IS2_L/GPIO50 USB_HSD9N USB20_N9 <25>
<19> LAN_CLKREQ0# AC18 CLK_REQ0_L/SATA_IS3_L/GPIO60
AF20 D13 SMB_FCH_DA0 R191 1 2 2.2K_0402_5%
SATA_IS4_L/FANOUT3/GPIO55 USB_HSD8P USB20_P8 <25>
AE19 SATA_IS5_L/FANIN3/GPIO59 USB_HSD8N C13 USB20_N8 <25> USB(USB/B2) NB_PWRGD
<21> FCH_SPK AF19 SPKR_GPIO66 1 2

GPIO

USB 2.0
AD22 G12 R192 4.7K_0402_5%
<8,9> SMB_FCH_CK0 SCL0_GPIO43 USB_HSD7P USB20_P7 <20>
<8,9> SMB_FCH_DA0 AE22 SDA0_GPIO47 USB_HSD7N G14 USB20_N7 <20> BT(MINI CARD)
<20> SMB_FCH_CK1 F5 SCL1_GPIO227
<20> SMB_FCH_DA1 F4 SDA1_GPIO228 USB_HSD6P G16
AH21 G18 SCL2 2 1
CLK_REQ2_L/FANIN4_GPIO62 USB_HSD6N R193 10K_0402_5%
<20> WLAN_CLKREQ1# AB18 CLK_REQ1_L/FANOUT4_GPIO61
E1 D16 SDA2 2 1
IR_LED_L/LLB_L/GPIO184 USB_HSD5P R194 10K_0402_5%
AJ21 SMARTVOLT2/SHUTDOWN_L/GPIO51 USB_HSD5N C16
H4 EC_RSMRST# 1 2
PAD T25 DDR3_RST_L/GEVENT7_L R195 2.2K_0402_5%
D5 GBE_LED0/GPIO183 USB_HSD4P B14
D7 A14 GBE_COL 2 1
GBE_LED1/GEVENT9_L USB_HSD4N R196 10K_0402_5%
G5 GBE_LED2/GEVENT10_L
C K3 E18 GBE_CRS 2 1 C
GBE_STAT0/GEVENT11_L USB_HSD3P R197 10K_0402_5%
AA20 CLK_REQG_L/GPIO65_OSCIN USB_HSD3N E16
GBE_RXERR 2 1
J16 R198 10K_0402_5%
USB_HSD2P USB20_P2 <18>
<25> USB_OC#7 H3 BLINK/USB_OC7_L/GEVENT18_L USB_HSD2N J18 USB20_N2 <18> CardReader

USB OC
<23> EC_LID_OUT# D1 USB_OC6_L/IR_TX1/GEVENT6_L
E4 USB_OC5_L/IR_TX0/GEVENT17_L USB_HSD1P B17 USB20_P1 <12>
D4 USB_OC4_L/IR_RX0/GEVENT16_L USB_HSD1N A17 USB20_N1 <12> Camera
E8 USB_OC3_L/AC_PRES/TDO/GEVENT15_L
F7 USB_OC2_L/TCK/GEVENT14_L USB_HSD0P A16 USB20_P0 <25>
E7 USB_OC1_L/TDI/GEVENT13_L USB_HSD0N B16 USB20_N0 <25> USB(MB)
<25> USB_OC#0 F8 USB_OC0_L/TRST_L/GEVENT12_L
@R200
@ R200 2 1 10K_0402_5%
FCH_RSMRST# R199 2 1 0_0402_5% EC_RSMRST# <23>
HD AUDIO

<21> HDA_BITCLK
R201 1 2 33_0402_5%HDA_BITCLK_RM3 AZ_BITCLK SCL2/GPIO193 D25 SCL2
<21> HDA_SDOUT
R202 1 2 33_0402_5%HDA_SDOUT_R N1 AZ_SDOUT SDA2/GPIO194 F23 SDA2
<21> HDA_SDIN0 L2 AZ_SDIN0/GPIO167 SCL3_LV/GPIO195 B26 SCL3_LV <5>
<14> HDA_SDOUT_R M2 AZ_SDIN1/GPIO168 SDA3_LV/GPIO196 E26 SDA3_LV <5>
@R205
@ R205 2 1 10K_0402_5% M1 F25
AZ_SDIN2/GPIO169 EC_PWM0/EC_TIMER0/GPIO197
M4 AZ_SDIN3/GPIO170 EC_PWM1/EC_TIMER1/GPIO198 E22
<21> HDA_SYNC
R206 1 2 33_0402_5% HDA_SYNC_R N2 AZ_SYNC EC_PWM2/EC_TIMER2/GPIO199 F22 EC_PWM2 <14>
<21> HDA_RST#
R207 1 2 33_0402_5% HDA_RST#_R P2 AZ_RST_L EC_PWM3/EC_TIMER3/GPIO200 E21 EC_PWM3 <14>

KSI_0/GPIO201 G24
GBE_COL T1 G25
GBE_CRS GBE_COL KSI_1/GPIO202
T4 GBE_CRS
EMBEDDED CTRL KSI_2/GPIO203 E28
L6 GBE_MDCK KSI_3/GPIO204 E29
GBE_MDIO L5 D29
GBE_MDIO KSI_4/GPIO205
T9 GBE_RXCLK KSI_5/GPIO206 D28
GBE LAN

U1 GBE_RXD3 KSI_6/GPIO207 C29


U3 GBE_RXD2 KSI_7/GPIO208 C28
B T2 B
GBE_RXD1
U2 GBE_RXD0 KSO_0/GPIO209 B28
T5 GBE_RXCTL/RXDV KSO_1/GPIO210 A27
GBE_RXERR V5 B27
GBE_RXERR KSO_2/GPIO211
P5 GBE_TXCLK KSO_3/GPIO212 D26
M5 GBE_TXD3 KSO_4/GPIO213 A26
P9 C26 R209 2 1 0_0402_5%
GBE_TXD2 KSO_5/GPIO214
T7 GBE_TXD1 KSO_6/GPIO215 A24
P7 GBE_TXD0 KSO_7/GPIO216 B25
M7 A25 +3VS @
GBE_TXCTL/TXEN KSO_8/GPIO217 C194 0.1U_0402_16V7K
P4 GBE_PHY_PD KSO_9/GPIO218 D24
M9 GBE_PHY_RST_L KSO_10/GPIO219 B24 1 2
GBE_PHY_INTR V7 C24
GBE_PHY_INTR KSO_11/GPIO220

5
KSO_12/GPIO221 B23
E23 A23 2

P
PAD T32 PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222 B EC_FCH_PWROK <23>
PAD T33 E24 PS2_CLK/SCL4/GPIO188 KSO_14/GPIO223 D22 <34> FCH_PWROK 4 Y
F21 SPI_CS2_L/GBE_STAT2/GPIO166 KSO_15/GPIO224 C22 A 1 VGATE <23,34>

G
PAD T26 G29 FC_RST_L/GPO160 KSO_16/GPIO225 A22
B22 NC7SZ08P5X_NL_SC70-5

3
KSO_17/GPIO226
D27 PS2KB_DAT/GPIO189 U10 @
F28 PS2KB_CLK/GPIO190
F29 PS2M_DAT/GPIO191
E27 PS2M_CLK/GPIO192
21807-A11-HUDSON-M1_FCBGA605

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
USB,GPIO,GLAN,HDA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, December 03, 2010 Sheet 15 of 36
5 4 3 2 1
5 4 3 2 1

+3VS +3VS_SB +1.1VS_VDDCR +1.1VS


42mA U6C POWER 979.4mA
D 2 R210 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z AH1 N13 0.1U_0402_16V4Z 1U_0402_6.3V6K 1 R211 2 D
VDDIO_33_PCIGP_1 VDDCR_11_1

CORE S0
1 1 1 1 V6 R15 1 1 1 1 1 0_0805_5%
VDDIO_33_PCIGP_2 VDDCR_11_2

PCI/GPIO I/O
0_0603_5% C195 C196 C197 C198 Y19 N17 C203 C202 C201 C200 C199
VDDIO_33_PCIGP_3 VDDCR_11_3
AE5 VDDIO_33_PCIGP_4 VDDCR_11_4 U13
AC21 U17 10U_0603_6.3V6M
2 2 2 2 VDDIO_33_PCIGP_5 VDDCR_11_5 2 2 2 2 2 +1.1VS
AA2 VDDIO_33_PCIGP_6 VDDCR_11_6 V12
22U_0805_6.3V6M 0.1U_0402_16V4Z AB4 V18 0.1U_0402_16V4Z 1U_0402_6.3V6K
VDDIO_33_PCIGP_7 VDDCR_11_7
AC8 VDDIO_33_PCIGP_8 VDDCR_11_8 W12
AA7 VDDIO_33_PCIGP_9 VDDCR_11_9 W18
+1.1VS_CLK 次_5A
120次 +1.1VS
AA9
AF7
VDDIO_33_PCIGP_10
382.9mA 次
DCR:0.02次
VDDIO_33_PCIGP_11

CLKGEN I/O

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M
AA19 K28 0.1U_0402_16V4Z 1U_0402_6.3V6K L34 1 2
R212 VDDIO_33_PCIGP_12 VDDAN_11_CLK_1
1 2 0_0402_5% VDDAN_11_CLK_2 K29 1 1 1 1 1 FBMA-L11-201209-121LMA50 1 1
J28 C208 C207 C206 C205 C204
VDDAN_11_CLK_3 C185 + C186 +
0.16mA VDDAN_11_CLK_4 K26

FLASH I/O
J21 @
VDDAN_11_CLK_5 2 2 2 2 2
AF22 VDDIO_18_FC_1 VDDAN_11_CLK_6 J20
0.1U_0402_16V4Z 1U_0402_6.3V6K 22U_0805_6.3V6M 2 2
+3VS 次_0.2A
220次 +3VS_PCIE_VDDPL
AE25 VDDIO_18_FC_2 VDDAN_11_CLK_7 K21
AF24 J22
DCR:0.2次
次 AC22
VDDIO_18_FC_3 VDDAN_11_CLK_8
L22 1 0.1U_0402_16V4Z VDDIO_18_FC_4
2
FBMA-L11-160808-221LMT_2P 1 1 V1 2 R213 1 0_0603_5%
C209 C211 VDDRF_GBE_S
2.2U_0402_6.3VM 22.5mA 2 R214 1 0_0603_5%
VDDIO_33_GBE_S M10 ESR:9ohm(MAX)
2 2

PCI EXPRESS
AE28 VDDPL_33_PCIE
+1.1VS 次_5A
120次 +1.1VS_PCIE

GBE LAN

DCR:0.02次 1115.6mA
U26 VDDAN_11_PCIE_1 VDDCR_11_GBE_S_1 L7 2 R215 1 0_0603_5%
L23 1 2 1U_0402_6.3V6K 0.1U_0402_16V4Z V22 L9
FBMA-L11-201209-121LMA50 VDDAN_11_PCIE_2 VDDCR_11_GBE_S_2
1 1 1 1 1 V26 VDDAN_11_PCIE_3
0.1U_0402_16V4Z

C212 C213 C214 C215 C216 V27


C 22U_0805_6.3V6M @ VDDAN_11_PCIE_4 C
V28 VDDAN_11_PCIE_5 VDDIO_GBE_S_1 M6 2 R216 1 0_0603_5%
V29 VDDAN_11_PCIE_6 VDDIO_GBE_S_2 P8
2 2 2 2 2
W22 VDDAN_11_PCIE_7
1U_0402_6.3V6K W26 VDDAN_11_PCIE_8
+3VS 次_0.2A
220次 +3VS_SATA_VDDPL

DCR:0.2次 15.5mA

SERIAL ATA

3.3V_S5 I/O
L24 1 2 AD14 49.5mA
FBMA-L11-160808-221LMT_2P VDDPL_33_SATA +3VALW_VDDIO +3VALW
1 1 VDDIO_33_S_1 A21
C217 C218
0.1U_0402_16V4Z AJ20 D21
2.2U_0402_6.3VM VDDAN_11_SATA_1 VDDIO_33_S_2
AF18 VDDAN_11_SATA_4 VDDIO_33_S_3 B21 2 R217 1
AH20 VDDAN_11_SATA_2 VDDIO_33_S_4 K10
2 2 0.1U_0402_16V4Z 1 0_0603_5%
+1.1VS 120次 次_5A +1.1VS_SATA
AG19 VDDAN_11_SATA_3 VDDIO_33_S_5 L10
C219 C220
1
C221
1
DCR:0.02次 次 1354.2mA AE18 VDDAN_11_SATA_5 VDDIO_33_S_6 J9
2.2U_0402_6.3VM
AD18 VDDAN_11_SATA_6 VDDIO_33_S_7 T6
L25 1 2 1U_0402_6.3V6K 0.1U_0402_16V4Z AE16 T8
FBMA-L11-201209-121LMA50 VDDAN_11_SATA_7 VDDIO_33_S_8 2 2 2
1 1 1 1 1
C222 C223 C224 C225 C226 +1.1VALW_VDDCR 2.2U_0402_6.3VM +1.1VALW
22U_0805_6.3V6M 0.1U_0402_16V4Z 165.2mA
CORE S5
534.5mA F26 0.1U_0402_16V4Z 2 R218 1 0_0603_5%
2 2 2 2 2 VDDCR_11_S_1
A18 VDDAN_33_USB_S_1 VDDCR_11_S_2 G26 1 1 1
次_3A
220次 1U_0402_6.3V6K A19 15.3mA C246 C227 C228
+3VALW +3VALW_USB_AVDD VDDAN_33_USB_S_2 1U_0402_6.3V6K
A20 M8 +VDDIO_AZ

DCR:0.04次 B18
VDDAN_33_USB_S_3 VDDIO_AZ_S
58mA +1.1VALW_USB_VDDCR
VDDAN_33_USB_S_4 2 2 2 +1.1VALW
USB I/O

L26 1 2 1U_0402_6.3V6K 0.1U_0402_16V4Z B19 A11


FBMA-L11-201209-221LMA30T_0805 VDDAN_33_USB_S_5 VDDCR_11_USB_S_1 1U_0402_6.3V6K
1 1 1 1 1 B20 VDDAN_33_USB_S_6 VDDCR_11_USB_S_2 B11
C231 C232 C233 C18 L27 1 2
C229 C230 VDDAN_33_USB_S_7 FBMA-L11-160808-221LMT_2P
10U_0603_6.3V6M
C20 VDDAN_33_USB_S_8 46.5mA C236
1
C235
1
C234
1
2 2 2 2 2
D18 VDDAN_33_USB_S_9 VDDPL_33_SYS M21 +3VS_VDDPL 次_0.2A
220次
D19 65.3mA 0.1U_0402_16V4Z
VDDAN_33_USB_S_10 DCR:0.2次

PLL

10U_0603_6.3V6M 1U_0402_6.3V6K D20 L22 +1.1VALW_VDDP 10U_0603_6.3V6M


VDDAN_33_USB_S_11 VDDPL_11_SYS_S 2 2 2
B +1.1VALW +1.1VALW_USB_VDDAN
E19 VDDAN_33_USB_S_12 16.1mA 0.1U_0402_16V4Z B
VDDPL_33_USB_S F19 +3VALW_USB_AVDD
L28 1
88.6mA 11.4mA
2 C11 VDDAN_11_USB_S_1 VDDAN_33_HWM_S D6 +3VALW
FBMA-L11-160808-221LMT_2P 1 1 D11 5.0mA
C237 C238 VDDAN_11_USB_S_2
次_0.2A
220次 VDDXL_33_S L20
2.2U_0402_6.3VM 0.1U_0402_16V4Z

DCR:0.2次 21807-A11-HUDSON-M1_FCBGA605 次_0.2A
220次
2 2 +3VS_VDDXL +3VS
DCR:0.2次

L29 1 2
FBMA-L11-160808-221LMT_2P +VDDIO_AZ
1 1
C240 C239
R219 2 1 0_0603_5% +3VALW
0.1U_0402_16V4Z 2.2U_0402_6.3VM 1 R220 2 1 0_0603_5% +1.5V
2 2 C241 @

2.2U_0402_6.3VM
2

+3VALW
+3VS_VDDPL 次_0.2A +3VS
220次 +1.1VALW_VDDP 次_0.2A +1.1VALW
220次

DCR:0.2次 次
DCR:0.2次
L32 1 2 L30 1 2 1
1 1 FBMA-L11-160808-221LMT_2P 1 1 FBMA-L11-160808-221LMT_2P C247 close pin D6
C242 C243 C244 C245
0.1U_0402_16V4Z
2.2U_0402_6.3VM 0.1U_0402_16V4Z 2.2U_0402_6.3VM 0.1U_0402_16V4Z 2
2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, November 26, 2010 Sheet 16 of 36
5 4 3 2 1
5 4 3 2 1

U6D
Y14 VSSIO_SATA_1 VSS_1 AJ2
Y16 VSSIO_SATA_2 VSS_2 A28
AB16 A2 FCH_SPI_DI 2 R1550 1 0_0402_5%
VSSIO_SATA_3 VSS_3 ROM@
AC14 VSSIO_SATA_4 VSS_4 E5
AE12 D23 FCH_SPI_CLK 1 @ 2 FCH_SPI_CLK 2 R1551 1 0_0402_5%
VSSIO_SATA_5 VSS_5 R1455 0_0402_5% ROM@
AE14 VSSIO_SATA_6 VSS_6 E25
AF9 E6 FCH_SPI_CS1# 2 R1552 1 0_0402_5%
VSSIO_SATA_7 VSS_7 ROM@
AF11 VSSIO_SATA_8 VSS_8 F24 1
AF13 N15 @ FCH_SPI_DO 2 R1553 1 0_0402_5%
VSSIO_SATA_9 VSS_9 C928 ROM@
AF16 VSSIO_SATA_10 VSS_10 R13
AG8 R17 10P_0402_50V8J
VSSIO_SATA_11 VSS_11 2
AH7 VSSIO_SATA_12 VSS_12 T10
AH11 VSSIO_SATA_13 VSS_13 P10
D AH13 V11 For EMI close U59 D
VSSIO_SATA_14 VSS_14 U20 FROM@
AH16 VSSIO_SATA_15 VSS_15 U15
AJ7 VSSIO_SATA_16 VSS_16 M18 1 1OE#
AJ11 V19 4 FCH_SPI_DO_R
VSSIO_SATA_17 VSS_17 2OE#
AJ13 VSSIO_SATA_18 VSS_18 M11 10 3OE#
AJ16 VSSIO_SATA_19 VSS_19 L12 13 4OE#

GND
VSS_20 L18
A9 J7 2 3 FCH_SPI_DI_R
VSSIO_USB_1 VSS_21 <13> FCH_SPI_DO 1A 1B
B10 VSSIO_USB_2 VSS_22 P3 <13> FCH_SPI_CS1# 5 2A 2B 6
K11 V4 9 8 FCH_SPI_CLK_R
VSSIO_USB_3 VSS_23 <13> FCH_SPI_CLK 3A 3B
B9 VSSIO_USB_4 VSS_24 AD6 <13> FCH_SPI_DI 12 4A 4B 11
D10 AD4 FCH_SPI_CS1#_R
VSSIO_USB_5 VSS_25 R1557 FROM@ 2 0_0402_5% +3V_SPI
D12 VSSIO_USB_6 VSS_26 AB7 +3VS 1 14 VCC GND 7
D14 AC9 +3VALW R1558 @ 2 1 0_0402_5%
VSSIO_USB_7 VSS_27 SN74CBT3125PWRG4_TSSOP14
D17 VSSIO_USB_8 VSS_28 V8 1
E9 W9 C595
VSSIO_USB_9 VSS_29 0.1U_0402_16V4Z
F9 VSSIO_USB_10 VSS_30 W10 1
F12 AJ28 FROM@ C593
VSSIO_USB_11 VSS_31 2 0.1U_0402_16V4Z
F14 VSSIO_USB_12 VSS_32 B29 2MB
F16 U4 U21
VSSIO_USB_13 VSS_33 FCH_SPI_CS1#_R 2
C9 VSSIO_USB_14 VSS_34 Y18 1 CS# VCC 8
G11 Y10 FCH_SPI_DO_R 2 7
VSSIO_USB_15 VSS_35 DO(IO1) HOLD#(IO3) FCH_SPI_CLK_R
F18 VSSIO_USB_16 VSS_36 Y12 +3V_SPI 3 WP#(IO2) CLK 6
D9 Y11 U22 FROM@ 4 5 FCH_SPI_DI_R
VSSIO_USB_17 VSS_37 GND DI(IO0)
H12 VSSIO_USB_18 VSS_38 AA11 <23,24,29> EC_ON 1 1OE#
H14 AA12 4 W25Q16BVSSIG_SO8
VSSIO_USB_19 VSS_39 2OE#
H16 VSSIO_USB_20 VSS_40 G4 10 3OE#
H18 VSSIO_USB_21 VSS_41 J4 13 4OE#
J11 VSSIO_USB_22 VSS_42 G8
J19 VSSIO_USB_23 VSS_43 G9 <23,24> KSI3 2 1A 1B 3
K12 VSSIO_USB_24 VSS_44 M12 <23,24> KSI7 5 2A 2B 6
K14 VSSIO_USB_25 VSS_45 AF25 <23,24> KSI6 9 3A 3B 8
C K16 H7 12 11 C
VSSIO_USB_26 VSS_46 <23,24> KSI5 4A 4B
K18 VSSIO_USB_27 VSS_47 AH29
H19 VSSIO_USB_28 VSS_48 V10 +3V_SPI 14 VCC GND 7
VSS_49 P6
N4 1 2 SN74CBT3125PWRG4_TSSOP14
VSS_50
Y4 EFUSE VSS_51 L4
L8 C594 0.1U_0402_16V4Z
VSS_52 FROM@
D8 VSSAN_HWM
M19 VSSXL VSSPL_SYS M20
R1549 ROM@ R1556 @
+3VS 2 1 +3V_SPI +3VALW 2 1 +3V_SPI
P21 VSSIO_PCIECLK_1 VSSIO_PCIECLK_14 H23
P20 H26 0_0402_5% 0_0402_5%
VSSIO_PCIECLK_2 VSSIO_PCIECLK_15
M22 VSSIO_PCIECLK_3 VSSIO_PCIECLK_16 AA21
M24 AA23 +5VALW
VSSIO_PCIECLK_4 VSSIO_PCIECLK_17 +5VALW
M26 VSSIO_PCIECLK_5 VSSIO_PCIECLK_18 AB23
P22 VSSIO_PCIECLK_6 VSSIO_PCIECLK_19 AD23

2
P24 AA26 C436 FROM@
VSSIO_PCIECLK_7 VSSIO_PCIECLK_20 R416 FROM@
P26 VSSIO_PCIECLK_8 VSSIO_PCIECLK_21 AC26 1 2
T20 VSSIO_PCIECLK_9 VSSIO_PCIECLK_22 Y20 10K_0402_5%
T22 W21 0.1U_0402_16V4Z
VSSIO_PCIECLK_10 VSSIO_PCIECLK_23 R420

8
T24 W20 U142A FROM@

1
VSSIO_PCIECLK_11 VSSIO_PCIECLK_24
V20 AE26 1 2 3

P
VSSIO_PCIECLK_12 VSSIO_PCIECLK_25 +5VALW +
J23 VSSIO_PCIECLK_13 VSSIO_PCIECLK_26 L21 O 1
K20 EC_ON 2
VSSIO_PCIECLK_27 100K_0402_5% -

G
1
1 0.1U_0402_16V4Z
21807-A11-HUDSON-M1_FCBGA605 FROM@ R418 FROM@ LM393DG_SO8 C435

4
100K_0402_5% +5VALW
2 +3VALW

2
FROM@
B R419 B
+5VALW FROM@ D6 FROM@
10K_0402_5%
RB715F_SOT323-3

1
U142B D
2

1
5 FROM@ 1 2 Q28 FROM@

P
<23,26,30,33> SUSP# + G AO3416_SOT23-3
R422 2 O 7 3
1 10K_0402_5% S
Net Name Description +5VALW 6

3
-

G
1 +3V_SPI
FROM@ LM393DG_SO8 C434 FROM@

4
2

1
FROM@ 0.1U_0402_16V4Z
R421 R417 FROM@
0 : Bypass internal PLL clock 10K_0402_5%
2
100K_0402_5%
PCI_AD27
1 : Use internal PLL-generated PLL CLK *
1

2
0 : ILA auto run enable
PCI_AD26 @ R334 2.2K_0402_5%
1 : ILA auto run disable * <14> PCI_AD23 2 1

@ R335 2 1 2.2K_0402_5%
<14> PCI_AD24
@ R336 2.2K_0402_5%
0 : Bypass internal FC Clk <14> PCI_AD25 2 1

PCI_AD25 @ R337 2 1 2.2K_0402_5%


<14> PCI_AD26
1 : Use internal PLL FC Clk * NEED CHECK @ R338 2 1 2.2K_0402_5%
<14> PCI_AD27

A 0 : Getting the value from I2C EPROM A

PCI_AD24 NEED CHECK


1 : Disable I2C ROM *
PCI_AD23
0 : Reserved
Security Classification Compal Secret Data Compal Electronics, Inc.
1 : Required setting (use ROMTYPE straps to Issued Date 2009/02/04 2010/02/04 Title
* Deciphered Date
GND
determine the ROM type) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, December 03, 2010 Sheet 17 of 36
5 4 3 2 1
A B C D E F G H

JHDD CONN@
1 GND
SATA_ITX_C_DRX_P0 2
SATA HDD Conn. <13> SATA_ITX_C_DRX_P0
<13> SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_N0 3
A+
A-
4 GND
1 SATA_DTX_C_IRX_N0 C248 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N0 5 1
<13> SATA_DTX_C_IRX_N0 B-
SATA_DTX_C_IRX_P0 C249 1 2 0.01U_0402_16V7K SATA_DTX_IRX_P0 6
<13> SATA_DTX_C_IRX_P0 B+
7 GND

+3VS 8 V33
9 V33
10 V33
+5VS +3VS 11 GND
12 GND
0.1U_0402_16V4Z 10U_0805_10V4Z 13 GND
+5VS 14 V5
1 1 1 1 1 1 15 V5
16 V5
C250 C251 C252 C253 C254 C255 17
1000P_0402_50V7K 0.1U_0402_16V4Z GND
18 Reserved
2 2 2 2 2 2 @
19 GND
20 V12
1U_0603_10V4Z 10U_0805_10V4Z 21 V12
22 V12

SANTA_190501-1_22P

SD,MMC,MS muti-function pin define


2 2
MDIO SD Card MMC Card MS Card
SD_WP/MS_CLK SD_CLK/MSD2 PIN Name PIN Name PIN Name PIN Name
SP1 SP1 SP1

1
R221 R222 SP2
10_0402_5% 10_0402_5% SP3
SD_CLK/MSD2 1 R223 2 0_0402_5% SD_CLK/MSD2_R

2
SD_WP/MS_CLK 1 R224 2 0_0402_5% SD_WP/MS_CLK_R SP4
1 1
C256 C257 SP5
10P_0402_50V8J 10P_0402_50V8J SP6
2 2
SP7
SP8
SP9
SP10
2 1 C258 @ 100P_0402_50V8J U11
R225 1 2 6.19K_0402_1% 1 AV_PLL 20mil (+1.8V internal regulator) SP11
REFE
GPIO0 17
+3VS_CR_VCC
<15> USB20_N2 2 DM SP12
40mil <15> USB20_P2 3 DP CLK_IN 24 CLK_SD_48M <14>
SP13
+3VS 1 R226 2 0_0603_5% 4 3V3_IN XD_D7 23
+VCC_OUT 5 SP14
CARD_3V3 MS_BS
6 V18 SP14 22
1U_0603_10V4Z

1 C260 1 21 SDDAT2 SP15


3 C261 SP13 SDDAT3/MSD1 3
7 XD_CD# SP12 20
C259 19 SP16
4.7U_0805_10V4Z 0.1U_0402_16V4Z SD_WP/MS_CLK SP11 SD_CMD +VCC_3IN1
8 SP1 SP10 18
2 2 MS_INS# MSD0
9 SP2 SP9 16 SP17
SDDAT1 10 15 SD_CLK/MSD2
SP3 SP8
EPAD

SDDAT0 11 14 SP18
MSD3 SP4 SP7 SD_CD# JREAD CONN@
12 SP5 SP6 13
SD_WP/MS_CLK_R 1 SP19
RTS5138-GR_QFN24_4X4 SDDAT1 SD-WP
2
25

SDDAT0 SD-DAT1
3 SD-DAT0
4 SD-GND
5 MS-GND
MS_BS 6
SD_CLK/MSD2_R MS-BS
7 SD-CLK
SDDAT3/MSD1 8
MSD0 MS-DAT1
9 MS-DAT0
10 SD-VCC
C262 SD_CLK/MSD2_R 11
CLK_48M R361 2 CLK_SD_48M MS-DAT2
2 1 1 12 SD-GND
MS_INS# 13
22P_0402_50V8J 0_0402_5% MSD3 MS-INS
14 MS-DAT3
+VCC_3IN1 SD_CMD 15
SD_WP/MS_CLK_R SD-CMD
40mil 16
17
MS-SCLK
+VCC_OUT SDDAT3/MSD1 MS-VCC
1 R229 2 18 SD-DAT3
0_0603_5% 19
SDDAT2 MS-GND
1 1 20 SD-DAT2 GND1 22
SD_CD# 21 23
C263 C265 SD-CD GND2
TAITW_R009-025-LR_NR
0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
HDD Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, December 03, 2010 Sheet 18 of 36
A B C D E F G H
5 4 3 2 1

U12 8105E@ J2
@ JUMP_43X79
1 1 2 2
C266 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_P2 22 31
<6> PCIE_PTX_C_IRX_P2 HSOP LED3/EEDO
LED1/EESK 37
C267 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_N2 23 40 Q16 AP2301GN_SOT23-3
<6> PCIE_PTX_C_IRX_N2 HSON LED0 @
17 30 R230 1 2 10K_0402_5% +3VALW 3 1 1U_0402_6.3V4Z +3V_LAN
<6> PCIE_ITX_C_PRX_P2 HSIP EECS/SCL
18 32 R231 1 2 10K_0402_5%
<6> PCIE_ITX_C_PRX_N2 HSIN EEDI/SDA
1
+3VALW @
R232 1 2 0_0402_5% 16 1 LAN_MDI0+ C268 1 1 @
<15> LAN_CLKREQ0#

2
CLKREQB MDIP0 LAN_MDI0- @C270
@ C270
MDIN0 2 C269 C271

1
LAN_MDI1+ R233 @ 2 @
<14,20,23> PLT_RST_BUF# 25 PERSTB RTL8105E/8111E MDIP1 4 4.7U_0805_10V4Z
5 LAN_MDI1- 0.1U_0402_16V7K 1 2
D MDIN1 LAN_MDI2+ 100K_0402_5% 2 2 D
<14> CLK_PCIE_LAN 19 REFCLK_P MDIP2(NC) 7
20 8 LAN_MDI2-
<14> CLK_PCIE_LAN# REFCLK_N MDIN2(NC) R234 0.01U_0402_25V7K
10 LAN_MDI3+ @

2
MDIP3(NC) LAN_MDI3-
MDIN3(NC) 11 <23> EN_WOL# 1 2
LAN_X1 43 CKXTAL1
R235 @ 10K_0402_5% LAN_X2 47K_0402_5% +3V_LAN
44 CKXTAL2 DVDD10 13 +LAN_VDD10
+3V_LAN 1 2 DVDD10 29
DVDD10 41
28 C272 2 1 0.1U_0402_16V4Z
<15,20> FCH_PCIE_WAKE# LANWAKEB
ISOLATEB 26 27 +3V_LAN C273 2 1 0.1U_0402_16V4Z
ISOLATEB DVDD33
DVDD33 39
C274 2 1 0.1U_0402_16V4Z
8111E@ 14 12 +3V_LAN
R240 1 SMBCLK(NC) AVDD33
2 10K_0402_5% 15 SMBDATA(NC) AVDD33 42 Close to Pin27,39,47 and 48. C275 2 1 0.1U_0402_16V4Z
+3VS 1 2 38 47
+3V_LAN GPO/SMBALERT AVDD33
R236 1K_0402_5% 48 C386 2 1 0.1U_0402_16V4Z
AVDD33 8111E@
ENSWREG 33 ENSWREG
2

EVDD10 21 +LAN_EVDD10
R252 +LAN_VDDREG 34 VDDREG
10K_0402_5% 35 VDDREG AVDD10 3 +LAN_VDD10
@ AVDD10 6
R237 2.49K_0402_1% 9
1

AVDD10 L33 4.7UH_1008HC-472EJFS-A_5%_1008


1 2 46 RSET AVDD10 45
+LAN_REGOUT 1 2 +LAN_VDD10
24 36 +LAN_REGOUT 1 1
LAN_CLKREQ0# GND REGOUT C276
49 GND C277
L6 must be within 200mil to 2
22U_0805_6.3V6M
2
0.1U_0402_16V4Z
RTL8105E-VC-GR_QFN48_6X6
C +3V_LAN RTL8105E RTL8111E
Pin36, C276, C277must be C
+3VS USE SA00003PO00 footprint within 200mil to L6;
06-30 Pin12 NC +3V_LAN +LAN_REGOUT: Width=60mil +LAN_VDD10
1

Pin14 NC NC
R239
R238 0_0402_5% Y2 Pin15 NC 10K ohm PD C278 2 1 0.1U_0402_16V4Z
1K_0402_1% LAN_X1 1 2 LAN_X2
Pin38 1K ohm Pull-high C279 2 1 0.1U_0402_16V4Z
2

ISOLATEB ENSWREG 25MHZ_20PF_7A25000012 C282 2 1 0.1U_0402_16V4Z


1

Close to pin3, pin13, pin 29 C284 2 1 0.1U_0402_16V4Z


R242 R243 @ 1 1
15K_0402_5%
and pin45. C283
0_0402_5% 2 1 0.1U_0402_16V4Z 8111E@
C280 C281
33P_0402_50V8J 33P_0402_50V8J C290 2 1 0.1U_0402_16V4Z 8111E@
2

2 2
C385 2 1 0.1U_0402_16V4Z 8111E@

T27 8105E@ JLAN CONN@

1 24 R282 1 8111E@ 2 0_0402_5% RJ45_MIDI3- 8 R244


LAN_MDI3- TCT1 MCT1 RJ45_MIDI3- PR4-
2 TD1+ MX1+ 23 +LAN_VDD10 1 2 1U_0402_6.3V4Z +LAN_EVDD10
LAN_MDI3+ 3 22 RJ45_MIDI3+ RJ45_MIDI3+ 7 0_0603_5%
TD1- MX1- PR4+
4 21 R283 1 8111E@ 2 0_0402_5% RJ45_MIDI1- 6 1 1
LAN_MDI2- TCT2 MCT2 RJ45_MIDI2- PR2-
5 TD2+ MX2+ 20 Close to Pin 21
LAN_MDI2+ 6 19 RJ45_MIDI2+ RJ45_MIDI2- 5 C285 C286
B TD2- MX2- PR3- B
0.1U_0402_16V4Z
RJ45_MIDI2+ 2 2
7 TCT3 MCT3 18 4 PR3+
LAN_MDI1- 8 17 RJ45_MIDI1-
LAN_MDI1+ TD3+ MX3+ RJ45_MIDI1+ RJ45_MIDI1+
9 TD3- MX3- 16 3 PR2+
10 15 RJ45_MIDI0- 2
LAN_MDI0- TCT4 MCT4 RJ45_MIDI0- PR1- R245
11 TD4+ MX4+ 14
LAN_MDI0+ 12 13 RJ45_MIDI0+ RJ45_MIDI0+ 1 +3V_LAN 1 2 4.7U_0603_6.3V6K +LAN_VDDREG
TD4- MX4- PR1+ 0_0603_5%
SHLD1 9
1 1 1
C289 X'FORM_ NS892404 10 Close to Pin 34 and 35
SHLD2 C291 C292
0.1U_0603_25V7K C287 1000P_0402_50V7K 0.1U_0402_16V4Z
2 RJ45_GND SANTA_130452-C 2 2
2 1 1 2
R1000 75_0402_1%

RJ45_GND 1 2 1000P_1808_3KV7K LANGND


C1000 1 1
C1001 @ C1002 @

0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2 2
For P/N and footprint LANGND
Please place them to ISPD page
3

U12
D32 D33 @ R341 @
AZC199-02S.R7G C/C SOT23 AZC199-02S.R7G C/C SOT23 1 2
0_0603_5%

R358 @
A 8111E 10/100M/1000M 1 2 A
8111E@ 0_0603_5%
1

T27

10/100M/1000M transformer
Security Classification
2009/02/04
Compal Secret Data
2010/02/04 Title
Compal Electronics, Inc.
8111E@
Issued Date Deciphered Date
RTL8105E-VC-GR&RTL8111E-VB-GR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Sheet 19 of 36
5 4 3 2 1
5 4 3 2 1

+3V_WLAN

WLAN&BT 1
R246
2 WLAN_CLKREQ1#
10K_0402_5%
+3V_WLAN

@
R247 0_0805_5% +3VS

+1.5VS
JWLAN CONN@
<15,19> FCH_PCIE_WAKE#
R249 1 2 0_0402_5% WLAN_WAKE# 1 1 2 2
D 3 4 D
3 4
<23> BT_PWR 5 5 6 6
<15> WLAN_CLKREQ1# 7 7 8 8 LPC_FRAME# <14,23>
9 9 10 10 LPC_AD3 <14,23>
<14> CLK_PCIE_WLAN# 11 11 12 12 LPC_AD2 <14,23>
<14> CLK_PCIE_WLAN 13 13 14 14 LPC_AD1 <14,23>
C736 R357 15 15 16 16 LPC_AD0 <14,23>
R251 0_0402_5% 17 18
<14,19,23> PLT_RST_BUF# 17 18
2 1 2 1 CLK_PCI_DB 19 20
<14> CLK_PCI_DB 19 20 WL_OFF# <23>
21 21 22 22 PLT_RST_BUF# <14,19,23>
33P_0402_50V8J 33_0402_5% <6> PCIE_PTX_C_IRX_N3 23 23 24 24
<6> PCIE_PTX_C_IRX_P3 25 25 26 26
@ @ 27 28
27 28 R339 1
29 29 30 30 2 0_0402_5% SMB_FCH_CK1 <15>
31 32 R340 1 2 0_0402_5%
<6> PCIE_ITX_C_PRX_N3 31 32 SMB_FCH_DA1 <15>
R253 <6> PCIE_ITX_C_PRX_P3 33 33 34 34
35 35 36 36 USB20_N7 <15>
1 2 EC_TX_P80_DATA 37 38
37 38 USB20_P7 <15> +3VS
+3V_WLAN 39 39 40 40
100K_0402_5% 41 41 42 42
43 43 44 44
45 45 46 46
47 47 48 48 1
<23> EC_TX_P80_DATA 49 50 C294
49 50
<23> EC_RX_P80_CLK 51 51 52 52 +3V_WLAN
0.1U_0402_16V4Z
2
53 GND1 GND2 54

ACES_88910-5204
+3V_WLAN +1.5VS

C C
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6K
1

C295 C296 C297 C298 C299 C300 C301


47P_0402_50V8J 47P_0402_50V8J
2

@ @

H26
H23 H24 H25 H27 H3 H4 H_6P2
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
H_6P2

1
H_3P0
1

B B

H1
H_3P4
H_3P4 FD1 FD2 FD3 FD4
1

@ @ @ @

1
H7 H8 H9 H10
H_4P5 H_4P5 H_4P5 H_4P5
H_4P5
1

H11
H_3P1N
H_3P1N
1

H20
H_4P1X3P1N

A A
H_4P1X3P1N
1

Security Classification Compal Secret Data Compal Electronics, Inc.


2009/02/04 2010/02/04 Title
Issued Date Deciphered Date
WLAN&BT&SCREW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Sheet 20 of 36
5 4 3 2 1
A B C D E F G H

R255
+PVDD1 0.1U_0402_16V4Z 1 2 0.1U_0402_16V4Z +5VS
0_0603_5%
1 1 1 1
C302 C303 C304 C305

1
J1

1
2 2 10U_0805_10V4Z 2 2
JUMP_43X39
@ 10U_0805_10V4Z

2 2
1 @R256
@ R256 1
+DVDD_IO +PVDD2 1 2 0.1U_0402_16V4Z +5VS
R310 0_0603_5%
+3VS 2 1 0.1U_0402_16V4Z 1 1 1 1
0_0603_5% 1 1 C310 @C307
@ C307 @ C308 C311
C309 0.1U_0402_16V4Z @
C306
R257@
2 2 10U_0805_10V4Z 2 2
+1.5VS 1 2
0_0603_5% 2 10U_0805_10V4Z 2 10U_0805_10V4Z
+3VS_DVDD +AVDD

R259 REAL@
R258 10U_0805_10V4Z 0.1U_0402_16V4Z 1 2 +5VS
+3VS 2 1 0.1U_0402_16V4Z 0_0603_5%
1 1 1 1 1 1
0_0603_5% C312 C319 C314 C315 C316
C313
Place close to chip

39

46

25

38
1

9
2 10U_0805_10V4Z 2 U13 2 2 2 2

DVDD

DVDD_IO

PVDD1

PVDD2

AVDD1

AVDD2
REAL@ 10U_0805_10V4Z 0.1U_0402_16V4Z

R348 1 2 4.7K_0402_5% MIC1_VREFO_R


23 LINE1_L SPK_OUT_L+ 40 SPKL+ <22>
24 41 4.7U_0805_10V4Z
LINE1_R SPK_OUT_L- SPKL- <22>
MIC1_R_C C317 1 2 MIC1_R_R R346 1 2 1K_0402_1% MIC1_R <25>
14 LINE2_L SPK_OUT_R+ 45 SPKR+ <22>
+3VS 15 44 MIC1_L_C C318 1 2 MIC1_L_R R347 1 2 1K_0402_1%
LINE2_R SPK_OUT_R- SPKR- <22> MIC1_L <25>
C558 @1 2 MIC1_L_C 21 32 R261 1 2 75_0402_1% 4.7U_0805_10V4Z
MIC1_L HP_OUT_L HP_L <25>
MIC1_R_C 22 33 R262 1 2 75_0402_1%
2 MIC1_R HP_OUT_R HP_R <25> 2
R349 1 2 4.7K_0402_5% MIC1_VREFO_L
0.1U_0402_16V4Z
5

U26 @ MIC2_L_C 16
HDA_RST# MIC2_R_C MIC2_L 4.7U_0805_10V4Z
1 17
P

IN1 PD# MIC2_R MIC2_L_C C430 MIC2_L_R R350 1


O 4 SYNC 10 HDA_SYNC <15> 1 2 2 1K_0402_1%
<23> EC_MUTE# 2 IN2
G

2 6 MIC2_R_C C429 1 2 MIC2_R_R R351 1 2 1K_0402_1%


GPIO0/DMIC_DATA BCLK HDA_BITCLK <15> INT_MIC <22>
SN74AHC1G08DCKR_SC70-5 R353 1 2 0_0402_5% 1 2
3

3 C735 22P_0402_50V8J 4.7U_0805_10V4Z


GPIO1/DMIC_CLK
SDATA_OUT 5 HDA_SDOUT <15>
R355 1 2 0_0402_5% R352 1 2 4.7K_0402_5% MIC2_VREFO
PD# 4 8 R265 1 2 33_0402_5%
PD# SDATA_IN HDA_SDIN0 <15>

11 47 R266 1 2 0_0402_5%
<15> HDA_RST# RESET# EAPD EAPD <23>
@ 48 For P/N and footprint
C322 MONO_IN SPDIFO
1 2 100P_0402_50V8J 12 PCBEEP Please place them to ISPD page
MONO_OUT 20
U13 VIA@
SENSE_A 13 SENSE A
MIC2_VREFO 29 MIC2_VREFO
18 SENSE B
30 REAL@
MIC1_VREFO_R MIC1_VREFO_R
C323 1 2 2.2U_0603_6.3V4Z 36 28 2 1 C324
CBP LDO_CAP S IC VT1802P QFN 48P CODEC
35 27 0.1U_0402_16V4Z 10U_0805_10V4Z
CBN VREF

MIC1_VREFO_L 31 19 R267 1 REAL@ 2 20K_0402_1% 1 2 R267 VIA@


MIC1_VREFO_L JDREF C326
43 34 C325 1 2 2.2U_0603_6.3V4Z C327
PVSS2 CPVEE
42 PVSS1 2.2U_0603_6.3V4Z
2 1
49 DVSS2 AVSS1 26
3 7 37 3
DVSS1 AVSS2 5.1K_0402_1%
ALC259-GR_QFN48_7X7

R269 1 SENSE_A
USE SA00003QR00 footprint
<25> HP_PLUG# 2 39.2K_0402_1%

R268 1 2 20K_0402_1%
<25> MIC_PLUG#

R260 1 2 47K_0402_5%
<23> EC_BEEP#
Sense Pin Impredance Codec Signals Function R280 2 1 0_0603_5%
C320
39.2K PORT-I (PIN 32,33) Headphone out R286 2 1 0_0603_5% R263 1 2 47K_0402_5% 1 2 MONO_IN
<15> FCH_SPK

R270 0.1U_0402_16V4Z
20K PORT-I (PIN 21,22) EXT.MIC 2 1 0_0603_5%

1
SENSE A 2
R264
10K @C331
@ C331 1 2 0.1U_0603_50V7K 10K_0402_5% C321
0.1U_0402_16V4Z
1

2
5.1K

39.2K
4 4

SENSE B 20K

10K

5.1K
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
ALC259-GR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, December 03, 2010 Sheet 21 of 36
A B C D E F G H
A B C D E

R342 PACDN042Y3R_SOT23-3
SPKL+ 1 2 0_0603_5% 10U_0805_10V4Z SPK_L1
<21> SPKL+
1 2
1
@ C332 3
1 1
2
1 @ D16
@
C333
1U_0402_6.3V4Z
@1 2
C334 ACES_87213-0400G
R343 SPK_L1 1
SPKL- 2 10U_0805_10V4Z SPK_L2 SPK_L2 1
<21> SPKL- 1 2 0_0603_5% 2 2
SPK_R1 3
SPK_R2 3 GND 5
4 4 GND 6
JSPK CONN@

R344 PACDN042Y3R_SOT23-3
SPKR+ 1 2 0_0603_5% 10U_0805_10V4Z SPK_R1
<21> SPKR+
1 2
1
@ C335 3
2
1 @ D17
@
C336
1U_0402_6.3V4Z
@1 2
C337
R345
SPKR- 2 10U_0805_10V4Z SPK_R2
<21> SPKR- 1 2 0_0603_5%

2 2

1
D18
PACDN042Y3R_SOT23-3
@

3
MIC1 45@
<21> INT_MIC 1 1
2 2
WM-64PCY_2

use CYWM64P0110 footprint

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/05/06 Deciphered Date Title
MIC & Speaker
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCM10 LA6741 M/B SCHEMATIC
Date: Friday, December 03, 2010 Sheet 22 of 36
A B C D E
5 4 3 2 1

Board ID / SKU ID Table for AD channel


+3VALW +EC_DVCC +EC_AVCC
Vcc 3.3V
FBM-11-160808-601-T_0603 Ra
R354 0_0805_5% 1 2
100K_5%
L40
C342
2 Board ID Rb / Rd VAD_BRD min VAD_BRD typ VAD_BRD max
1 1 1 1 1 1 0 0 0V 0V 0V

0.1U_0402_16V4Z
C348

0.1U_0402_16V4Z
C344

0.1U_0402_16V4Z
C345

0.1U_0402_16V4Z
C349

1000P_0402_50V7K
C346

1000P_0402_50V7K
C347
0.1U_0402_16V4Z
1
1 8.2K_5% 0.216V 0.250V 0.289V
2 2 2 2 2 2

ECAGND
2 18K_5% 0.436V 0.503V 0.538V
D 3 33K_5% 0.712V 0.819V 0.875V D

111
125
22
33
96

67
4 56K_5% 1.036V 1.185V 1.264V

9
U14
5 100K_5% 1.453V 1.650V 1.759V

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
1 2
R277 0_0402_5%
6 200K_5% 1.935V 2.200V 2.341V
GATEA20
KB_RST#
<15> GATEA20 1 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F 21
EC_BEEP# 7 NC 2.500V 3.300V 3.300V
<15> KB_RST# 2 1 2 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 23 EC_BEEP# <21>
D20 @ <14> SERIRQ SERIRQ 3 26
RB751V-40_SOD323-2 LPC_FRAME# SERIRQ# FANPWM1/GPIO12
<14,20> LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF <28>
<14,20> LPC_AD3 LPC_AD3 5
C350 LPC_AD2 LAD3 C352 1 ECAGND
<14,20> LPC_AD2 7 LAD2 PWM Output 2
2 1 1 2 <14,20> LPC_AD1 LPC_AD1 8 63 0.01U_0402_16V7K
LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <27>
R275 0_0402_5% LPC_AD0
22P_0402_50V8J
<14,20> LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
ADP_I/AD2/GPIO3A 65 ADP_I <28>
CLK_PCI_EC 12 AD Input 66 +3VALW
<14> CLK_PCI_EC PCICLK AD3/GPIO3B
<14,19,20> PLT_RST_BUF# 13 PCIRST#/GPIO05 AD4/GPIO42 75
R276 1 2 EC_RST# 37 76 MB_ID
+3VALW ECRST# SELIO2#/AD5/GPIO43

1
47K_0402_5%
<15> EC_SCI#
EC_SCI# 20 SCI#/GPIO0E R278
MB_ID
1 38 CLKRUN#/GPIO1D
C351 68 Ra 100K_0402_5%

0.1U_0402_16V4Z
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D 70 EN_FAN1
IREF
EN_FAN1 <5> EVT 0
DA Output 71 IREF <28>

2
2 KSI0 IREF/DA2/GPIO3E CHGVADJ MB_ID
55 72 CHGVADJ <28>
KSI1 56
KSI0/GPIO30
KSI1/GPIO31
DA3/GPIO3F
DVT 1

1
KSO[0..15] KSI2

0.1U_0402_16V4Z
<24> KSO[0..15] 57 KSI2/GPIO32 1
KSI3 58 83 EC_MUTE# C353 R279
EC_MUTE# <21>
<17,24> KSI[0..7]
KSI[0..7] KSI4
KSI5
59
60
KSI3/GPIO33
KSI4/GPIO34
PSCLK1/GPIO4A
PSDAT1/GPIO4B 84
85
USB2_ON
BT_PWR
USB2_ON <25>
@ Rb 33K_0402_5% PVT 2
KSI5/GPIO35 PSCLK2/GPIO4C BT_PWR <20> 2
KSI6 61 PS2 Interface 86 APU_PROCHOT_EC
APU_PROCHOT_EC# <5>

2
C
KSI7
KSO0
62
39
KSI6/GPIO36
KSI7/GPIO37
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E 87
88
TP_CLK
TP_DATA
TP_CLK <24> PreMP 3 C
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <24>
+3VALW KSO1 40
KSO2 KSO1/GPIO21
41 KSO2/GPIO22
KSO3 42 97
KSO3/GPIO23 SDICS#/GPXOA00 VGATE <15,34>
1 2 KSO1 KSO4 43 98 EN_WOL#
KSO4/GPIO24 SDICLK/GPXOA01 EN_WOL# <19>
R284 47K_0402_5% KSO5 +1.1VS_ON
+3VALW KSO2 KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW#
+1.1VS_ON <26>
+3VALW
1 2 45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW# <24>
R285 47K_0402_5% KSO7 46 SPI Device Interface
KSO8 KSO7/GPIO27
47 KSO8/GPIO28
KSO9 48 119 FRD#SPI_SO LID_SW# R118 1 2 100K_0402_5%
KSO9/GPIO29 SPIDI/RD# FRD#SPI_SO <24>
1 2 EC_SMB_CK1 KSO10 49 120 FWR#SPI_SI
R287 2.2K_0402_5% KSO11 KSO10/GPIO2A SPIDO/WR# SPI_CLK
50 KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126
+5VS
1 2 EC_SMB_DA1 KSO12 51 128 FSEL#SPICS#
R288 2.2K_0402_5% KSO13 KSO12/GPIO2C SPICS#
52 KSO13/GPIO2D
KSO14 53 TP_CLK R291 1 2 4.7K_0402_5%
+3VS KSO15 KSO14/GPIO2E
54 KSO15/GPIO2F CIR_RX/GPIO40 73
81 74 TP_DATA R292 1 2 4.7K_0402_5%
EC_SMB_CK2 KSO16/GPIO48 CIR_RLC_TX/GPIO41 FSTCHG
1 2 82 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 89 FSTCHG <28>
R289 2.2K_0402_5% 90 BATT_FULL_LED# C358
BATT_CHGI_LED#/GPIO52 BATT_FULL_LED# <24>
1 2 EC_SMB_DA2 91 CAPS_LED# SUSP# @ 1 2 100P_0402_50V8J
CAPS_LED#/GPIO53 CAPS_LED# <25>
R290 2.2K_0402_5% 1 1 77 GPIO BATT_LOW_LED#/GPIO54 92 CHARGE_LOW_LED#
<27> EC_SMB_CK1 SCL1/GPIO44 CHARGE_LOW_LED# <24>
C356 C357 <27> EC_SMB_DA1 78 93 PWR_ON_LED#
SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_ON_LED# <24>
@ @ <5> EC_SMB_CK2 79 SM Bus 95 SYSON C359
SCL2/GPIO46 SYSON/GPIO56 SYSON <31>
100P_0402_50V8J 100P_0402_50V8J <5> EC_SMB_DA2 80 121 VR_ON_EC BATT_TEMP @ 1 2 100P_0402_50V8J
2 2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON_EC <34>
127 ACIN_D
AC_IN/GPIO59 C360
+3VALW FSTCHG @ 1 2 100P_0402_50V8J
FCH_SLP_S3# 6 100 EC_RSMRST#
<15> FCH_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <15>
FCH_SLP_S5# 14 101 EC_LID_OUT#
<15> FCH_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <15>

1
EC_SMI# 15 102 EC_ON
<15> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <17,24,29>