Académique Documents
Professionnel Documents
Culture Documents
Professor
Department of Electrical Engineering
The Maharaja Sayajirao University of Baroda
Vadodara
Gujarat
© Oxford University Press. All rights reserved.
Contents
Preface v
1. Evolution of Microcontrollers 1
1.1 Digital System Organization 2
1.1.1 Microprocessor-based System 4
1.1.2 Three-bus Structure 4
1.2 Interfacing Other Logic Families 5
1.2.1 Interfacing TTL, CMOS Families 5
1.2.2 Interfacing TTL, ECL Families 6
1.3 Microcontroller Architectures 6
1.3.1 Von Neumann Architecture 6
1.3.2 Harvard Architecture 6
1.3.3 CISC and RISC Architecture 7
1.4 Data Transfer Schemes 7
1.4.1 Programmed I/O 8
1.4.2 Interrupt Driven I/O 11
1.4.3 Direct Memory Access 14
1.5 Microcontroller-based Systems 15
1.5.1 Factors Affecting Selection 16
2. Introduction to Microcontroller Families 18
2.1 Packaging Information 19
2.2 Microcontroller Families 20
2.3 The Preceders 22
2.4 X51 Family 22
2.4.1 Basic Building Blocks of X51 23
2.4.2 8051 Hardware Overview 25
2.4.3 Architecture 26
2.4.4 Memory Organization 27
2.4.5 Special Function Registers 29
2.4.6 I/O Ports 34
2.4.7 Accessing External Memory 34
2.4.8 Timers/Counters 35
2.4.9 Serial Port Interface 37
2.4.10 Interrupt Structure 40
2.4.11 Enhanced Architecture 42
The processor controls the operation of the entire system via control program
stored in its read only memory abbreviated as ROM. It is essential to be able to
change the ROM program to perform different functions for different applications.
Each line of ROM contents specifies the control signals of the system in coded
form. A hierarchical approach called stored-program control has been developed.
Stored-program control In a stored-program system, the ROM within the
processor contains a standardized program used for all applications. The standard
program in ROM sequences all the control signals to perform the specified
operation. Data movement, arithmetic, Boolean functions, and data shifting are
commonly implemented operations. The programmer’s instructions stored in
the memory subsystem are responsible for a complex sequence of actions to be
performed. The system can be applied to solve many problems by changing the
instruction sequence. Microcomputers are advantageous as they reduce the
development cost of complex digital systems.
Microcomputer operation A microcomputer is a computer that uses a micro-
processor as its CPU. A microprocessor requires external memory to execute
programs and it cannot interact directly with the I/O devices. To add memory
components and I/O devices to a microprocessor-based design, a bus is employed.
A bus is defined as a collection of electronic signals and signal paths that are grouped
together according to the function performed by them. It can be unidirectional or
bidirectional depending on whether the information flows in one direction or
both directions. Hence, it can be said that the signals in a specified bus have a
common function.
A memory subsystem is connected with a single processor. The addresses
are sent to the memory from the processor via address bus. So the address bus
is unidirectional.
Data may be sent from the processor to the memory or from the memory to
the processor. The data signal thus flows in both directions on data bus, which
requires that it must be bidirectional.
Instructions are also transferred on the data bus from the memory to the pro-
cessor. This simple processor system consists of two major parts: the accumulator
and the arithmetic logic unit (ALU), which manipulate data transferred between
processor and memory via the data bus. The rest of the processor sequences the
operation of the instructions stored in the memory system’s ROM.
The program counter register (PC) provides the address of the instruction to
be performed. The IR or instruction register holds the instruction after it is
extracted from memory. The control unit sequences all the control signals needed
to perform these operations and those signals needed to perform the data
operations specified by the instructions in the IR. The control unit also provides
memory control signals. An I/O subsystem may be connected with I/O control
signals from the processor’s control unit.
Address bus
Data bus
Processor
Input Output Memory
device device units
Control bus
The three-bus structure (Fig. 1.1) contains three buses: data bus, address bus,
and the control bus. They are named based on the signals they carry.
Data bus It provides a physical path for communication of data to be transferred.
The signal is required to flow in both directions, hence it is bidirectional.
Address bus It outputs the address to enable correct path for communication.
The information is given by the processor, hence address bus is unidirectional.
Control bus It provides signals to start and terminate the specified operation.
of the next instruction and execution of the current instruction are done simul-
taneously. Executing this instruction in the Harvard architecture also takes place
over two instructions, but the instruction read takes place while the previous
instruction is being carried out. This allows the instruction to be executed in
one instruction cycle.
Address Decoding
In order to impart or generate an address for the port, two most popular techniques
are:
1. Memory-mapped I/O
2. I/O-mapped I/O
In the former method all the 16 address lines are used to generate unique
port address, while only lower order address bus is used in case of I/O-mapped
I/O scheme. In case of microprocessors, to reduce the hardware of the address
decoding circuits, I/O-mapped I/O scheme is used. In the instruction set for
microprocessors, there are special instructions called I/O group of instructions
to support I/O-mapped I/O scheme. However, microcontrollers do not have
specific I/O instruction, the former scheme is used.
In memory-mapped I/O, an I/O device is considered as a memory location
in the address space. Hence, it can be accessed by normal memory reference
instructions. This eliminates the need of special instructions for data transfer
from I/O devices.
The advantages of memory-mapped I/O scheme are as follows:
1. Since all the address lines are used, there is no chance of multiple addresses
for the device. This relieves system programmer from the fear of multiple
device selection.
2. Even though the decoding logic is complex, due to a large number of address
lines being used more I/O devices can be connected. Theoretically, it can
be as large as (216).
3. Data transfer can take place between memory and any register or internal
memory location.
The task of the address decoder is to decode the address bits and generate
address select signals for each device in the system. In effect, it breaks the address
space of processor into the blocks. Each address select signal indicates that the
address on the address bus is within a predetermined range.
The decoding can be done using any one of the following methods:
1. Linear decoding The method is very simple. It uses one address line for one
device for selecting port address. The drawback of this scheme is that there
may be multiple addresses for the same device.
2. Absolute decoding It uses all the address lines. But in order to generate a
unique port, address for the device gates/decoders/programmable ROM
(PROM)/programmable logic arrays (PLA)/programmable array logics
(PAL), etc. are used.
It is a low power schottky version of TTL logic family. It has three enable
inputs denoted as:
1. Two active-low (G2A and G2B)
2. One active-high (G1)
In order to function as an address decoder, the IC must be enabled first by
applying appropriate signals. This can be done by pulling inputs (G2A and G2B)
logically low and (G1) made high. Otherwise all the outputs of decoder will be
high.
All the outputs are active-low, so the selected output is low and all other are
high. The address decoder has three inputs, called address inputs. The combination
of the address inputs will select any one of eight outputs low, while others are
kept high.
Using PROM
This technique uses a specially programmed bipolar PROM as the address decoder.
PROM is available with either open-collector or three-state outputs. The three-
state versions are preferable, since their low-to-high transitions are much faster
and output pull-up resistors are not required. Since the PROMs outputs are in
the high-impedance state when chip select is negated, pull-up resistors are
required even on the output. Commonly used bipolar PROMs are MMI 63S141,
AMD 27S21, and 74S287 from the National Semiconductors.
Figure 1.3 shows a typical (256 ´ 4) PROM used as an address decoder. Address
bits A15…A10 select one of 64 locations in the PROM. Address bits [A0 ... A9]
from the microcontroller are ignored by the PROM, so each PROM location is
accessed for a range of 1 K addresses. Table 1.1 shows an example of PROM
programming
256 ¥ 4 PROM
Jumpers to
select address
mapping (optional)
Fig. 1.3 PROM decoder
The first memory location is programmed with 1110; this makes only D0 output
low, when this location is accessed. Since this is the only memory location with
a zero in the D0 bit position, the D0 output is asserted for a range of 1 K addresses.
If some range of addresses are unused the contents of PROM locations may be
made all HIGH, so it will not select any device. The range of address can be
easily extended by programming more PROM locations.
Vectored Interrupts
This is a simple method used for resolving the multiple interrupts. Each of the
interrupt pin on the processor corresponds to a fixed IBA in the processor’s memory
address space. This technique is called vectored interrupts. In this, the processor
does not require any identification procedure for the interrupting device and the
service required by the device. On getting a request from the device, the processor
jumps to the specified IBA and executes the appropriate interrupt service routine,
which specifies the operation to be performed by the processor to handle the
device request.
In most of the processors the problem of handling multiple interrupts is solved
by allocating priorities to the interrupt pins. Normally a priority is fixed for
each pin on the processor. In case of multiple requests, the device connected to
the interrupt pin, having the highest priority, will be entertained first. This is
due to the inbuilt hardware support in the processor interrupt structure.
Polled Interrupts
This method can even be used to expand the interrupt handling capacity of the
interrupt pins. This allows more than one device to be connected to the same
interrupt pin.
This method makes use of device polling. The interrupt locating subroutine,
(ILS) resides in the memory and asks each device whether it has interrupted or
not. If the device has interrupted, processor will invoke appropriate ISS, execute
and return to normal operation, otherwise the processor polls another device.
In the case of more than one device interrupt, priority will be the sequence in
which, ILS scans the devices for the interrupt identification. There are two
methods of polling the interrupts depending upon, whether the interrupt pin to
which more than one device are connected, is a vectored or non-vectored one.
They are software polling and hardware polling.
Software polling The interrupt locating subroutine ILS is implemented using
a program code/software. Typical feature of this interrupt is that all the interrupts
are combined using an OR gate and output of the gate is connected to the vectored
pin of the processor. Polling process begins on getting the device request, with
the status flag checking according to the routine written.
Figure 1.4 depicts the polling scheme. The device interrupt status is connected
to a data bus in tristate. The enable line of the buffer is connected to one of the
output of a decoder and it is ANDed with device select lines. When the processor
gets an interrupt request, it sends an appropriate address on bus and one of the
bits is transferred generating a control signal for decoder. The output of the decoder
is ANDed with strobe input, which READS the signal sent by the processor and
is used for enabling output buffer.
Data bus
C C
STB
Buffer Buffer
Latch
Latch
En En
D
D
Device Device
Q Q
Device Device
select select
(INTx) pin
–+
of controller
Fig. 1.4 Software polling
After reading the status, it checks whether status is at logic level ‘1’ or not. If
it is ‘1’, it jumps to interrupt service routine (ISR) otherwise continues polling.
Polling stops after each device has been scanned. For proper operation the
interrupt status of the device, which has transferred the data needs to be reset.
The reset output may be at the (logic HIGH/LOW) depending upon the software
convenience. In later chapters, we will study how to implement this scheme for
microcontrollers.
Hardware polling Figure 1.5 depicts configuration of setup employing
hardware polling. It is also known as a daisy chain. The priority of the devices
connected is determined by the location of the device in the hardware layout.
The device nearest to the CPU will have the highest priority.
The basic assumptions in this scheme are as follows:
1. All the devices are connected to same non-vectored interrupt pin.
2. Acknowledge signal is issued in the beginning of next machine cycle.
3. During this interval the processor will receive instructions from the device
and not from the memory.
It is possible to use an acknowledge pin, in case of processors, which generates
INTA signal. Microcontrollers do not have provision for INTA pin, this technique
cannot be used directly. However, it is possible to generate INTA signal and
make it available on any one of the port pin of the microcontroller by writing a
program.
Device 0 Device 7
En INT En INT
CPU
INTA
C
INTR +
DMA
RESET flag
To ready
pin of
processor
(Interface for DMA)
(CPU)
(IMA add) (DMA)
Add Reg
Memory (DMA)
Data Reg
DMA
(Data)
1. Speed requirement
2. Time-critical functions
3. Arithmetic operations
4. Memory requirements: ROM, RAM
5. Input/output requirements
6. Data transfer scheme
7. Power requirement
EXERCISES
1.1 What are the three blocks of a processing unit? 1.11 What is a programmed I/O? State the advan-
Explain functions of each block. tages of this scheme over interrupt driven I/O?
1.2 What is a stored program control? What are 1.12 Define the terms: PORT and PORT address.
the advantages of it? 1.13 What does address decoding mean? What is
1.3 What is the need of control signals? its need?
1.4 Explain the operation of a microcontroller 1.14 Explain the address decoding schemes used
system. in design of microcontroller-based system?
1.5 What is another name for an architecture? 1.15 What do you mean by an interrupt?
1.6 State merits and demerits of a three-bus 1.16 State the advantages of interrupt driven data
architecture. transfer scheme.
1.17 Define multiple interrupts. Explain various
1.7 What do you understand by bus loading? How
methods used to handle multiple interrupts.
they can be eliminated?
1.18 Define polled interrupts.
1.8 Why is a combination of CISC and RISC pre-
1.19 State the characteristics to be considered for
ferred in microcontrollers?
designing a microcontroller-based system.
1.9 Explain different data transfer schemes used
1.20 How can the software for the microcontroller-
in a digital system.
based system be developed? State important
1.10 Why is DMA not used in microcontroller- factors affecting the choice.
based systems?