National University of Computer & Emerging Sciences (FAST-NU)

Final Report
MIPS Simple Pipeline Simulator

Prepared by

Muhammad Safi 15K-2143

Rawaha Bin Khalid 15K-2879

Zeeshan Mustafa 15K-3638

Submitted to

Dr. Hasina Khatoon

Ms. Safia Baloch

Project details
Introduction:
MIPS (an acronym for Microprocessor without Interlocked Pipeline Stages) is a
reduced instruction set computer (RISC) instruction set architecture (ISA) developed by
MIPS Technologies (formerly MIPS Computer Systems). The MIPS is a RISC architecture
and corresponding assembly language use a limited number of instruction formats. Thirty-
two general-purpose registers are available for integer operations (some have dedicated uses),
as are thirty-two single-precision floating point registers. MIPS-32 is a clean design with
simple instructions. Since computer science and computer engineering departments may not
have adequate access to MIPS equipment to support laboratory activities, software-based
MIPS simulators may be used. MIPS simulator is designed as an alternative to SPIM
specifically for the needs of typical undergraduate students and their instructors. It should be
useful in courses such as computer organization and architecture, assembly language
programming, and compiler writing.

SPECS OF THE MIPS Pipeline:

Our work

We have implemented MIPS Simple Pipeline in which there are five stages IF (Instruction
fetch from memory), ID (Instruction decode & register read), EX (Execute operation or
calculate address), MEM (Access memory operand) and WB (Write result back to register).

1. Instruction Fetch

» Get the next instruction from memory

» Increment Program Counter value by 4

2. Instruction Decode

» Figure out what the instruction says to do

» Get values from the named registers

» Simple instruction format means we know which registers we may need before the
instruction is fully decoded

3. Execute

» On a memory reference, add up base and offset

 » On an arithmetic instruction, do the math

4. Memory Access

» If load or store, access memory

» If branch, replace PC with destination address

» Otherwise do nothing

5. Write back

» Place the results in the appropriate register

Total effort done in no. of hours

We worked almost 12 and a half days to come up with this implementation. As the code show
our efforts. We have put out the best effort to accomplish our task.

Results achieved

Pipelined Execution of given MIPS ISA Instructions is achieved with value of registers of
last 3 instructions.

Concluding/ closing remarks

Since we have designed our own interpreter to interpret the MIPS ISA Instructions, haven’t
implemented all of the instructions but major ones.

REFERENCES:

John L. Hennessy, David A. Patterson _ Computer Architecture, Fifth Edition: A Quantitative

Approach 5th Edition, Morgan Kaufmann Publishers Inc. San Francisco, CA, USA ©2011

ISBN:012383872X 9780123838728

https://www.scss.tcd.ie/~jones/vivio/dlx/dlxtutorial.htm

www.cs.cornell.edu/courses/cs3410/2012sp/project/pa1.html

https://www.ijircce.com/upload/2017/ncspcn/21_I7.pdf

https://www.cs.cmu.edu/afs/cs/academic/class/15740-f97/public/info/pipeline-slide.pdf

http://eecs.oregonstate.edu/research/vlsi/teaching/ECE472_FA12/chapter4_pipelining_END_
FA11.pdf