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2 -1
MOSFET Technologies
SOURCE SOURCE SOURCE
MOSFET Model
D D D
G G G
S S S
(a) (b) (c)
Fig.2.
2 -2
Critical Parameters
• CGS - overlap of the source and channel region by the gate
electrode.
• CGD - overlap of the JFET silicon region by the gate
electrode and the capacitance of the depletion region.
• CDS - capacitance of the body diode.
• RG,I - material resistance in the gate signal distribution
(gate mesh resistance), polysilicon gate R > metal gate R
• VTH - measured at 250uA, and 25C, (-7mV/C)
• gfs - transconductance, active (linear) state, gfs=dID/dVGS
• LS - source inductance, inside the package
• LD - drain inductance, inside the package
• Other circuit components: LLK, RSNS, RGATE, Driver’s
output impedance (RHI, RLO, RDRV)
Switch-Mode Applications
• Switch between lowest and highest resistance states of the
MOSFET in the shortest possible time. (reduce switching
losses)
• Switching performance of a MOSFET is determined by the
time required to establish voltage changes across
capacitances. (Charge carriers can travel across the channel
in 20ps to 200ps depending on the size of the cells.)
• Achieve the lowest possible RDSON within the limitations
of the device. (reduce conduction loss)
2 -3
Clamped Inductive Switching
• Simple schematic is valid for all
IDC power conversion topologies to
model switching operation.
RGATE
• Turn-off speed is inversely
proportional to the gate current of
VDRV VOUT the device.
• Turn-on speed is limited by the
switching characteristic of the
clamp diode (rectifier element).
• Because of the fundamental nature
of the diode operation, the switch
ends up with most of the switching
losses.
Fig.3.
Turn-On Procedure
Step 1.
Vgs
Charge CGS to the threshold level.
Vth
Ig VDRV
D
LD
CGD
Ids S
Fig.4.(a)
2 -4
Turn-On Procedure
Step 2.
Vgs
Charge CGS from VTH to VGS,MIN
Vth required to carry ID. (linear region)
VDRV
Ig
ID
D
LD
CGD
S
Ids
Fig.4.(b)
Turn-On Procedure
Step 3.
Vgs
Discharge CGD and CDS
Vth as VDS falls close to GND.
VDRV
Ig
ID
D
LD
IG CGD
RHI RGATE RG,I
Vds
G CDS
CGS
LS
S
Ids
Fig.4.(c)
2 -5
Turn-On Procedure
Step 4.
Vgs
Apply overdrive by charging CISS to the
Vth
final gate voltage.
VDRV
Ig
ID
D
LD
CGD
RHI RGATE RG,I
Vds
G CDS
IG
CGS
LS
S
Ids
Fig.4.(d)
Turn-Off Procedure
Step 1.
Vgs
Discharge CISS from the final gate voltage
Vth
to VGS,MIN required to carry ID.
VDRV
Ig
ID
D
LD
CGD
RLO RGATE RG,I
Vds
G CDS
IG
CGS
LS
S
Ids
Fig.5.(a)
2 -6
Turn-Off Procedure
Step 2.
Vgs
Charge CGD and CDS as VDS rises to the
Vth
final turn-off voltage.
VDRV
Ig
ID
D
LD
IG CGD
RLO RGATE RG,I
Vds
G CDS
CGS
LS
S
Ids
Fig.5.(b)
Turn-Off Procedure
Step 3.
Vgs
Discharge CGS from VGS to VTH to turn-
Vth
off the channel. (linear region)
VDRV
Ig
ID
D
LD
CGD
RLO RGATE RG,I
Vds
G CDS
IG
CGS
LS
S
Ids
Fig.5.(c)
2 -7
Turn-Off Procedure
Step 4.
Vgs
Discharge CGS to GND.
Vth
VDRV
Ig
D
LD
CGD
RLO RGATE RG,I
Vds
G CDS
IG
CGS
LS
S
Ids
Fig.5.(d)
IL LD+LLK
LLK CGD (LDL)
2x DIDEAL RHI RHI+RGATE+RG,I
DUT VO VDRV
(RGON) CDS
RGATE
RLO RSNS
VDRV
CGS
LS
2 -8
Gate Drive Power Losses
Vgs, Gate-to-Source Voltage (V) • Gate drive losses accrue during the entire gate
charge / discharge cycles.
VDRV
• Power loss is independent from how quickly
the charge is delivered.
VDS
• Gate charge curves give relatively accurate
worst case estimate.
QG
PGATE = Q G ⋅ VDRV ⋅ f DRV I AVE = Q G ⋅ f DRV
Qg, Total Gate Charge (nC)
VBIAS IAVE
• The equations give the average VDRV
current and the power drawn from L∞
CDRV
the bias circuitry but does not give
you the actual power dissipation in RHI RGATE RG,I
the driver!
1 R HI ⋅ Q G ⋅ VDRV ⋅ f DRV
PDRV,ON = ⋅
2 R HI + R GATE + R G,I
Fig.6.
Fig.7.
2 -9
Direct Gate Drive
V (V )
• Optimizing the layout is DRV BIAS
difficult
VCC
• PWM controllers have limited PWM
drive currents controller RGATE
• High current spikes disrupt OUT
analog circuits
• Power dissipation in PWM
GND
controller
• Series inductance(s) reduces distance!
switching speed, causes ringing. • Ground plane eliminates only
• Bipolar output stage needs half of the loop inductance!
protection against reverse • Low forward voltage drop
currents occurring during Schottky diodes must be placed
oscillations in the gate loop. very close to the IC pins and to
the HF bypass capacitor.
2 - 10
Gate Driver Totem-Poles
VBIAS VDRV VBIAS VDRV
R R
VCC VCC
PWM PWM
controller RGATE controller RGATE
OUT OUT
RB
GND GND
distance! distance!
D OFF
• Works when:
GND VD,FW
IG >
R GATE
Fig.12.
2 - 11
Turn-Off Circuits
VDRV VDRV
QINV
GND GND
• Most popular circuit for fast turn-off. • Self biasing mechanism holds
It is a simplified totem-pole! MOSFET off during power up.
• Reduces the effect of driver output • Inversion is needed to drive the
impedance, external gate resistor discharge transistor.
• Shunts, gate drive loop inductance, • QINV draws current during ON
current sense resistor. state, helps protect the driver
• Halves driver’s total power dissipation. against reverse current.
• QOFF never saturates • Holds gate closer to GND than its
• QOFF clamps gate at turn-on. PNP counterpart.
dv/dt Protection
dv I V − 0.007 ⋅ (TJ − 25) • Capacitive divider of CGD and CGS
= G = TH provides some protection at very low
dt C GD R EFF ⋅ C GD
VDRV
voltages.
• Start-up dv/dt protection
VCC
• MOSFET has a natural dv/dt limit based
Driver
RGATE on RG,I and CGD.
OUT
• Actual dv/dt limit depends on the gate
RLO
drive circuit.
GND
• Examples: Typical values:
dv VTH, MIN 2V V
= = = 1000
VDRV
dt (R G,I + R GATE + R LO ) ⋅ CGD (1Ω + 5Ω + 4Ω) ⋅ 200pF µs
VCC
DON
Driver
RGATE dv VTH, MIN − VBE 2V − 0.7 V V
= = = 5963
dt (R + R GATE + R LO ) ⋅ C 5Ω + 4Ω
OUT QOFF
(1Ω + ) ⋅ 200pF µs
G, I GD
RLO β 100
GND
2 - 12
Driving Synchronous Rectifiers
QFW
V IL
QSR
Fig.16.
Fig.17.
2 - 13
High Side Driver Applications
Device Type: Design checklist:
• P-Channel MOSFET • Power requirements (efficiency
• N-Channel MOSFET of the drive circuit)
Driver Type: • Bias requirements
• Speed limitations
• Direct drive (low voltage)
ground referenced • Maximum duty-cycle limitation
• Level shifted drive schemes • dv/dt implications
• Bootstrap techniques • Start-Up conditions
• Using floating bias supplies • Transient operation
• Bypass capacitor size
• Layout, grounding
considerations
VBIAS
VCC
PWM R1
controller VCC RGATE
RGATE
OUT PWM
controller
OUT QINV
RB
GND
R2
GND
• P-channel drivers are referenced to an
AC ground potential and does not • Works with regular PWM signal.
have to swing between large potential
differences. • Turn-on speed is fast.
• VIN<VGS,MAX • Small continuous current flows in
the inverter during on time.
• Needs inverted PWM output.
• Gate drive power and inverter
• Avoid open collector drivers. current is coming from VIN.
• Gate current does not flow in the • VIN ramp up time at power on has
ground plane, speed, maximum dv/dt to be matched to the dv/dt
might be impeded by parasitic L’s. immunity of the gate drive.
Fig.18. & Fig.20(a).
2 - 14
N-Channel High Side Direct Drive
VDRV VIN
Close up of the switching transition:
Optional 2
VCC
PWM 3
controller RGATE
VDRV
OUT
1
1
GND
• VIN<VDRV-VGS,MIN
VIN+VGS,Miller
• Gate current flows through the load.
2
• Source terminal can pull OUT pin below
GND if not protected.
Optional turn-off circuit: 3 VIN
• PNP is turned off when source rings below
-VGS,Miller FWD recovery &
• Reduced noise tolerance during off state. VGS= Current transfer
Bootstrap Implementations
VDRV VIN VDRV VIN
DBST
PWM controller
VCC
RGATE VCC DBST
PWM
controller VBST CBST
Level-Shift
OUT CBST
VOUT OUT RGATE
QLS
SRC
GND
GND
2 - 15
Protecting The SRC Pin
VDRV VIN
PWM controller
or driver output
DBST
VCC
VBST CBST
Level-Shift
OUT RGATE
SRC
GND
Fig.27.
Fig.28.
2 - 16
Start-Up and Load Transient
VBIAS VIN
DBST DSTART RSTART
VCC CBST
VCC VB DZ R
PWM GATE
controller OUT Battery
OUT IN VS
High Side
GND
Driver
GND
Fig.29.
0.8
VCC
PWM +VDRV VDRV-VCL 0.6
controller -VCL
0V
OUT 0.4 VCL
CC VDRV
IC,AVE=0 Zener Clamp
-VCL RGS
0.2
GND
0
0 0.2 0.4 0.6 0.8 1
Duty Ratio
• AC coupling provides simple level shift for
the gate drive signal. • The coupling capacitor voltage is the
• Results in slower turn-on but faster turn-off function of the duty ratio.
and higher dv/dt immunity. (VC=D⋅VDRV)
• RGS is essential to develop voltage across • VC will develop across CC over time.
the coupling capacitor. (τ=RGS⋅CC)
• RGS also serves as pull-down during start up. • Reduced negative bias at low duty-
• The clamp network is usually needed if the cycle!
duty cycle can go significantly above 50%.
Fig.31. & Fig.32.
2 - 17
Transformer Coupled Gate Drives
• Provides isolation
• Works across high potential differences
• Reliable
BUT:
• Must understand magnetics, transformer design and
operation.
– Leakage inductance must be minimized
– Faraday’s Law requires VL=0V over a period of time
– Core saturation limit (BSAT) defines maximum volt-second product
– Capacitive currents flow between the winding
• More components
• Not necessarily more expensive or bigger
IOUT
2 - 18
DC Restoration
VDRV
+VDRV-VC
VCC
+VDRV -VC +VDRV-VD
PWM
controller 0V VC VC-VD -VD
+ -
+ -
OUT
RC CC1 CC2
DC2 RGS
GND
Fig.35.
0.8
DC coupled
• Consider extreme operating
0.6 (double ended) conditions when choosing ∆B.
Normalized V·s Product
0.4
AC coupled • Minimize AC resistance.
(single ended)
• Maximize magnetizing
0.2
inductance to minimize
0
magnetizing current and droop.
0 0.2 0.4 0.6 0.8 1
Duty Ratio • Minimize leakage inductance:
– reduced drive impedance
– shorter drive delay
Fig.36.
2 - 19
Circuits With Dual Function Transformer
• Single transformer carries control signal and bias power to the gate driver.
VDRV
VDRV
GND
2 - 20
Summary
• Understanding the MOSFET’s switching behavior is
essential to design reliable, high performance gate drive
circuits.
• A systematic design approach was demonstrated.
• Mix and match of the described techniques to satisfy the
application requirements.
• Apply the same analyses to evaluate many other possible
gate drive circuits.
• Low drive impedance is imperative for high speed
switching and dv/dt immunity in MOSFET gate drive.
2 - 21