Vous êtes sur la page 1sur 56

ENSC 350: Digital Systems Design

Instructor: Dr. Ameer Abdelhadi

Spring 2017

Lecture Set: 1 January 4, 2017


Course Staff
• Course instructor:
Ameer Abdelhadi <aabdelha@sfu.ca>
Office: ASB 10827; Office hours: Thursday 4:30PM-5:40PM.
I will also try to drop into labs when possible.
• PhD from UBC in parallel memory architectures for FPGAs
• Previous academic activities
• Adjunct professor at Concordia University
• Postdoc fellow at both UBC and McGill
• Industrial experience:
Hardware designer and architect at Intel R&D and other startups

• TAs:
Eric Matthews <eric_matthews@sfu.ca> Office hours: TBD.
Maryam RasouliDanesh <rasoulid@sfu.ca> Office hours: TBD.
• Both are PhD candidates at the Dept. of Engineering Science
Slide Set 1, Page 2
Communicatinon
Emails containing questions regarding technical questions directly
related to the topics of Ensc 252 are always welcome.
Unfortunately email is not a very useful or efficient method for
discussing technical points. You may meet with TAs and myself to
address more complex technical issues.

Discussion board on Canvas. Use it to ask questions!


- You will get an answer much faster (you won’t get one using email)

My inbox has over 4000 unread messages.


Don’t get lost in there!

Personal issues: email or direct massage through Canvas


Technical issues: Canvas public discussion!

Slide Set 1, Page 3


Canvas Discussion Forums
If you ask a question, but then solve it on your own, please come share
your answer with us!

https://xkcd.com/979/ Page 4
Scheduled Activities
Lectures:
D100 Tu 2:30 PM – 4:20 PM AQ 3181
D100 Th 2:30 PM – 4:20 PM SSCB 9200
Labs:
LA01 Fr 8:30 AM – 10:20 AM ASB 10810*
LA02 Fr 10:30 AM – 12:20 PM ASB 10810*
LA03 Fr 12:30 PM – 2:20 PM ASB 10810*
LA04 Fr 2:30 PM – 4:20 PM ASB 10810*

• The Digital Hardware Laboratory has two doors numbered ASB


10810 and ASB 10808.
• The card reader is associated with ASB 10808. Please enter
through this door.
Slide Set 1, Page 5
Quizzes
• Multiple-choice i-Clicker quizzes:
• ~10 minutes
• every lecture
• ~10% of final grade

• Design Quizzes:
• ~ 30 minutes
• Every other week
• ~20% of final grade
• To be run by the TAs during lectures
Slide Set 1, Page 6
Mechanics of the Course:

Course Marking scheme:


Labs: 25%

Midterm: 25% (February 24th in class, 110 minutes)

Final Exam: 50%

See “Facts Sheet” handout for more course details. Read it carefully!

See the handout on Ethical and Professional Behaviour. Read it carefully


and sign it ASAP!!!

Slide Set 1, Page 7


Labs
Each lab spans two weeks:

Working Week:
- Spend your lab session working on your lab assignment
- TAs will be there to help you and answer questions

Marking Week:
- The lab section will primarily be used to mark your lab
- Each handout will indicate what you must demo
- The TA will also ask you questions about your lab
- You should come in with the lab done
- Your demo should be loaded and ready for your demo time slot

Marking is possible during working week, but only if the TA has time
(helping students has higher priority).
Slide Set 1, Page 8
Labs
Work in Pairs. You can choose your own partners. You will have to select
a marking demo slot. I’ll let you know if this will be done online or in the
lab on Friday.

You will have to sign out DE2-115 boards next week for the lab. I’ll post info
on lab 1 ASAP.

Please note that you need to settle into lab groups by the end of the week.
If you can’t find a partner, use Canvas.

I’ll post a “Lab Handout” handout with more details and let you know on
Canvas. Read it carefully!

Slide Set 1, Page 9


LABS START NEXT WEEK!!!

I’m going to work on Lab 1 today and tomorrow.


I’ll let you know on Canvas once it is posted so you can download it.

I’ll also let you know when you can go to sign out your lab boards
(probably Monday and Tuesday).

Slide Set 1, Page 10


Violations of Laboratory Rules and Safety Policies

Unprofessional conduct that violates safety policies or posted


laboratory rules can result in significant penalties that include loss of
access to facilities and/or a reduction in grades. This is in accordance
with the school’s policy on safety and professionalism in laboratories.

In particular, no food or drink in the lab and treat the lab equipment
with respect.

Slide Set 1, Page 11


Policies
Missed Exams and Labs:
A missed exam or lab due to illness requires a doctor’s note within 7
days or a grade of 0 will be given.

Mark Corrections:
Any error in recording your marks on Canvas must be reported
within 7 days of the mark being posted. After this time, no changes
will be made.

Ameer Abdelhadi 2017 ENSC 252: Fundamentals of 7


Digital Logic & Design
Academic Honesty
Cheating is taken very seriously …
You are allowed and encouraged to discuss assignments with other
students in the class. Getting verbal advice/help from people
who’ve already taken the course is also acceptable.
Reference to assignments from previous terms or web postings is not
unacceptable
Any copying of non-trivial code is unacceptable.
– Non-trivial = more than a line or so
– Includes reading someone else’s code and then going off to
write your own.
Giving/receiving help on an exam is unacceptable
Penalties for academic dishonesty:
– Zero on the assignment for the first occasion
– Automatic failure of the course for repeat offenses

Ameer Abdelhadi 2017 ENSC 252: Fundamentals of 8


Digital Logic & Design
Software
Students will require the use of software circuit design tools. The primary
tools will be the integrated FPGA development environment (IDE), Quartus
II. and the industry standard VHDL simulator, ModelSim‐Altera. Fully-
functional professional versions are installed in ASB 10808.
Students should download and install a free Web‐Edition of Quartus II,
available from the Altera website. (www.altera.com)
Students should download the accompanying DE2-115 CD-ROM (NXP
USB) Version 1.0.6 for the DE2-115 Development kit available from
(www.terasic.com)
A vector drawing program, Visio, by Microsoft, is also available on most
computers administered by the school of engineering science. Visio is
extremely easy to use and will be immensely useful in preparing
documents for this and future EnSc courses.
Students may be able to acquire a license for Visio through the Schools
MSDNAA using your DreamSpark Account. Please ask the school of
engineering sciences IT services for further information. ensc-
help@sfu.ca

Ameer Abdelhadi 2017 ENSC 252: Fundamentals of 10


Digital Logic & Design
Textbook
There is no required textbook. In ENSC 252/264 you will have used:
Steven Brown, Zvonko Vranesic, “Fundamentals of Digital Logic with
VHDL Design”
It will be a good reference.

Other books that you might find useful:


1. Douglas J. Smith’s HDL Chip Design: A Pracitical Guide for Designing,
Synthesizing & Simulating ASICs and FPGAs Using VHDL or Verilog
(mostly useful in learning how to switch from VHDL to Verilog)
2. David Harris, Sarah Harris, “Digital Design and Computer Architecture”,
2nd edition [ Both VHDL and Verilog]
3. Dally’s VHDL or Verilog versions of “Digital Design: A Systems
Approach” (“Digital Design using VHDL: A Systems Approach”)
4. Steven Brown, Zvonko Vranesic, “Fundamentals of Digital Logic with
Verilog Design”

Slide Set 1, Page 15


ENSC 350 is in transition…
In 2014 our second year curriculum has been revised:
- We now need to update the content of 350 to reflect the new
prerequisite materials being taught.

This year, I will be starting that process:


1) We will still be teaching VHDL. However, if I have time, I’ll try and put
some sample Verilog/System Verilog examples at the end of the course
slide sets. You won’t be responsible for the Verilog material, it will be
for the enthusiasts.

2) I’ll be significantly revising the course lecture notes and the lab
component to try and increase your design experience and knowledge.
There is no course textbook, but your ENSC 252/264 text will be a good
reference.

3) No one should take this course without having taken ENSC 252/264 first.
Slide Set 1, Page 16
What you should know from last year
Most of you have taken ENSC 252 or ENSC264:
- You should review your VHDL notes
- You should review basic logic design, state machine design,
numerical representations

Elephant in the room: Some of you found


ENSC 252 challenging. Don’t worry. Stick with
the course, do the assignments and lab, attend
the lectures, and it will all make sense.

Remember: The TAs and I both have office


hours. Use them if you need help- we all want you to succeed.

Next slide set, we will review the basics of VHDL and I’ll introduce
Processes. Slide Set 1, Page 17
How this relates to other courses:

ENSC 252: You were introduced to Digital Logic, VHDL, and the Altera
FPGA tools. You didn’t have enough time to go very deep. We will
start where you left off, reinforce what you learned, and then show
you how you can use it to design larger systems with confidence.

ENSC 254: You learned about basic computer organization. This


course will teach you how to design basic “hardware accelerators”
and how to integrate them into a system using traditional bus
architectues.

Slide Set 1, Page 18


Who might be interested in this course?
This course will be useful for:

• Those of you that want to design chips


• Those of you that want to design communication/power
systems, including cell phones and other mobile devices
• Those of you that want to control real things (robots)
• Those of you that want to design biomedical applications
• Those of you that want to write software
• Anyone else interested in Electrical and Computer Engineering

Have I forgot anyone?

Slide Set 1, Page 19


High-Level Learning Objectives
1. What is the role of digital hardware? Why not just software?
2. How do you create a working hardware design given an algorithm?
3. How do you effectively test and debug a digital circuit?
4. How do you optimize the circuit for speed, area, and cost?
5. How do you design more advanced digital systems?

Slide Set 1, Page 20


Time to start the fun.

I love this material!!!

It ties in closely with my research and I normally teach the advanced


class (ENSC 452).

I want you all to do well, so use the help that is available to you:
Piazza Discussion Board, TA Office Hours, and my Office hours
Slide Set 1, Page 21
What is digital design?
• Design of systems that operates using discrete
electric signals rather than continuous signals
• Design of systems that operates using discrete
electric signals rather than continuous signals
• Logic gates are implemented using transistors
• The entire system is implemented as a
microchip:
• FPGA: programmable (used in this course)
• ASIC: fixed-function (ENSC 450)

Slide Set 1, Page 22


History of Digital Systems: 1st Generation
• Built with Vacuum Tubes
• 1946 – 1947
• ~40,000 operations per second

Slide Set 1, Page 23


History of Digital Systems : 2nd Generation
• Built with Transistors
• 1958 – 1964

Slide Set 1, Page 24


Metal-Oxide-Semiconductor Field-Effect
Transistor (MOSFET)
Semiconductor Device Fabrication
History of Digital Systems : 3rd Generation
• Fabrication technology allowed for Integrated Circuits
• 1965 – 1971
• Small Scale Integration: <100 devices per chip
• Medium Scale Integration: 100 – 3000 devices per
chip
• ~1,000,000 oper. per second
• 1972 – 1977
• Large Scale Integration:
3,000 – 100,000 devices per chip
• ~10,000,000 oper. per second

Slide Set 1, Page 27


MOSFET Technology
Allows placement of billions transistors on a single chip!
The backbone of Very Large Scale Integration (VLSI)
Currently (early 2017), the densest Integrated Circuit (IC) device ever
is:

Stratix 10 FPGA device


by Intel (formally Altera)
with more than
30 billion transistors!
History of Digital Systems : 4th Generation
• Very Large Scaled Integration: 100,000 – 20,000,000,000
• > 50,000,000,000 operations per second
• (i.e. Nvidia GV100 21B Transistors)

Slide Set 1, Page 29


Integrated Circuits (ICs)
MOSFET Fabrication Steps
Technology Nodes
10 µm 1971
Characterized by the minimum half distance between 6 µm 1974
identical features 3 µm 1977
1.5 µm 1982
Current Commercial technology node is 10nm 1 µm 1985
– For comparison: 800
nm
1989

the distance between the centers of two silicon 600 1994


atoms (covalent bond distances) is 2 Å nm
350 1995
(1Å=0.1nm) nm
– The channel of a 10nm transistor can fit 50 250
nm
1997

silicon atoms! 180 1999


nm
130 2001
nm
90 nm 2004
65 nm 2006
45 nm 2008
32 nm 2010
22 nm 2012
14 nm 2014
10 nm 2017
7 nm 2018
5 nm 2020
And the trend continues...
Moore’s Law (1965)
• Gordon Moore, Fairchild Semiconductor
• Noticed 2x number of transistors every 12-
18 months
"The complexity for minimum component costs has increased
at a rate of roughly a factor of two per year. Certainly over the
short term this rate can be expected to continue, if not
increase. Over the longer term, the rate of increase is a bit
more uncertain, although there is no reason to believe it will
not remain for nearly constant for at least 10 years. That
means by 1975, the number of components per integrated
circuit for minimum cost will be 65,000.”
"I believe that such a large circuit can be built on a single
wafer."

Slide Set 1, Page 33


And the trend continues...
Moore’s Law

Slide Set 1, Page 34


And the trend continues...
Moore’s Law

• Partly self-fulfilling prophecy (sets industry targets)


• While at the same time,

Slide Set 1, Page 35


The Design Productivity Gap
Design Complexity vs. Designer Productivity
10,000 100,000

1,000 10,000

Productivity ( Trans. Per


Logic Transistors per Chip

Design Complexity
(58% per year compounded)
1,000

Staff - Month )
100

10 100

1 10

0.1 1
Productivity Growth
(21% per year compounded)
0.01 0.1

0.001 0.01
1981

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2003

2005

2007

2009
Source: ITRS

Constant need for new design techniques


and more engineers
Slide Set 1, Page 36
Where are Digital Systems used?

Slide Set 1, Page 37


Application #1: Consumer Electronics

Page 38
Application #1: Consumer Electronics
iPad Pro
Gyroscope/Acc
elerometer
Audio Codec
Cortex M0
RAM Processor

NFC Controller
A9X Processor
Application #1: Consumer Electronics
iPhone 6 Plus
Envelope
Tracking

A8 Processor
LTE Modem

Gyroscope/Acc
elerometer Source: ifixit.com
Application #2: Automotive
- 7-Series BMW: 63 Embedded Processors
- Mercedes S-Class: 65 Embedded Processors
- More than 80% of the innovation in autos is from innovations in
electronics (Daimler-Chrysler)
- Automotive Semiconductor Market: US$ 13.1 billion / year
Application #2: Automotive
Application #3: Biomedical Applications
Surgical Robotics

Diagnostic

Electronic Medical Implants


Advanced
Prosthetics

Page 43
Application #4: Scientific

Slide Set 1, Page 44


Application #5: Defense

Slide Set 1, Page 45


Application #6: Communication Circuits
24 100 Meg + 2 Gig Port Ethernet
Switch

- 60 Million Transistors
- Over 4 Million Gates
- 8Mb of Embedded RAM

Slide Set 1, Page 46


Application #7: Home Automation

Page 47
Application #8: Control Applications
Digital Systems are the Brains in virtually all electronic equipment!
Implementation Options
ENSC
252

ENSC
450
Slide Set 1, Page 50
Complexity…
Intel Sandy Bridge: More than 2 billion transistors…

Slide Set 1, Page 51


Digital Systems: Hardware vs. Software
main()
{
int i,j,tt=0;
for(i=0;i<100;i++) {

Software for(j=0;j<i;j++) {
}
tt = tt*i+j;
}

Generic
Processor
(eg. ARM, Custom
x86) Hardware
Circuit

Create custom hardware circuit


Software runs on generic
that does just what you want.
processor (available from ARM,
Intel, etc).
Implement using breadboard,
custom chip (ASIC), FPGA…

Slide Set 1, Page 52


Hardware is orders-of-magnitude faster than software
Hardware uses orders-of-magnitude less power
But, hardware takes more time to design…

A good (a.k.a. highly paid) engineer needs to be able to understand the


benefits of limitations of each in order to make good design decisions.

Slide Set 1, Page 53


The future: Hardware and Software
But what about a mix? A system with both hardware and software

Hot trend: FPGAs in the data-center (“cloud”)


- Each node in a data center may have a processor and hardware
fabric (based on an FPGA)
- Programming this involves writing both software and hardware
Slide Set 1, Page 54
Interesting example…

Every picture uploaded to Facebook is scanned by two neural


networks to identify faces
- Neural nets use an algorithm called Convolutional Neural Nets
modeled after the structure of the brain
- Very time consuming, Facebook is building hardware
accelerators out of FPGAs and custom chips

Slide Set 3, Page 55


Slide Set 1, Page 56