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INTRODUCTION TO MICROPROCESSOR, ITS ARCHITECTURE & DIFFERENT PARTS, ALU

MICROPROCESSORS INTEL 8085 CPU BLOCK DIAGRAM

PARTS, ALU MICROPROCESSORS INTEL 8085 CPU BLOCK DIAGRAM Figure Intel 8085 CPU Block Diagram SYMBOL TYPE

Figure Intel 8085 CPU Block Diagram

SYMBOL

TYPE

NAME

FUNCTION

     

The most significant 8 bits of the memory address or the 8 bits

A 6 -

A 15

0

ADDRESS BUS

of the I/O address, 3 stated during Hold and Halt modes and during Reset

AD 0 - 7

I /0

MULTIPLEXED ADDRESS / DATA BUS

Lower 8 bits of memory address from the first clock cycle ( T state ) become the data bus during second and third clock cycles.

     

1) It occurs during the first clock state of the machine cycle and enables the address to get latched into the on-chip latch of

ALE

0

peripherals.

ADDRESS LATCH ENABLE

2) The failing edge of ALE is set to guarantee set-up and hold

     

times for the address information.

3) Failing edge be used to strobe the status information.

4) ALE is never 3 states

     

1) S 1 can be used as an advanced R/W.

2) S 0 , S 1 and IO/M become valid at the beginning of the

S 0 , S 1 and IO/M

0

MACHINE CYCLE STATUS

machine cycle and remain stable throughout the cycle.

3)The failing edge of ALE may be used to latch the state of these lines.

     

A

low on RD indicates the selected memory or I/O device is to

RD

0

READ CONTROL

be read and the Data Bus is available for the data transfer , 3

stated during Hold and Halt modes and during RESET.

WR

0

WRITE CONTROL

A

low level on WR indicates the data on the Data Bus is to be written into the selected memory.

     

1) If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready to send and receive data.

READY

1

READY

2) If READY is low , CPU will wait an integral number of clock cycles for READY to go high before completing the read or write cycle.

     

1) HOLD is requesting the use of address and data buses.

2) The CPU, receive HOLD request , it will relinquish the use

HOLD

1

HOLD

of

the bus as soon as the completing of the current bus

transfer.

     

3) The processor can regain the bus only after the HOLD is removed.

     

1) Cpu has received the HOLD request and relinquish the bus

in

the next clock cycle.

HOLD

 

HLDA

0

ACKNOWLEDGE

2) HLDA goes low after the low request removed.

3) Cpu takes the bus one half clock cycle after HLDA goes low.

     

1) Used as general purpose interrupt.

2) If it is active , the Program Counter (PC) will be inhibited

INTR

1

INTERRUPT REQUEST

from

incrementing and INTA will be issued.(During this cycle RESTART or CALL instruction can be inserted to jump to

     

the interrupt service routine)

3) INTR is enabled and disabled by software.

4) It is disabled by RESET and immediately after an interrupt is accepted.

   

INTERRUPT

 

INTA

0

ACKNOWLEDGE

It can be used to activate an 8259A Interrupt is accepted.

RST 5.5

   

These interrupts have the same timing as INTR excepted they

RST 6.5

RST 7.5

1

RESTART

INTERRUPTS

cause an internal RESTART to be automatically inserted.

     

1) Trap interrupt is non mask able RESTART interrupt.

TRAP

1

TRAP

2) It has the highest priority of any interrupt.

     

1) Sets the Program Counter to zero and reset the interrupt Enable and HLDA flip-flops.

RESET IN

1

RESET IN

2) RESET IN is a Schmitt-triggered input, allowing connection to an R-C network for power -on RESET delay.

     

1) RESET OUT indicates CPU is being reset.

RESET OUT

0

RESET OUT

2) Can be used as a system reset.

     

1) Connected to a crystal , LO or RC network to drive the internal clock generator.

X 1 , X 2

1

X 1 , X 2

2) X 1 can be external clock input from logic gate.

     

1) Clock output for uses as a system clock.

CLK

0

CLOCK

2) The period of clock is twice the X 1 , X 2 are input period.

SID

1

SERIAL INPUT DATA LINE

The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed.

   

SERIAL OUTPUT

The output SOD is set or reset as specified by the SIM instruction.

SOD

0

DATA LINE

V CC

 

POWER

+ 5 volt supply

V

SS

 

GROUND

Reference

Table Pin Description

Figure Intel 8085 Pin Configuration NAME PRIORITY Address Branched To (1) When Interrupts Occurs. Type

Figure Intel 8085 Pin Configuration

NAME

PRIORITY

Address Branched To (1) When Interrupts Occurs.

Type Trigger

TRAP

1

24H

Rising edge AND high level until sampled.

RST 7.5

2

3CH

Rising edge latched

RST 6.5

3

34H

High level until sampled

RST 5.5

4

2CH

High level until sampled

INTR

5

Refer notes above

High level until sampled

Table Interrupt Priority, Restart Address and Sensitivity

* CPU is stand for Central Processing Unit. It is brain of a computer.

* CPU can read from the input rise to the output and do all the computation inside the computer.

* CPU = ALU (legal function) + Control Unit (decoding and destruction) + Register (storage device).

* ALU is arithmetic operational logical such

as + , - , x , AND, OR, EX-OR , NOT and so on. It used for addition.

Example:-

0

1 0

+

1

0

1 1

used for addition. Example:- 0 1 0 + 1 0 1 1 Figure ALU * Register

Figure ALU

* Register

* Control Unit = Internal control signal & external control signal.

* Microprocessors is a CPU made on a single VLSI chip.

Actually, long time ago, people wanted to have a chip to do something very fast. So, they did a project (INTEL). It was made to put knowledge inside. It has a different programming

language call as simple language.

* Microcomputer = Microprocessor + Memory + I/O

* Microsystems

= Buffer, a set of flip-flop and temporary storage of data.

= Microcomputer + Software.

The first microprocessors made call as, INTEL 4001 (4 bit words length), they found that the function went down so another microprocessors was made call as INTEL 808 (8 bit words length.This intel can do around 220 functions). INTEL 8080 (8 bits words length) INTEL 8085 ( INTEL 8080 and clock generator ) INTEL 80086 ( 16 bit words length) INTEL 80286 ( 16 bit words length)

INTEL 80386 (16/32 bit words length) INTEL 80486 ( 32 bit words length)

Motorola - introduce M6800, M 68020

Zilog

- introduce Z80, Z8000

Texas

- introduce TMS80, TMS 8000

Z80, Z8000 Texas - introduce TMS80, TMS 8000 Figure CPU connected to Memory * Note :

Figure CPU connected to Memory

* Note : Intel 8085 example of CPU 40 pins

* CPU interact using electric signals(40 pins). Electrical signal coming-out from CPU device to 3 lines.Only CPU give address to memory.

* CPU can read and write without memory. Bus is a set of electrical wayer that carry signal. Every instruction must translate to binary code.

* In CPU, there is one Program Counter.

* Memory is divided in 2 parts .

First part is external, example : HDD, FDD , CD-ROM. Second part is internal , example : semiconductor memory RAM, ROM. CPU will read location 0 from memory.

Program Counter must have 10 bits. It always points to memory and point to instruction to be execute.

Program Counter Size :-

1

2

3

and so on.

Bits -

Bits -

Bits -

2

2

2

1

2

3

16 bits program counter = 16 flip-flops. n bit pc = can address 2 n location.

General Purpose Register It looks like Scratch pad register. Some register inside microprocessor

to scratch for temporary storage of data. Size of register in generally equal to word length.

8085 ===> 8 bit

8086 ===> 16 bit

386, 486 ===> 32 bit All three above are A, B, C, D, E, H, L

A, B, C can be used as single 8 bit register and also can be used as pairs.

Flag Register 5 Flip-flops - Signify different condition in ALU takes place. (1) Carry Flag - F/F is set when there is carry in result. (2) Zero Flag - It set to 1 when result = 0 useful to compare the two number.

(3) Sign Flag

(4) Parity Flag - Used to add up parity bit in the system.

- Data is change on the way - Make a noise of electricity. - Is used by ALU to BCD addition , attach to ALU.

(5) AC Flag

- Identify either the number is +ve or -ve.

Temporary Registers. Used for temporary storage of data by a CPU. It is not reliable to users.

Conclusion:-

Program Counter ----> Address lines ----> Memory ----> Data ---->CPU ---> Operation Code Buffer ------> Decoder-----> Timing. Explanation Microprocessors used to read and write from memory .There, operation code register was stored. CPU will issue address on address lines using program counter. Memory will issue operation code which will be stored in operation code buffer.The output of operation code is decoder using 8 decoder to understand the memory of code/instruction.Output of decoder given to timing to generate internal and external control signals for execution and instruction.

Figure Buffer - Decoder- Timing & Control Unit Basic System Timing * The 8085AH has

Figure Buffer - Decoder- Timing & Control Unit

Figure Buffer - Decoder- Timing & Control Unit Basic System Timing * The 8085AH has a

Basic System Timing

* The 8085AH has a multiplexed Data Bus.

* ALE is used as strobe to sample the lower 8 bits of address on the Data Bus.

* Figure 8085AH Basic System Timing shows an instruction

fetch, memory read and I/O write cycle ( as would occur during processing at the OUT instruction).

* Note that during the I/O write and read cycle that the I/O port address

is copied on both the upper and lower half of the address. There are seven possible types of machines cycles. Which of these seven takes place is

defined by the status lines ( IO/M , S 1 , S 0 ) and the three control

signals ( RD, WR and INTA). (See the table 3). The status lines can be used as advanced controls (for devices selection, for example), since they become active at the T 1 set at the outset of each machines cycle.

* Control lines RD and WR become active later, at the time when the transfer of data is to take place, so are used as command lines. A machine cycle normally consists of three T states , with the exception of UNICODE FETCH, which normally has either four or six T states (unless WAIT

or HOLD states are forced by the receipt of READY or HOLD inputs). Any T state must be one of ten possible states , shown on table 4.

Machine Cycle Status:- S 1 S 0 Control:- I /OM RD WR INTA OPCODE FETCH
Machine Cycle
Status:-
S 1
S 0
Control:-
I
/OM
RD
WR
INTA
OPCODE FETCH (OF)
Status:-
0
1
1
Control:-
0
1
1
MEMORY READ (MR)
Status:-
0
1
0
Control:-
0
1
1
MEMORY WRITE
Status:-
0
0
1
Control:-
1
0
1
(MW)
I/O READ
Status:-
1
1
0
Control:-
0
1
1
(IOR)
I/O WRITE
Status:-
1
0
1
Control:-
1
0
1
(IOW)
ACKNOWLEDGE OF INTA
(INA)
Status:-
1
1
1
Control:-
1
1
0
BUS IDLE
(BI):-
Status:-
0
1
0
Control:-
1
1
1
DAD
ACK.OF
RST,
Status:-
1
1
1
Control:-
1
1
1
TRAP
HALT
Status:-
TS
0
0
Control:-
TS
TS
1

Table 3 (8085AH Machine Chart )

STATUS & MACHINE STATE S1,S0 A 8 -A 15 AD 0 -AD 7 CONTROL:- ALE
STATUS &
MACHINE STATE
S1,S0
A 8 -A 15
AD 0 -AD 7
CONTROL:-
ALE
BUSES:-
I/OM
RD,WR
INTA
STATUS &
T
X
X
X
X
CONTROL:-
1
1
1
1
BUSES:-
STATUS &
T
X
X
X
X
CONTROL:-
X
X
0
2
BUSES:-
STATUS &
X
X
X
X
CONTROL:-
X
X
0
T WAIT
BUSES:-
STATUS &
T
X
X
X
X
CONTROL:-
X
X
0
3
BUSES:-
STATUS &
T
1
O
X
TS
CONTROL:-
1
1
0
4
BUSES:-
STATUS &
T
1
O
X
TS
CONTROL:-
1
1
0
5
BUSES:-
STATUS &
T
1
O
X
TS
CONTROL:-
1
1
0
6
BUSES:-
STATUS &
X
TS
TS
TS
CONTROL:-
TS
1
0
T RESET
BUSES:-
STATUS & T 0 TS TS TS CONTROL:- TS 1 0 HALT BUSES:- STATUS &
STATUS &
T
0
TS
TS
TS
CONTROL:-
TS
1
0
HALT
BUSES:-
STATUS &
T
X
TS
TS
TS
CONTROL:-
TS
1
0
HOLD
BUSES:-
Table 4 (8085AH Machine State Chart)

* NOTE

0 = LOGIC "0"

1 = LOGIC "1"

TS = HIGH IMPEDANCE X = UNSPECIFIED

(1) ALE NOT GENERATED DURING 2ND AND 3RD MACHINE CYCLES OF DAD INSTRUCTION (2) IO/M = 1 DURING T 4- T6 OF INA MACHINE CYCLE.

3RD MACHINE CYCLES OF DAD INSTRUCTION (2) IO/M = 1 DURING T 4- T6 OF INA

Figure 8085AH Basic System Timing