2014 IEEE 28th Convention of Electrical and Electronics Engineers in Israel

Designing of Single Precision Floating Point DSP

Co-Processor
Evgeni R. Overchick, Binyamin Abramov
Dept. Electrical Engineering
Afeka College of Engineering
Tel Aviv, Israel
ronyevgenio@mail.afeka.ac.il, binyamina@afeka.ac.il

Abstract—In this paper, we show that using FPGA as a Co-
Processor with floating point arithmetic can enhance DSP system
performance levels through optimized core implementation of
critical compute-intensive digital signal processing algorithms
such as Fast Fourier Transform (FFT) . Our approach is based
on building basic building blocks, by implementing optimized,
multi-cycle, floating point arithmetic core, which are then used to
implement much complex layers of logic such as FFT butterfly,
complex multiplier and a DFT block. We present performance
results to show that a speedup of 10-19X can be achieved over an
optimized FFT DSP Coprocessor implementation on a low cost
FPGA such as Cyclone IV.
Index Terms - DSP Coprocessor, FFT, Single Precision
Floating Point Numbers, IEEE754, FPGA.
I. INTRODUCTION
Effective hardware implementation of FFT algorithm can
be achieved through the following methods. The first, related
to the modern and new techniques is the Field Programmable
Gate Array (FPGA) approach, and the second, based on
Application Specified Integrated Circuit (ASIC) architecture.
The FPGA technologies are quite mature for Digital Signal
Processing (DSP) applications [5] due to fast progress in Very
Large Scale Integration (VLSI) technology. Today, the FPGA
devices provide fully programmable system-on-the-chip
environments by incorporating the programmability of logic
cells, and architecture of gate arrays. They consist of tens of
thousands of configurable logic blocks which make them an
appropriate solution for specified digital signal processing
application.
The objective of this work was to get an area and time
efficient architecture that could be used as a coprocessor, with

T he Fourier transform converts information from the time

domain into the frequency domain [16]. It has been widely
applied in the analysis and implementation of video, audio and
digital communication systems. Since digital communication is
quite an active field, the arithmetic complexity of the Discrete
Fourier Transform (DFT) algorithm became a significant factor
with impact in global computational costs. The Fast Fourier
Transform (FFT) is an efficient algorithm for computing the
Discrete Fourier Transform (DFT) and requires fewer
computations than a direct evaluation of DFT. The FFT is the
generic name for a class of computationally efficient
algorithms that are widely used in the field of digital signal
processing [7]. FFT can be implemented by using different
techniques. Because of the complexity of the processing
algorithm of The FFT, recently various FFT algorithms have
been proposed to meet real-time processing requirements and
to reduce hardware complexity over the last decades such as
single-memory architecture, dual-memory architecture, cached
memory architecture, array architecture and pipelined
architecture [17]. We implement single precision floating point
arithmetic units such as Adder/Subtractor, multiplier and use
them as building blocks for the coprocessor. The algorithm we
implement is decimation in time Radix 2 FFT. In order to boost
the performance of the coprocessor, we use in-place calculation
and optimized floating point core.
all necessary resources built-in, for an embedded DSP
application.
The basic concept of FPGA technique will be described in
details which will cover the necessary subjects that are needed
in the application design. The design procedures of FFT for
FPGA technique will be presented with its results.
The paper is structured as follows: Section II describes
related work done in the field, sections III describes Single
Precision IEEE 754 format and section IV describes FFT. Our
implementation is discussed in section V, Section VI describes
the results in terms of LE and maximum frequency, and section
VII discusses our conclusions.
II. RELATED WORK
Unlike CPUs, FPGAs have a high degree of hardware
configurability. The dataflow nature of computation
implemented in FPGA overcomes some of the issues of the
memory and bandwidth limit that Floating Point arithmetic
raises [1]. Much work has been done in designing coprocessor
units on FPGAs in order to accelerate performance in different
fields i.e. Geophysics, Image Processing, Molecular Dynamics,
etc., [2][3][4]. FPGAs consist of an array of programmable
logic blocks of potentially different types, including general
logic, memory and multiplier blocks, surrounded by a
programmable routing fabric that allows blocks to be
programmably interconnected. The array is surrounded by
programmable input/output blocks, labeled I/O in the figure,
that connect the chip to the outside world.
The “programmable” term in FPGA indicates an ability to
program a function into the chip after silicon fabrication is
complete. This customization is made possible by the
programming technology, which is a method that can cause a
change in the behavior of the pre-fabricated chip after
fabrication, in the “field,” where system users create designs
[18]. The use of FPGAs in signal processing offers an
alternative solution for computationally-intensive function
found in DSP [5] [6]. One of DSP’s most widely used
algorithms is Fast Fourier Transform (FFT). Using this
transform, signals are being represented in the frequency
domain where performing analysis or filtering is much less
complex. When considering the different alternative
implementations of the FFT algorithm to be chosen, one must
carefully consider different parameters, whether the execution
speed and hardware complexity, flexibility and precision. For
real time systems the execution speed is the main concern.
Many of the FPGA implementation of the FFT for real time
signals use fixed point arithmetic[7] [8]. The flexibility of the
FPGA allows one to design application specific floating point
operators by tailoring its parameters to the application
requirements [9]. Floating point arithmetic requires much more
area per operation and, more importantly, it requires almost as
much area for an adder as for multiplier. Also, it has higher
demands on memory and bandwidth capacities. Number of
vendors sell a IEEE 754 single precision floating point FFT
core [10][11], but their implementation details, and various
design choices are not discussed. Also, an open source library
that implements IEEE 754 floating point arithmetic exists [12]
but it is not optimized and baseline performance are low if it is
used as is.
III. IEEE 754 FLOATING POINT OVERVIEW
Floating point encoding and functionality are defined in the
IEEE 754 Standard last revisited in 2008 [13] [14]. The
standard binary floating point format has three components. A
one bit sign, followed by exponent bits encoding the exponent
offset by a numeric bias, and the mantissa, which encodes the
significant or fraction. In order to ensure consistent
computation across different platforms and to exchange
floating point data, IEEE 754 defines basic formats. The Single
Precision format is a 32 bit binary floating point number which
have the following bit lengths:
Sign – 1 bit Exponent – 8 bit Fraction – 23 bit
The sign is either negative or positive. The exponent field
encodes the exponent in base 2 and is biased by 127 to allow
exponents to extend from negative to positive. The fraction
field encodes the significant without the most significant non-
zero bit. Also, there is an extra bit of precision that comes from
an implied (hidden) leading one bit except in a special case of
sub-normal numbers where this implied bit is dropped. The
IEEE 754 also describes infinity and Not-a-Number (NaN).
Moreover, given that, the fraction field described by limited
number of bits, not all real numbers can be represented exactly.
It is handled by rounding rules which are specified in IEEE 754
standard.
IV. FAST FOURIER TRANSFORM
The Fast Fourier Transform (FFT) is a discrete Fourier
transform algorithm which reduces the number of
computations needed for N points from 2N2 to 2NlogN where
log is the base-2 logarithm [16]. Fourier analysis converts time
or space to frequency and vice versa. In many domains fixed
point is sufficient. However, the FFT also has uses in scientific
applications ranging from climate modeling, molecular
dynamics and radar, which require floating point arithmetic.
The fundamental calculation of the N point DFT is
described as:
N 1−1 − i 2π jk
Y[ j] = ∑ X [k ]WNjk ; where WNjk = e
k =0
N
(1)
We choose to implement FFT by using radix-2 decimation
in time algorithm, where each stage operates pairwise on data
set. A complete flow graph of radix 2 DIT decomposition of 8
point DFT is represented in Figure 1.
Fig. 1. 8 point decimation in time FFT flow graph
Radix-2 algorithm was chosen because of its simplicity. It
yields the smallest butterfly unit compared to other radices.
Moreover, other radices reduce the total number of operations
but are much complex [17]. Also, in Figure 1, we notice that
the butterfly unit is a basic operation which repeats itself at
each stage but with different input.
 Hence, our effort to optimize the process begins at the
butterfly unit. The structure of the butterfly unit, as shown in
Figure 2, consists of a single complex multiplication and two
complex additions.
Fig. 2. Radix-2 Decimation In Time Butterfly
V. FFT COPROCESSOR IMPLEMENTATION
We exploit FPGA’s parallelism in the FFT computation in
two ways: pipelined floating point arithmetic units (multiplier
and add/sub unit) and parallelism within the stages of FFT.
A. Floating Point Hardware Considerations
In any operation, that’s using floating point numbers the
first task is to analyze the exponent and the mantissa operands
in order to determine the number type. On the other hand, the
last task of the operation is to compose the sign, exponent and
mantissa of the result into a number. Therefore, our floating
point units, the multiplication unit and the sub/add unit are
composed of three stages: the pre-processing stage, the
calculation stage and the post-processing stage, as illustrated in
Figure 3.
Fig. 3. Floating point operation flow
Two key design decisions were introduced. The first is
simplification of denormalized numbers, and the second is
limitation of the rounding to just truncation toward zero.
Most of the needed logic in the pre-processing stage and
post-processing stage is used for handling denormalized
numbers. The significant use of resource, negatively affects the
performance of arithmetic units. However, floating point
operation algorithms require normalized numbers e.g.
mantissa’s leading bit has to be equal to 1. Moreover, the use
of denormalized numbers does not contribute to most
applications because denormalized numbers represent a small
infrequent part of the format. Most of the floating point format
is reserved for normalized numbers. Moreover, their value
−126
(i.e. < 2 ) is rarely used too, and is infrequent in most
applications. Therefore, in order to simplify the pre and post
processing stages, which would lead to reduced synthesized
logic and a boost in performance, denormalized numbers were
handled as zero so all related logic would be eliminated. The
Fig. 4. Complex multiplier implementation
cost of this solution is in resolution and in accuracy. However,
this loss of accuracy is relative as the resolution of a
denormalized number depends on the position of its leading 1.
B. Floating Point Adder/Subtractor
In the pre-processing stage, the unit checks which input
number is bigger by comparing the exponent and then aligns
the mantissa of the smaller number by the difference. In the
calculation stage of a floating-point adder/Subtractor unit we
use fixed arithmetic adder/Subtractor which does not present
any particular complexity that calculates the mantissa of the
result. The sign of the result is calculated in the preprocessing
stage by taking into account the input signs, if it is an addition
or a subtraction and which operand is bigger. The exponent of
the result which equals to the exponent of the biggest operand
is adjusted during post-processing, if the mantissa result
presents a carry (addition) or a cancelation of its most
significant bits (subtraction).
C. Floating Point Multiplication
In order to optimize the multiplication unit, we chose to
implement multiplication operation in the calculation stage by
using FPGA’s embedded multipliers. Nowadays most of the
FPGA’s include a combination of on-chip resources and
external interfaces that help increase the performance of DSP
systems. In Cyclone IV devices (we used EP4CE115) the
embedded multiplier can be configured as either one 18x18
multiplier or two 9x9 multipliers. We used embedded
multipliers to build a three cycle 24x24 multiplier by cascading
18x18 and a 9x9 multiplier.
D. Complex Multiplication
In FPGA’s complex multiplication is an expensive
operation in terms of logical operations in hardware. This is
true also when it is implemented using floating point
arithmetic. As such, we reduce the complexity of this
multiplication in the following manner:
R + jI = (X + jY) × (C+ jS) (2)
R = (C− S) × Y + Z (3)
I = (C+ S) × X − Z (4)
Where Z = C × ( X − Y ) (5)
In this manner, we reduce the multiplicative complexity by
calculating only three sub/add operations and three real
 flow graph at figure 1, the DFT units, recive different input
data and coefficients but the operation remains the same. This
is why our FFT unit has only four parallel DFT units. We use a
control unit and in-place memory calculation in order to repeat
the operation three times with diffrenet inputs and coefficients.
VI. RESULTS
In order to examine the proposed approach for design of
FFT DSP coprocessor we built a system simulating an input of
1024 point vector of normalized numbers. The system was
composed of test software written in C# that calculated a vector
of 1024 point of a Sine function. The system injected the vector
Fig. 5. FFT Unit Principal Architectute into a RAM unit and activated the coprocessor. The results of
the coprocessor were compared to pre-calculated FFT on the
multiplications. The twiddle factor is a number represented by same vector. The simulation of the coprocessor and the test
C and S, and is pre-computed. Therefore, it is necessary only to system were simulated using ModelSim software. In figure 6,
store the following coefficients: C+S, C S and C in a the FFT unit simulation is being presented. The first signal in
memory table. The signal flow of the complex multiplier unit the simulation is the coefficient address, which at each stage
can be seen in figure 3. changes. The next four signals are the DFT unit reset signal.
The stage signal is a counter which represents the current stage
E. DFT Unit in order to determine the correct address that the address
The DFT unit is the building block of the FFT. It is composed generator provides to diffrenet units (signals address_sig,
of a complex multiplier which was described previously, a addr_input_stage, counter_load). Signals d_i, d_r, q_r_out and
twiddle unit which is composed of two floating point q_i_out are the data signal vectors that are composed 8
Adder/Subtractor and a ROM that holds twiddle factor numbers of 32 bit lengths. The synthesis we used Altera
coefficients that were calculated in advance (C+S, C S and Qurtaus. Altera Cyclone IV FPGA was used as a basis for the
C). A simple state machine with only three states controls this implementation of the coprocessor and the test system. The
unit. The first two states control the operation of complex results of the experiments are presented in Table I and in Table
multiplier and of the twiddle factor, while the third state is the II. In Table I the first column shows the unit name, the next
end state where the DFT unit is on standby for another input. three columns describe the number of cycles each unit need in
order to finish its operation and get a result, the maximum
F. FFT Unit frequency of a unit and the number logic elements each unit
This is the main unit that performs the FFT calculation. It is requires. In comparison to floating point Adder/Subtractor unit
composed of four parallel DFT units, two serial-in parallel out that was instantiated by Bishop floating point library [12],
register and two parallel-in serial out register, each for real which required approximately 6000 LE and had maximum
numbers vector and for imagionary numbers vector (figure 5). operating frequency of 14 MHz, our FP Adder/Subtractor takes
Both of the registers receive eight floating point number (real ten time’s fewer logic elements (600 LE) and has a maximum
and imaginary) which are represented IEEE 754 format (32 operation frequency of 140 MHz. Moreover, the coprocessor
bit). An address generator unit is in charge of providing calculates FFT at 50 MHz tenfold faster than a 3.5 GHz i7
address to a RAM module that holds input/output values and to quad processor and at 130 MHz almost 20 times faster with
the coefficient ROM in the complex multiplier. The FFT unit
calculates in-place FFT. The first state of the FFT operation is
error of ≈ 1 ⋅10 −7 compared to pre calculated results in Matlab.
to receive an input vector into the RAM module. The next state TABLE I
is sending eight points of the input vector to the parallel DFT DESIGN SUMMARY OF DIFFRENT COPROCESSOR MODULES
Max
units through the memory registers. Inside the DFT unit, the Unit Cycles Frequency LE
first operation to be perfomed is the complex multiplication of [MHz]
the input and the pre-calculated coefficients which are chosen FP Adder/Subtractor 4 140 600
using the provided address from the address generator unit of FP Multiplier 3 250 200
the FFT. The last step in the DFT unit is the butterfly Complex
12 140 ~2400
calculation. After this calculation, the DFT results are written Multiplication
to the same place in the RAM module, again using the FFT 96 130 ~18k
provided address from the address generator unit. In fact, the TABLE II
FFT COPROCESSOR PERFORMANCE
address generator unit is composed of several counters of
Unit 50 [MHz] 100 [MHz] 130 [MHz]
diffrent lengths that are being used by all the control units and
all the memory units such as the coefficient ROM and the I/O CoProcessor 1.8 [µs] 0.9 [µs] 0.6932[µs]
results RAM. This flow repeats itself three times according to TABLE III
the eight point radix-2 FFT algorithm. At each stage in the FFT FFT COPROCESSOR PERFORMANCE
FFT i7 @ i5 @ 1.7 E2160 @ E8400 @
CoProcessor 3.5GHz GHz 1.8GHz 3GHz
0.6932[µs] 10 [µs] 24 [µs] 60 [µs] 12 [µs]
 VII. CONCLUSIONS
The present paper proposes architecture for DSP
Coprocessor for FFT calculation using floating point
arithmetic. The proposed architecture provides:
• Optimized floating point arithmetic units such as
Adder/Subtractor and multiplier with IEEE 754 single
precision representation.
• In-place 8 point radix 2 FFT using single precision
IEEE 754 floating point representation.
Result analysis shows that the proposed solution can boost the
performance of complex DSP algorithms. Our FFT
Coprocessor is x20 times faster than i7@3.5GHz CPU.
Two design decisions targeting the simplification of floating
point complexity have been explained. Handling complexity
requires logic resources, thus as the complexity is reduced so
are the logic resources needed for an operator. Additionally, as
fewer resources are used, arithmetic operator’s
implementations become more efficient, and speed (clock
frequency) is also improved. For latency dependent
applications, instead of increasing the clock frequency, we can
reduce the number of pipeline stages. Our approach focused on
optimizing those features of floating-point arithmetic that
require a heavy processing overhead while their relevance in
the format is minimum or can be neglected. Also, when
implementing higher level building blocks of the FFT, we
optimized the mathematical complexity of the complex
multiplier and used pre-calculated coefficients which were
stored in memory. Moreover, the in-place FFT approach
combined with an address generator reduces the memory
requirements, simplifies the control unit of the systems and
allows more efficient implementation.
Fig. 6. FFT unit simulation result
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