[CprE 381] Computer Organization and Assembly-

Level Programming, Fall 2017

Project B - Report
Name(s) Tristan E. Anderson

Section /Lab Time Section F

Refer to the highlighted language in the Project B instruction for the context of the following questions.

a. [Part. 3] Provide a description of a few test cases (at least one test case for each of the six instructions)
and clear screenshots depicting your functioning test cases. (6 pts)
 ADD
This screenshot shows the first add instruction in the program besides the one that zeroes
out register 16. This adds register 16 (0) to register 10 (1) and stores to register 16 (0+1=1).

1|Page
 ADDI
This screenshot shows the first ADDI in the program, adding 4 to register 9.

 LW
This screenshot shows the initial LW in the pipeline test, which loads 10 into register 8. You
can see the register write enable go to 1, the selected register is 8, and the write data is 10.
Then you see the value of register 8 become 10.

2|Page
 SW
This screenshot shows the SW where register 16 is stored into dmem. Note the value of
dmem(inst32) wren going to 1 and then back to 0.

3|Page
 BEQ
This screenshow shows the branch at the very end of the program execution. Note that
register 16 has a value of 37 which is in fact the final value. The signal to look at is the i_a,
i_b, and o_f of “branchand” which is “anding” the branch signal from the main control and
from the comparator and outputting whether the branch is taken or not.

4|Page
  J
This image shows the jump value going to 1. This represents the first jump in the program.

b. [Part 4] Implement ID stage branch resolution and provide a legible simulation-screenshot of a taken-
branch instruction correctly executing. (6 pts)
This screenshot shows the branch comparator value (i_A) and the branch select from main
control (i_B) and puts them into an “and2” and outputs o_F to decide if the branch is being
taken. You can see the id instruction update after the branch.

5|Page
c. [Part 5a] Implement a forwarding unit (using VHDL) to support the following data dependent cases.
Give simulation screenshots of correct forwarding for each case: (6 pts)
i) ALU producer to ALU consumer at distance 1 (e.g. ADD $1, $2, $3; ADD $4, $1, $2)
This screenshot represents test one, which includes addi t0, zero, 1.. add t1, zero, t0..add
t2,t1,zero.

6|Page
ii) ALU producer to ALU consumer at distance 2 (e.g. ADD $1, $2, $3; <INST>; ADD $4, $1,
$2)
This screenshot represents test two which includes addi t0, zero, 4.. addi t1, zero, -1.. add t2,
zero, t0.. add t3, t1, zero.

7|Page
iii) Load producer to ALU consumer distance 2 (e.g. LW $1, 0($10); <INST>; ADD $5, $1, $r2)
This screenshot represents test 13 which includes lw t0, 24(zero).. nop.. add t1, t0, t0

iv) ALU producer to BEQ consumer at distance 2 (e.g. ADD $1, $2, $3; <INST>; BEQ $1, $2,
label)
This screenshot represents test 7 which includes addi t0,zero,35.. nop.. beq t0, zero, 35. You
can see that the program correctly does not branch after the addi if you look at the
if_pc_plus_4, it does not move irregularly.

8|Page
d. [Part 5b] Implement a hazard detection unit (using VHDL) to support the following data dependent
cases. Give simulation screenshots of correct forwarding for the cases described in the lab manual. (6
pts)

This screenshot represents a jump/branch hazard. It takes place at the end of the program when
the branch IS TAKEN. You can see the hazard detection unit values at the bottom of the
waveform.

This screenshot represents two separate hazards. A jump/branch hazard during a jump first,
and then a Load use hazard during the lw and addi at the beginning of the loop that it just jumped
back to.

9|Page
e. [Part 5c] Connect your forwarding and hazard detection units to your pipelined processor and provide
a simulation screenshot showing that your pipeline correctly executes the given test program. (6 pts)
This screenshot shows the end of the waveform of the program showing that it branches to exit at
the end, and it also shows the dmem file at the end which shows that the program wrote correctly
and did not write anything extra.

10 | P a g e