ALGORITHM

1. Here we design the VHDL module for multiplication of two 16-bit numbers.
2. According to program and logic flow of state diagram we create
ARITH_Module.vhd module as our synthesis module.
3. The MultUB_STD_C42_RC000 is the main module and UBPPG_15_0_15_0
(Partial Product generator), C42TR_15_0_16_1_1000 (Wallence tree using Half
Adder, Full Adder and 4:2 Compressor) and UBRCA_31_4_31_0 (Ripple Carry
Adder) are sub-module as shown in tree diagram in Xilinx ISE design tool
13.1.All these modules are implemented in ARITH_Module.vhd
4. I defined two 16 bits input and one 32 bit output. Inputs are 16 bit Multiplier and
Multiplicand and Output is 32 bit product.
5. Partial products are generated using AND gate. Each bit of multiplier is ANDed
with each bit of multiplicand. This Produces 16*16 = 256 partial products.
While (i <= 15)
{
While (j<=15)
{
PPij=Ai*Bj
J++
}
i++
}
6. Now as partial products are generated our next task is to reduce them using
Wallence tree.
7. Wallence tree is implemented in three stages.
8. Wallace Tree multiplier accumulates partial products column-wise into four, three
and two bits and gives them to 4:2 compressors, Full-Adders and Half Adders
respectively to reduce as Sum, Carry bits. Any bit that does not belong to these
adders is bypassed to next stage and carry is propagated to one-bit higher order
column of next stage. This process is continued until the stage height is reduced to
2 rows.
9. In first stage four reduction blocks are used.
A. 1st reduction block: PP[15:0], PP[16:1] ,PP[17:2], PP[18:3] are added to
generate two rows of sum and carry.

component UB4_2Comp_15_0_16000
port(
C : out std_logic_vector(18 downto 2);
S : out std_logic_vector(18 downto 0);
IN0 : in std_logic_vector(15 downto 0);
IN1 : in std_logic_vector(16 downto 1);
IN2 : in std_logic_vector(17 downto 2);
IN3 : in std_logic_vector(18 downto 3));
end component;

B. 2nd reduction block: PP[19:4], PP[20:5] ,PP[21:6], PP[22:7] are added to

generate two rows of sum and carry.

component UB4_2Comp_19_4_20000
port(
C : out std_logic_vector(22 downto 6);
S : out std_logic_vector(22 downto 4);
IN0 : in std_logic_vector(19 downto 4);
IN1 : in std_logic_vector(20 downto 5);
IN2 : in std_logic_vector(21 downto 6);
IN3 : in std_logic_vector(22 downto 7));
end component;

C. 3rd reduction block: PP[23:8], PP[24:9] ,PP[25:10], PP[26:11] are added to

generate two rows of sum and carry

component UB4_2Comp_23_8_24000
port(
C : out std_logic_vector(26 downto 10);
S : out std_logic_vector(26 downto 8);
 IN0 : in std_logic_vector(23 downto 8);
IN1 : in std_logic_vector(24 downto 9);
IN2 : in std_logic_vector(25 downto 10);
IN3 : in std_logic_vector(26 downto 11));
end component;

D. 4th reduction block: PP[27:12], PP[28:13] ,PP[29:14], PP[30:15] are added to

generate two rows of sum and carry.

component UB4_2Comp_27_12_2000
port(
C : out std_logic_vector(30 downto 14);
S : out std_logic_vector(30 downto 12);
IN0 : in std_logic_vector(27 downto 12);
IN1 : in std_logic_vector(28 downto 13);
IN2 : in std_logic_vector(29 downto 14);
IN3 : in std_logic_vector(30 downto 15));
end component;

10. In 2nd stage two reduction blocks are used.

A. 5th reduction block: Result of 1st and 2nd reduction blocks are added to generate
two rows of sum and carry.

component UB4_2Comp_18_0_18000
port(
C : out std_logic_vector(23 downto 3);
S : out std_logic_vector(22 downto 0);
IN0 : in std_logic_vector(18 downto 0);
IN1 : in std_logic_vector(18 downto 2);
IN2 : in std_logic_vector(22 downto 4);
IN3 : in std_logic_vector(22 downto 6));
end component;
B. 6th reduction block: Result of 3rd and 4th reduction blocks are added to generate
two rows of sum and carry.

component UB4_2Comp_26_8_26000
port(
C : out std_logic_vector(31 downto 11);
S : out std_logic_vector(30 downto 8);
IN0 : in std_logic_vector(26 downto 8);
IN1 : in std_logic_vector(26 downto 10);
IN2 : in std_logic_vector(30 downto 12);
IN3 : in std_logic_vector(30 downto 14));
end component;

11. In 3rd stage one reduction blocks is used.

7th reduction block: Result of 5th and 6th reduction blocks are added to generate
two rows of sum and carry.

component UB4_2Comp_18_0_18000
port(
C : out std_logic_vector(23 downto 3);
S : out std_logic_vector(22 downto 0);
IN0 : in std_logic_vector(18 downto 0);
IN1 : in std_logic_vector(18 downto 2);
IN2 : in std_logic_vector(22 downto 4);
IN3 : in std_logic_vector(22 downto 6));
end component;

12. Now as we have reduced all the partial products in two rows we can add them
easily using Ripple Carry adder to generate output product. This is the last step of
this project
13. Finally to test the result we create a new source as a test bench as
Multiplier_15_0_tb.vhd. Here we give various input and check the behavioral
result.