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Topstar Digital technologies Co.,LTD


D D

15. PCH RTC/SATA/SPI/HDA/LPC


01. Title 16. PCH PCIE/CLK/SMBUS
Board name: MotherBoard Schematic 02. Sys block 17. PCH DMI/FDI/PWRGD
03. PWR block 18. PCH Display
Project name: F42 04. Notes 19. PCH PCI/USB
Version: VerC 05. Modify and history 20. PCH GPIO
06. Ivy Bridge DMI/FDI/PCIE21. PCH PWR 1/2
Initial Date: 07.Ivy Bridge CLK/MISC 22. PCH PWR 2/2
08. Ivy Bridge DDR3 23. PCH GND
09. Ivy Bridge Vcore/VTT 24. LVDS&Inverter CONN
10. Ivy Bridge VGFX/VDDQ 25. HDMI CONN
C
11. Ivy Bridge GND 26. CRT Interface C
12. Ivy Bridge Reserved 27. SATA HDD&ODD
13. DDR3 CHA SODIMM0 28. TP Module&BD CONN
14. DDR3 CHB SODIMM0

Topstar Confidential

Hardware drawing by: Hardware check by: EMI Check by:

B B
Power drawing by: Power check by:

Manager Sign by:

A A
TOPSTAR TECHNOLOGY
杨华明(Sky Yang)
Page Name Title(Cover Page)
Size Project Name Rev
A3 CL42 EVT
A
Date: Sunday, April 07, 2013 Sheet 1 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

Topstar Confidential
ShenZhen Topstar Industry Co.,LTD
D D

CL341 SYSTEM BLOCK Ver:C

CHA DDR3 SODIMM0


DDR3 1333/1600 NA
IVY Bridage
BGA1023
Backlight CHB DDR3 SODIMM1
Connector
+VCC_CORE,+VccGFX DDR3 1333/1600 1333/1600
+VDC +V1.5, +V1.8S,
+V0.75S,+V1.5,+V3.3S
+V1.05S
+VCCSA
PECI3.0
+V0.75S,+V1.5,+V3.3S

LVDS FDI GEN 2 DMI*4


LED Panel
+V3.3S RJ45
BIOS SPI RTL8105E/RTL8111E
C 32Mbit
PCIE 1X +V3.3S,+V3.3AL C
+V3.3S
RJ45
Panther Point
989 FCBGA
SATA ODD
+V3.3A,+V3.3S,+V1.5S, +V5S
+V1.05S,+V1.8S,
PCIE mini Card HDMI +V5A,+V5S
+V5S
S-ATA
2.5" HDD SD/MMC/MS CARD

+V5S,+V3.3S
Card Reader
USB2.0 RTS5138-GR
+V3.3S,+V3.3AL
PCIE 1X LPC
AZALIA
USB1.1/2.0

BLUE
USB PORT0/1 TOOTH(V2.1) Camera KB Controller/EC PECI3.0
+V5AL BCM-2046/CCOM 1.3M/2.0M
B MODULE ENE 3930 B
+V3.3AL +V3.3S +V3.3AL,+V3.3S L

R
MiC
AZALIA
ALC269
+V5S,+V3.3S

LID
LED/TouchPAD/Button/
DAUGHTER BOARD

KB Matrix
A A
TOPSTAR TECHNOLOGY
杨华明(Sky Yang)
Page Name Sys block
Size Project Name Rev
A3 CL42 EVT
A
Date: Sunday, April 07, 2013 Sheet 2 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A
TOPSTAR TECHNOLOGY
杨华明(Sky Yang)
Page Name PWR Block
Size Project Name Rev
A3 CL42 EVT
A
Date: Wednesday, January 09, 2013 Sheet 3 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A
TOPSTAR TECHNOLOGY
杨华明(Sky Yang)
Page Name Notes
Size Project Name Rev
A3 CL42 EVT
A
Date: Wednesday, January 09, 2013 Sheet 4 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

2012-5-16 VerA First Release.

D D

C C

B B

A A
TOPSTAR TECHNOLOGY
杨华明(Sky Yang)
Page Name Modify and history
Size Project Name Rev
A3 CL42 EVT
A
Date: Wednesday, January 09, 2013 Sheet 5 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

+V1.05S
+V1.05S 7,9,15,16,17,21,22,30,41,44,47
U16A
G3 PEG_IRCOMP_R R195 24.9,1%
PEG_ICOMPI G1 R0402
DMI_TXN0 M2 PEG_ICOMPO G4
17 DMI_TXN0 DMI_TXN1 P6 DMI_RX#[0] PEG_RCOMPO Layout notice:
17 DMI_TXN1 DMI_TXN2 P1 DMI_RX#[1]
17 DMI_TXN2 DMI_TXN3 P10 DMI_RX#[2] H22
17 DMI_TXN3 DMI_RX#[3] PEG_RX#[0] J21
D DMI_TXP0 N3 PEG_RX#[1] B22 D
17 DMI_TXP0 DMI_TXP1 P7 DMI_RX[0] PEG_RX#[2] D21
17 DMI_TXP1 DMI_RX[1] PEG_RX#[3]

DMI
DMI_TXP2 P3 A19
17 DMI_TXP2 DMI_TXP3 P11 DMI_RX[2] PEG_RX#[4] D17
17 DMI_TXP3 DMI_RX[3] PEG_RX#[5] B14
DMI_RXN0 K1 PEG_RX#[6] D13
17 DMI_RXN0 DMI_RXN1 M8 DMI_TX#[0] PEG_RX#[7] A11
17 DMI_RXN1 DMI_RXN2 N4 DMI_TX#[1] PEG_RX#[8] B10
17 DMI_RXN2 DMI_RXN3 R2 DMI_TX#[2] PEG_RX#[9] G8
17 DMI_RXN3 DMI_TX#[3] PEG_RX#[10] A8
DMI_RXP0 K3 PEG_RX#[11] B6
17 DMI_RXP0 DMI_RXP1 M7 DMI_TX[0] PEG_RX#[12] H8
17 DMI_RXP1 DMI_RXP2 P4 DMI_TX[1] PEG_RX#[13] E5
17 DMI_RXP2 DMI_RXP3 T3 DMI_TX[2] PEG_RX#[14] K7
17 DMI_RXP3 DMI_TX[3] PEG_RX#[15]
K22
PEG_RX[0] K19
PEG_RX[1] C21
17 FDI_TXN[7:0] FDI_TXN0 U7 PEG_RX[2] D19
FDI_TXN1 W11 FDI0_TX#[0] PEG_RX[3] C19
C FDI_TXN2 W1 FDI0_TX#[1] PEG_RX[4] D16 C
FDI_TXN3 AA6 FDI0_TX#[2] PEG_RX[5] C13
FDI_TXN4 W6 FDI0_TX#[3] PEG_RX[6] D12

PCI EXPRESS -- GRAPHICS


FDI_TXN5 V4 FDI1_TX#[0] PEG_RX[7] C11
FDI_TXN6 Y2 FDI1_TX#[1] PEG_RX[8] C9
FDI_TXN7 AC9 FDI1_TX#[2] PEG_RX[9] F8
FDI1_TX#[3] PEG_RX[10]

Intel(R) FDI
C8
PEG_RX[11] C5
17 FDI_TXP[7:0] FDI_TXP0 U6 PEG_RX[12] H6
FDI_TXP1 W10 FDI0_TX[0] PEG_RX[13] F6
FDI_TXP2 W3 FDI0_TX[1] PEG_RX[14] K6
FDI_TXP3 AA7 FDI0_TX[2] PEG_RX[15]
FDI_TXP4 W7 FDI0_TX[3] G22
FDI_TXP5 T4 FDI1_TX[0] PEG_TX#[0] C23
FDI_TXP6 AA3 FDI1_TX[1] PEG_TX#[1] D23
FDI_TXP7 AC8 FDI1_TX[2] PEG_TX#[2] F21
FDI1_TX[3] PEG_TX#[3] H19
AA11 PEG_TX#[4] C17
17 FDI_FSYNC0 AC12 FDI0_FSYNC PEG_TX#[5] K15
17 FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] F17
U11 PEG_TX#[7] F14
B B
17 FDI_INT FDI_INT PEG_TX#[8] A15
AA10 PEG_TX#[9] J14
17 FDI_LSYNC0 AG8 FDI0_LSYNC PEG_TX#[10] H13
17 FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] M10
PEG_TX#[12] F10
+V1.05S PEG_TX#[13] D9
PEG_TX#[14] J4
R206 DP_COMP AF3 PEG_TX#[15]
24.9,1% AD2 eDP_COMPIO F22
R0402 AG11 eDP_ICOMPO PEG_TX[0] A23
Layout notice: eDP_HPD# PEG_TX[1] D24
PEG_TX[2] E21
AG4 PEG_TX[3] G19
AF4 eDP_AUX# PEG_TX[4] B18
eDP_AUX PEG_TX[5] K17
PEG_TX[6]
eDP

G17
AC3 PEG_TX[7] E14 TOPSTAR TECHNOLOGY
AC4 eDP_TX#[0] PEG_TX[8] C15
eDP_TX#[1] PEG_TX[9] Robin
AE11 K13
AE7 eDP_TX#[2] PEG_TX[10] G13 Page Name
A Ivy Bridge DMI/FDI/PCIE A
eDP_TX#[3] PEG_TX[11] K10
AC1 PEG_TX[12] G10 Size Project Name Rev
AA4 eDP_TX[0] PEG_TX[13] D8 A4 CL42 EVT
eDP_TX[1] PEG_TX[14] A
AE10 K4
AE6 eDP_TX[2] PEG_TX[15] Date: Wednesday, January 09, 2013 Sheet 6 of 51
eDP_TX[3] PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
IC,IVB_2CBGA,0P7 to others or used for any purpose other than that for which it was obtained without
BGA1023_31X24 the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

+V3.3S 14,15,16,17,18,19,20,21,22,24,25,29,30,31,32,33,34,35,40,41,42,43,44,45,47
+V1.05S 6,9,15,16,17,21,22,30,41,44,47
+V1.5 14,40,45
+V3.3SB 15,17,20,22,28,31,33,35,37,38,39,45
+V3.3AL 15,16,17,19,20,22,24,28,31,33,40,43,45
+V1.5S_CPU_VDDQ
差异1:Processor type
+V1.5S 10,21,31,45
Sandy Bridge: Output High;
Ivy Bridge: Output low

D U16B D

J3
BCLK H2 CLK_EXP_P 16
BCLK# CLK_EXP_N 16

MISC

CLOCKS
F49 +V1.05S
20 H_SNB_IVB# PROC_SELECT# AG3 CLK_DP_P_R R492 1K R0402
DPLL_REF_CLK AG1 CLK_DP_N_R R496 1K R0402
C57 DPLL_REF_CLK#
T17 PROC_DETECT#
ns

ICTP
T69 C49
ns CATERR#

THERMAL
+V1.05S R154 0 ns H_PECI_R A48
ICTP AT30 CPU_DRAMRST#
20 H_PECI PECI SM_DRAMRST#
R0402
33 H_PECI_EC R155 47 DG要求R147为43 ohm 5%

DDR3
MISC
R0402 BF44 SM_RCOMP_0 R244 140ohm 1%R0402
VR_PROCHOT# R147 56 C45 SM_RCOMP[0] BE43 SM_RCOMP_1 R243 25.5ohm 1%
R0402
R0402 PROCHOT# SM_RCOMP[1] BG43 SM_RCOMP_2 R236 200,1% R0402
R241 SM_RCOMP[2]
75
R0402 D45
20,30 THERMTRIP# THERMTRIP#
R248
1K +V1.05S
R0402
N53
C VR_PROCHOT# 44 PRDY# N55 PREQ# R185 51ns R0402 C
PREQ#
3

L56 TCK R190 51 ns R0402


1 Q11 TCK L55 TMS R191 51 ns R0402
TMS

PWR MANAGEMENT
LMBT3904LT1G J58 TRST# R193 51 ns R0402
TRST#
SOT23

JTAG & BPM


2

R156 0 H_PM_SYNC_R C48 M60 TDI R189 51 ns R0402


17 H_PM_SYNC PM_SYNC TDI L59 TDO
R0402 R194 51 ns R0402
33 EC_PROCHOT# TDO
+V3.3S
R266 R171 0 H_CPUPWRGD_R B46
20 H_CPUPWRGD UNCOREPWRGOOD K58 DBR#
10K R0402 R146 1K R0402
R172 10K DBR#
R0402
R0402
+V3.3SB SM_DRAMPWROK BE45 G58
SM_DRAMPWROK BPM#[0] E55
BPM#[1] E59
BPM#[2] G55 +V1.5
BPM#[3] G59
PLT_RST#_R D44 BPM#[4] H60
RESET# BPM#[5] J59
BPM#[6] J61 R268
BPM#[7] 1K
R0402
R695 0
R0402 R265 0
ns Place near to DIMM ns
R267 Q13 R0402
+V3.3AL +V1.5S IC,IVB_2CBGA,0P7 1K L2N7002LT1G
B BGA1023_31X24 SOT23 B
R0402
3 2 R264 0 CPU_DRAMRST#
14 DDR3_DRAMRST# R0402
C363 R696 Note: Not mount R696 when S3 power save
0.1uF/10V,X7R 200,1% +V3.3AL R720 1K R0402
R530 R528 C0402 R0402 Note: ns R262

1
10K 200,1% ns S3 power save option: R539:2.37K, R234:2K R278 0 R0402 4.99K,1%
No S3 power save option: R539:0ohm, R234:ns 16 DRAMRST_CNTRL_PCH
R0402 R0402 U20 R0402
ns R297 1K C173
33 EC_DRAMRST_CNTRL_PCH
5

R0402
R531 0 R0402 1 VCC 470pF/25V,X7R
17 PM_DRAM_PWRGD 4 C0402
R539 2.37K,1% SM_DRAMPWROK
R534 0 R0402 2 R0402 TU142 VerB: Changed R297 to 1k and ns R720 for DRAMRST#
17,33,43 MAIN_PWROK GND
SN74AHC1G08DBV
isolate circuit control in Deep S3 2011-12-20
3

SOT23_5 R234
DRAMRST_CNTRL 10
2K,1%
R0402
Note:
When implement S3 power save function, need to mount +V3.3AL
S3_Power_Save option +V1.05S
C0402
C177 0.1uF/10V,X7R
ns
R246
75
U2 R0402
5

ns
A R710 0 1 VCC A
R0402 4 R247 PLT_RST#_R TOPSTAR TECHNOLOGY
2 2.2K
19,31,33,34 BUF_PLT_RST# GND Robin
R0402
SN74AHC1G08DBV Page Name Ivy Bridge CLK/MISC
3

SOT23_5 R238
1.05K 1% Size Project Name Rev
R0402 A3 CL42 EVT
A
R363 0 Date: Wednesday, January 09, 2013 Sheet 7 of 51
ns R0402 PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

U16C
U16D

AG6
AJ6 SA_DQ[0] AU36 14 MB_DATA[63:0] AL4
D MB_DATA0 D
AP11 SA_DQ[1] SA_CK[0] AV36 MB_DATA1 AL1 SB_DQ[0] BA34
SA_DQ[2] SA_CK#[0] SB_DQ[1] SB_CK[0] M_CLK_DDR2 14
AL6 AY26 MB_DATA2 AN3 AY34
AJ10 SA_DQ[3] SA_CKE[0] MB_DATA3 AR4 SB_DQ[2] SB_CK#[0] AR22 M_CLK_DDR#2 14
AJ8 SA_DQ[4] AK4 SB_DQ[3] SB_CKE[0] M_CKE2 14
MB_DATA4
AL8 SA_DQ[5] MB_DATA5 AK3 SB_DQ[4]
AL7 SA_DQ[6] MB_DATA6 AN4 SB_DQ[5]
AR11 SA_DQ[7] MB_DATA7 AR1 SB_DQ[6]
AP6 SA_DQ[8] AT40 MB_DATA8 AU4 SB_DQ[7]
AU6 SA_DQ[9] SA_CK[1] AU40 MB_DATA9 AT2 SB_DQ[8] BA36
AV9 SA_DQ[10] SA_CK#[1] BB26 AV4 SB_DQ[9] SB_CK[1] BB36 M_CLK_DDR3 14
MB_DATA10
AR6 SA_DQ[11] SA_CKE[1] MB_DATA11 BA4 SB_DQ[10] SB_CK#[1] BF27 M_CLK_DDR#3 14
SA_DQ[12] SB_DQ[11] SB_CKE[1] M_CKE3 14
AP8 MB_DATA12 AU3
AT13 SA_DQ[13] MB_DATA13 AR3 SB_DQ[12]
AU13 SA_DQ[14] MB_DATA14 AY2 SB_DQ[13]
BC7 SA_DQ[15] MB_DATA15 BA3 SB_DQ[14]
BB7 SA_DQ[16] BB40 MB_DATA16 BE9 SB_DQ[15]
BA13 SA_DQ[17] SA_CS#[0] BC41 MB_DATA17 BD9 SB_DQ[16] BE41
BB11 SA_DQ[18] SA_CS#[1] BD13 SB_DQ[17] SB_CS#[0] BE47 M_CS#2 14
MB_DATA18
SA_DQ[19] SB_DQ[18] SB_CS#[1] M_CS#3 14
BA7 MB_DATA19 BF12
BA9 SA_DQ[20] MB_DATA20 BF8 SB_DQ[19]
BB9 SA_DQ[21] MB_DATA21 BD10 SB_DQ[20]
AY13 SA_DQ[22] MB_DATA22 BD14 SB_DQ[21]
AV14 SA_DQ[23] AY40 MB_DATA23 BE13 SB_DQ[22]
AR14 SA_DQ[24] SA_ODT[0] BA41 MB_DATA25 BF16 SB_DQ[23] AT43
AY17 SA_DQ[25] SA_ODT[1] BE17 SB_DQ[24] SB_ODT[0] BG47 M_ODT2 14
MB_DATA24
SA_DQ[26] SB_DQ[25] SB_ODT[1] M_ODT3 14
AR19 MB_DATA27 BE18
BA14 SA_DQ[27] MB_DATA26 BE21 SB_DQ[26]
AU14 SA_DQ[28] MB_DATA28 BE14 SB_DQ[27]
C BB14 SA_DQ[29] MB_DATA29 BG14 SB_DQ[28] C
BB17 SA_DQ[30] AL11 MB_DATA30 BG18 SB_DQ[29]
SA_DQ[31] SA_DQS#[0] SB_DQ[30] MB_DQS#[7:0] 14
BA45 AR8 MB_DATA31 BF19 AL3 MB_DQS#0
AR43 SA_DQ[32] SA_DQS#[1] AV11 MB_DATA32 BD50 SB_DQ[31] SB_DQS#[0] AV3 MB_DQS#1
AW48 SA_DQ[33] SA_DQS#[2] AT17 MB_DATA33 BF48 SB_DQ[32] SB_DQS#[1] BG11 MB_DQS#2
BC48 SA_DQ[34] SA_DQS#[3] AV45 MB_DATA34 BD53 SB_DQ[33] SB_DQS#[2] BD17 MB_DQS#3
BC45 SA_DQ[35] SA_DQS#[4] AY51 MB_DATA35 BF52 SB_DQ[34] SB_DQS#[3] BG51 MB_DQS#4
SA_DQ[36] SA_DQS#[5] SB_DQ[35] SB_DQS#[4]
DDR SYSTEM MEMORY A

AR45 AT55 MB_DATA36 BD49 BA59 MB_DQS#5


SA_DQ[37] SA_DQS#[6] SB_DQ[36] SB_DQS#[5]

DDR SYSTEM MEMORY B


AT48 AK55 MB_DATA37 BE49 AT60 MB_DQS#6
AY48 SA_DQ[38] SA_DQS#[7] MB_DATA38 BD54 SB_DQ[37] SB_DQS#[6] AK59 MB_DQS#7
BA49 SA_DQ[39] MB_DATA39 BE53 SB_DQ[38] SB_DQS#[7]
AV49 SA_DQ[40] MB_DATA40 BF56 SB_DQ[39]
BB51 SA_DQ[41] MB_DATA41 BE57 SB_DQ[40]
AY53 SA_DQ[42] MB_DATA42 BC59 SB_DQ[41]
BB49 SA_DQ[43] MB_DATA43 AY60 SB_DQ[42]
AU49 SA_DQ[44] AJ11 MB_DATA44 BE54 SB_DQ[43]
BA53 SA_DQ[45] SA_DQS[0] AR10 MB_DATA45 BG54 SB_DQ[44]
SA_DQ[46] SA_DQS[1] SB_DQ[45] MB_DQS[7:0] 14
BB55 AY11 MB_DATA46 BA58 AM2 MB_DQS0
BA55 SA_DQ[47] SA_DQS[2] AU17 MB_DATA47 AW59 SB_DQ[46] SB_DQS[0] AV1 MB_DQS1
AV56 SA_DQ[48] SA_DQS[3] AW45 MB_DATA48 AW58 SB_DQ[47] SB_DQS[1] BE11 MB_DQS2
AP50 SA_DQ[49] SA_DQS[4] AV51 MB_DATA49 AU58 SB_DQ[48] SB_DQS[2] BD18 MB_DQS3
AP53 SA_DQ[50] SA_DQS[5] AT56 MB_DATA50 AN61 SB_DQ[49] SB_DQS[3] BE51 MB_DQS4
AV54 SA_DQ[51] SA_DQS[6] AK54 MB_DATA51 AN59 SB_DQ[50] SB_DQS[4] BA61 MB_DQS5
AT54 SA_DQ[52] SA_DQS[7] MB_DATA52 AU59 SB_DQ[51] SB_DQS[5] AR59 MB_DQS6
AP56 SA_DQ[53] MB_DATA53 AU61 SB_DQ[52] SB_DQS[6] AK61 MB_DQS7
AP52 SA_DQ[54] MB_DATA54 AN58 SB_DQ[53] SB_DQS[7]
AN57 SA_DQ[55] MB_DATA55 AR58 SB_DQ[54]
AN53 SA_DQ[56] MB_DATA56 AK58 SB_DQ[55]
AG56 SA_DQ[57] MB_DATA57 AL58 SB_DQ[56]
B AG53 SA_DQ[58] MB_DATA58 AG58 SB_DQ[57] B
AN55 SA_DQ[59] MB_DATA59 AG59 SB_DQ[58]
AN52 SA_DQ[60] BG35 MB_DATA60 AM60 SB_DQ[59]
AG55 SA_DQ[61] SA_MA[0] BB34 AL59 SB_DQ[60] BF32 MB_B_A[15:0] 14
MB_DATA61 MB_B_A0
AK56 SA_DQ[62] SA_MA[1] BE35 MB_DATA62 AF61 SB_DQ[61] SB_MA[0] BE33 MB_B_A1
SA_DQ[63] SA_MA[2] BD35 MB_DATA63 AH60 SB_DQ[62] SB_MA[1] BD33 MB_B_A2
SA_MA[3] AT34 SB_DQ[63] SB_MA[2] AU30 MB_B_A3
SA_MA[4] AU34 SB_MA[3] BD30 MB_B_A4
SA_MA[5] BB32 SB_MA[4] AV30 MB_B_A5
BD37 SA_MA[6] AT32 SB_MA[5] BG30 MB_B_A6
BF36 SA_BS[0] SA_MA[7] AY32 BG39 SB_MA[6] BD29 MB_B_A7
BA28 SA_BS[1] SA_MA[8] AV32 14 MB_B_BS0 BD42 SB_BS[0] SB_MA[7] BE30 MB_B_A8
SA_BS[2] SA_MA[9] BE37 14 MB_B_BS1 AT22 SB_BS[1] SB_MA[8] BE28 MB_B_A9
SA_MA[10] 14 MB_B_BS2 SB_BS[2] SB_MA[9]
BA30 BD43 MB_B_A10
SA_MA[11] BC30 SB_MA[10] AT28 MB_B_A11
BE39 SA_MA[12] AW41 SB_MA[11] AV28 MB_B_A12
BD39 SA_CAS# SA_MA[13] AY28 AV43 SB_MA[12] BD46 MB_B_A13
SA_RAS# SA_MA[14] 14 MB_B_CAS# SB_CAS# SB_MA[13]
AT41 AU26 BF40 AT26 MB_B_A14
SA_WE# SA_MA[15] 14 MB_B_RAS# BD45 SB_RAS# SB_MA[14] AU22 MB_B_A15
14 MB_B_WE# SB_WE# SB_MA[15]

IC,IVB_2CBGA,0P7
BGA1023_31X24 IC,IVB_2CBGA,0P7
BGA1023_31X24

A A
TOPSTAR TECHNOLOGY
Robin
Page Name Ivy Bridge DDR3
Size Project Name Rev
A3 CL42 EVT
A
Date: Sunday, April 07, 2013 Sheet 8 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

U16F POWER +VCC_CORE


+V1.05S
44
6,7,15,16,17,21,22,30,41,44,47

+VCC_CORE +V1.05S

ULV(17W):33A
LV(25W):43A
VCCIO[1]
AF46 Max: 8.5A 8.5A
SV(35W):53A AG48
VCCIO[3] AG50
A26 VCCIO[4] AG51 C346 C345 C150 C148 C348 C147 C146 C151 C149 C267
A29 VCC[1] VCCIO[5] AJ17 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805
A31 VCC[2] VCCIO[6] AJ21 10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V
A34 VCC[3] VCCIO[7] AJ25
D VCC[4] VCCIO[8] D
A35 AJ43
A38 VCC[5] VCCIO[9] AJ47
A39 VCC[6] VCCIO[10] AK50
A42 VCC[7] VCCIO[11] AK51 CRB 上10个10uF,26个1uF,两个330uF
C26 VCC[8] VCCIO[12] AL14
C27 VCC[9] VCCIO[13] AL15
C32 VCC[10] VCCIO[14] AL16
C34 VCC[11] VCCIO[15] AL20
C37 VCC[12] VCCIO[16] AL22
C39 VCC[13] VCCIO[17] AL26
C42 VCC[14] VCCIO[18] AL45
D27 VCC[15] VCCIO[19] AL48 C145 C353 C349 C347 C275 C273 C270 C350 C152 C274 C344 C276
D32 VCC[16] VCCIO[20] AM16 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402
D34 VCC[17] VCCIO[21] AM17 1uf/10V 1uf/10V 1uf/10V 1uf/10V 1uf/10V 1uf/10V 1uf/10V 1uf/10V 1uf/10V 1uf/10V 1uf/10V 1uf/10V
D37 VCC[18] VCCIO[22] AM21
D39 VCC[19] PEG IO AND DDR IO VCCIO[23] AM43
D42 VCC[20] VCCIO[24] AM47
E26 VCC[21] VCCIO[25] AN20
E28 VCC[22] VCCIO[26] AN42
E32 VCC[23] VCCIO[27] AN45 20*10uF+12*1uF
E34 VCC[24] VCCIO[28] AN48
E37 VCC[25] VCCIO[29]
E38 VCC[26]
CORE SUPPLY

F25 VCC[27]
F26 VCC[28]
F28 VCC[29]
F32 VCC[30]
F34 VCC[31]
F37 VCC[32] AA14
F38 VCC[33] VCCIO[30] AA15
F42 VCC[34] VCCIO[31] AB17
C VCC[35] VCCIO[32] C
G42 AB20
H25 VCC[36] VCCIO[33] AC13 +VCC_CORE
H26 VCC[37] VCCIO[34] AD16
H28 VCC[38] VCCIO[35] AD18
H29 VCC[39] VCCIO[36] AD21 CRB 上35个2.2uF,45个22uF,6个470uF
H32 VCC[40] VCCIO[37] AE14
H34 VCC[41] VCCIO[38] AE15
H35 VCC[42] VCCIO[39] AF16
H37 VCC[43] VCCIO[40] AF18 C129 C135 C115 C336 C337 C338 C141 C111 C131 C136 C110 C112
H38 VCC[44] VCCIO[41] AF20 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805
H40 VCC[45] VCCIO[42] AG15 10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V
J25 VCC[46] VCCIO[43] AG16
J26 VCC[47] VCCIO[44] AG17
J28 VCC[48] VCCIO[45] AG20
J29 VCC[49] VCCIO[46] AG21
J32 VCC[50] VCCIO[47] AJ14
J34 VCC[51] VCCIO[48] AJ15
J35 VCC[52] VCCIO[49]
J37 VCC[53]
J38 VCC[54] C138 C341 C342 C343 C117 C118 C122 C328 C123 C119 C329 C130
J40 VCC[55] +V1.05S C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402
J42 VCC[56] 1uf/10V 1uf/10V 1uf/10V 1uf/10V 1uf/10V 1uf/10V 1uf/10V 1uf/10V 1uf/10V 1uf/10V 1uf/10V 1uf/10V
K26 VCC[57] W16 R197 0
K27 VCC[58] VCCIO50 W17 R0402
K29 VCC[59] VCCIO51
K32 VCC[60]
K34 VCC[61]
K35 VCC[62] Processor 1.05V Quiet rail for DDR block,
K37 VCC[63] BGA only
K39 VCC[64]
K42 VCC[66] BC22 T84 ICTP ns C157 C170 C171 C165
B VCC[67] VCCIO_SEL B
L25 +V1.05S C0402 C0402 C0402 C0402
L28 VCC[68] 1uf/10V 1uf/10V 1uf/10V 1uf/10V
L33
L36
VCC[69]
VCC[70]
0.4A
L40 VCC[71] C121
N26 VCC[72] C0402
N30 VCC[73] AM25 1uf/10V +V1.05S
QUIET
RAILS

N34 VCC[74] VCCPQE[1] AN22


N38 VCC[75] VCCPQE[2]
VCC[76]

R721 R148
75 130,1%
R0402 R0402

A44 R140 45.3 1% R0402


VIDALERT# B43 R722 0 R0402 VR_SVID_ALERT# 44
VIDSCLK VR_SVID_CLK 44
SVID

C44 R723 0 R0402


VIDSOUT VR_SVID_DATA 44
请注意走线 +VCC_CORE

R141
100,1%
R0402

F43 VCCSENSE_R R149 0 R0402


VCC_SENSE VCCSENSE 44
G43 R150 0 R0402
SENSE LINES

VSSSENSE_R
VSS_SENSE VSSSENSE 44

A A
+V1.05S R741 10 R142
R0402 100,1% TOPSTAR TECHNOLOGY
AN16 R204 0 R0402 R0402
VCCIO_SENSE VCCP_SENSE 41 Robin
AN17 R205 0 R0402
VSS_SENSE_VCCIO VSSP_SENSE
Page Name Ivy Bridge Vcore/VTT
Size Project Name Rev
R742 Custom CL42 EVT
A
10
IC,IVB_2CBGA,0P7 Date: Wednesday, January 09, 2013 Sheet 9 of 51
R0402
BGA1023_31X24 PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

+V1.5 7,14,40,45
+V1.5S
+V1.5S_CPU_VDDQ
+VCCSA 42

+VGFX
U16G POWER R270
1K,1%
+VDC
+VGFX
24,37,39,40,41,44,47
44

+V1.5S 7,21,31,45
R0402 +V1.8S 20,21,40,45
GT2: 33A
GT1: 20A CRB 6颗22uF,6颗10uF,11颗1uF,2颗470uF AY43 SM_VREF R282 0 R0402 SM_VREF_R
AA46 SM_VREF

VREF
AB47 VAXG[1] C178
C327 C127 C352 C134 C143 C144 AB50 VAXG[2] BE7 DDR_WR_VREF01 R255 C0402 R269
C0805 C0805 C0805 C0805 C0805 C0805 AB51 VAXG[3] SA_DIMM_VREFDQ BG7 DDR_WR_VREF02 100K 0.1uF/10V,X7R 1K,1%
10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V AB52 VAXG[4] SB_DIMM_VREFDQ R0402
D R0402 D
AB53 VAXG[5] ns
AB55 VAXG[6]
AB56 VAXG[7]
AB58 VAXG[8]
AB59 VAXG[9]
AC61 VAXG[10]
C409 C358 C354 C356 C153 C154 AD47 VAXG[11]
C0805 C0805 C0402 C0402 C0805 C0805 AD48 VAXG[12] +V1.5S DDR_WR_VREF01
10uf/6.3V 10uf/6.3V 0.22uF/10V,X7R 0.01uF/16V,X7R 10uf/6.3V 10uf/6.3V AD50 VAXG[13] CRB 8颗10uF,10颗1uF,1颗330uF
AD51 VAXG[14] AJ28 Max: 5A
VAXG[15]

- 1.5V RAILS
AD52 VDDQ[1] AJ33 R728 1K ns
AD53 VAXG[16] VDDQ[2] AJ36 R0402
AD55 VAXG[17] VDDQ[3] AJ40 C174 C175 C168 C167 C166 C163
AD56 VAXG[18] VDDQ[4] AL30 C0805 C0805 C0402 C0402 C0402 C0402
AD58 VAXG[19] VDDQ[5] AL34 10uf/6.3V 10uf/6.3V 1uf/10V 1uf/10V 1uf/10V 1uf/10V
AD59 VAXG[20] VDDQ[6] AL38
C339 C351 C340 C326 C139 C133 AE46 VAXG[21] VDDQ[7] AL42
C0402 C0402 C0402 C0402 C0402 C0402 N45 VAXG[22] VDDQ[8] AM33
1uf/10V 1uf/10V 1uf/10V 1uf/10V 1uf/10V 1uf/10V P47 VAXG[23] VDDQ[9] AM36
P48 VAXG[24] VDDQ[10] AM40 R729 0 R0402
P50 VAXG[25] VDDQ[11] AN30 C474 C475 C476 C477 ns
P51 VAXG[26] VDDQ[12] AN34 C0805 C0805 C0805 C0805
P52 VAXG[27] VDDQ[13] AN38 10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V
P53 VAXG[28] VDDQ[14] AR26 DDR_WR_VREF02 2 3 R730 0

DDR3
VAXG[29] VDDQ[15] DDR_WR_VREF01_D1 14
P55 AR28 R0402

GRAPHICS
P56 VAXG[30] VDDQ[16] AR30 Q39
P61 VAXG[31] VDDQ[17] AR32 R731 1K ns L2N7002LT1G
T48 VAXG[32] VDDQ[18] AR34 R0402 SOT23

1
T58 VAXG[33] VDDQ[19] AR36
T59 VAXG[34] VDDQ[20] AR40
T61 VAXG[35] VDDQ[21] AV41
C C
U46 VAXG[36] VDDQ[22] AW26 DRAMRST_CNTRL
VAXG[37] VDDQ[23] 7 DRAMRST_CNTRL
V47 BA40
V48 VAXG[38] VDDQ[24] BB28
V50 VAXG[39] VDDQ[25] BG33
V51 VAXG[40] VDDQ[26]
V52 VAXG[41]
V53 VAXG[42]
V55 VAXG[43]
V56 VAXG[44]
V58 VAXG[45]
V59 VAXG[46]
W50 VAXG[47]
W51 VAXG[48]
W52 VAXG[49]
W53 VAXG[50]
W55 VAXG[51]
W56 VAXG[52]
W61 VAXG[53]
Y48 VAXG[54]
VAXG[55] TU142 VerB: Changed 0 ohm to open point for cost down 2011-12-20
Y61 CL341 VerC: Remove the open jump 1227
Check list and CRB: 10ohm VAXG[56]
Intel check change to 100ohm
+V1.5S
R743 100,1%
+VGFX
R0402 AM28 0.6A

QUIET RAILS
SENSE
LINES
F45 VCCDQ[1] AN26
44 VGFXVCCSEN VAXG_SENSE VCCDQ[2]
G45 C128
44 VGFXVSSSEN VSSAXG_SENSE C0402
R744 100,1% 1uf/10V
B R0402 B
+V1.8S
CRB 1个10uF,2个1uF,1个330uF
1.8V RAIL

FB30
Max: 1.2A
FB0805 2 1 VCCPLL BB3 差异3:VCCSA_SEL[1:0] pins enable dynamic selection
BC1 VCCPLL[1]
300ohm@100MHz,2A C362 C361 C360 C472 C473 BC4 VCCPLL[2]
C0805 C0402 C0402 VCCPLL[3]
10uf/6.3V 1uf/10V 1uf/10V ns ns
10uf/6.3V

10uf/6.3V

BC43
C0805

C0805

+VCCSA VDDQ_SENSE T79 ICTP ns


BA43 T85 ICTP ns
VSS_SENSE_VDDQ
SENSE LINES

Max: 6A L17
L21 VCCSA[1]
C132 C120 C478 C479 N16 VCCSA[2]
C0805 C0805 C0805 C0805 N20 VCCSA[3]
10uf/6.3V 10uf/6.3V 10uf/6.3V 10uf/6.3V N22 VCCSA[4]
SA RAIL

P17 VCCSA[5]
P20 VCCSA[6] U10
VCCSA[7] VCCSA_SENSE VCCSA_SENSE 42
公版5颗10uF,5颗1uF,1颗330uF R16
R18 VCCSA[8]
R21 VCCSA[9]
C359 C355 C357 C277 U15 VCCSA[10]
VCCSA[11]
VCCSA VID

C0402 C0402 C0402 C0402 V16


1uf/10V 1uf/10V 1uf/10V 1uf/10V V17 VCCSA[12] D48
VCCSA[13] VCCSA_VID[0] VCCSA_SELECT0 42
V18 D49
lines

V21 VCCSA[14] VCCSA_VID[1] VCCSA_SELECT1 42


W20 VCCSA[15]
VCCSA[16] VID0:For Sandy Bridge processor the
output will be low, for Ivy Bridge processor the output will be high.
A VID1:For Chief River platforms, this A
pin must have a pull down resistor to ground.
IC,IVB_2CBGA,0P7 TOPSTAR TECHNOLOGY
BGA1023_31X24
Robin
Page Name Ivy Bridge VGFX/VDDQ
Size
Project Name Rev
Custom CL42 EVT
A
Date: Wednesday, January 09, 2013 Sheet 10 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

U16H

U16I

A13 AM38
A17 VSS[1] VSS[91] AM4
A21 VSS[2] VSS[92] AM42 BG17 M4
A25 VSS[3] VSS[93] AM45 BG21 VSS[181] VSS[250] M58
A28 VSS[4] VSS[94] AM48 BG24 VSS[182] VSS[251] M6
A33 VSS[5] VSS[95] AM58 BG28 VSS[183] VSS[252] N1
A37 VSS[6] VSS[96] AN1 BG37 VSS[184] VSS[253] N17
A40 VSS[7] VSS[97] AN21 BG41 VSS[185] VSS[254] N21
D D
A45 VSS[8] VSS[98] AN25 BG45 VSS[186] VSS[255] N25
A49 VSS[9] VSS[99] AN28 BG49 VSS[187] VSS[256] N28
A53 VSS[10] VSS[100] AN33 BG53 VSS[188] VSS[257] N33
A9 VSS[11] VSS[101] AN36 BG9 VSS[189] VSS[258] N36
AA1 VSS[12] VSS[102] AN40 C29 VSS[190] VSS[259] N40
AA13 VSS[13] VSS[103] AN43 C35 VSS[191] VSS[260] N43
AA50 VSS[14] VSS[104] AN47 C40 VSS[192] VSS[261] N47
AA51 VSS[15] VSS[105] AN50 D10 VSS[193] VSS[262] N48
AA52 VSS[16] VSS[106] AN54 D14 VSS[194] VSS[263] N51
AA53 VSS[17] VSS[107] AP10 D18 VSS[195] VSS[264] N52
AA55 VSS[18] VSS[108] AP51 D22 VSS[196] VSS[265] N56
AA56 VSS[19] VSS[109] AP55 D26 VSS[197] VSS[266] N61
AA8 VSS[20] VSS[110] AP7 D29 VSS[198] VSS[267] P14
AB16 VSS[21] VSS[111] AR13 D35 VSS[199] VSS[268] P16
AB18 VSS[22] VSS[112] AR17 D4 VSS[200] VSS[269] P18
AB21 VSS[23] VSS[113] AR21 D40 VSS[201] VSS[270] P21
AB48 VSS[24] VSS[114] AR41 D43 VSS[202] VSS[271] P58
AB61
AC10
VSS[25]
VSS[26]
VSS[27]
VSS[115]
VSS[116]
VSS[117]
AR48
AR61
D46
D50
VSS[203]
VSS[204]
VSS[205]
VSS VSS[272]
VSS[273]
VSS[274]
P59
P9
AC14 AR7 D54 R17
AC46 VSS[28] VSS[118] AT14 D58 VSS[206] VSS[275] R20
AC6 VSS[29] VSS[119] AT19 D6 VSS[207] VSS[276] R4
AD17 VSS[30] VSS[120] AT36 E25 VSS[208] VSS[277] R46
AD20 VSS[31] VSS[121] AT4 E29 VSS[209] VSS[278] T1
AD4 VSS[32] VSS[122] AT45 E3 VSS[210] VSS[279] T47
AD61
AE13
VSS[33]
VSS[34]
VSS[35]
VSS VSS[123]
VSS[124]
VSS[125]
AT52
AT58
E35
E40
VSS[211]
VSS[212]
VSS[213]
VSS[280]
VSS[281]
VSS[282]
T50
T51
AE8 AU1 F13 T52
C AF1 VSS[36] VSS[126] AU11 F15 VSS[214] VSS[283] T53 C
AF17 VSS[37] VSS[127] AU28 F19 VSS[215] VSS[284] T55
AF21 VSS[38] VSS[128] AU32 F29 VSS[216] VSS[285] T56
AF47 VSS[39] VSS[129] AU51 F35 VSS[217] VSS[286] U13
AF48 VSS[40] VSS[130] AU7 F40 VSS[218] VSS[287] U8
AF50 VSS[41] VSS[131] AV17 F55 VSS[219] VSS[288] V20
AF51 VSS[42] VSS[132] AV21 G51 VSS[220] VSS[289] V61
AF52 VSS[43] VSS[133] AV22 G6 VSS[221] VSS[290] W13
AF53 VSS[44] VSS[134] AV34 G61 VSS[222] VSS[291] W15
AF55 VSS[45] VSS[135] AV40 H10 VSS[223] VSS[292] W18
AF56 VSS[46] VSS[136] AV48 H14 VSS[224] VSS[293] W21
AF58 VSS[47] VSS[137] AV55 H17 VSS[225] VSS[294] W46
AF59 VSS[48] VSS[138] AW13 H21 VSS[226] VSS[295] W8
AG10 VSS[49] VSS[139] AW43 H4 VSS[227] VSS[296] Y4
AG14 VSS[50] VSS[140] AW61 H53 VSS[228] VSS[297] Y47
AG18 VSS[51] VSS[141] AW7 H58 VSS[229] VSS[298] Y58
AG47 VSS[52] VSS[142] AY14 J1 VSS[230] VSS[299] Y59
AG52 VSS[53] VSS[143] AY19 J49 VSS[231] VSS[300]
AG61 VSS[54] VSS[144] AY30 J55 VSS[232]
AG7 VSS[55] VSS[145] AY36 K11 VSS[233]
AH4 VSS[56] VSS[146] AY4 K21 VSS[234]
AH58 VSS[57] VSS[147] AY41 K51 VSS[235]
AJ13 VSS[58] VSS[148] AY45 K8 VSS[236] A5
AJ16 VSS[59] VSS[149] AY49 L16 VSS[237] VSS_NCTF_1 A57
AJ20 VSS[60] VSS[150] AY55 L20 VSS[238] VSS_NCTF_2 BC61
AJ22 VSS[61] VSS[151] AY58 L22 VSS[239] VSS_NCTF_3 BD3
AJ26 VSS[62] VSS[152] AY9 L26 VSS[240] VSS_NCTF_4 BD59
AJ30 VSS[63] VSS[153] BA1 L30 VSS[241] VSS_NCTF_5 BE4

NCTF
AJ34 VSS[64] VSS[154] BA11 L34 VSS[242] VSS_NCTF_6 BE58
B AJ38 VSS[65] VSS[155] BA17 L38 VSS[243] VSS_NCTF_7 BG5 B
AJ42 VSS[66] VSS[156] BA21 L43 VSS[244] VSS_NCTF_8 BG57
AJ45 VSS[67] VSS[157] BA26 L48 VSS[245] VSS_NCTF_9 C3
AJ48 VSS[68] VSS[158] BA32 L61 VSS[246] VSS_NCTF_10 C58
AJ7 VSS[69] VSS[159] BA48 M11 VSS[247] VSS_NCTF_11 D59
AK1 VSS[70] VSS[160] BA51 M15 VSS[248] VSS_NCTF_12 E1
AK52 VSS[71] VSS[161] BB53 VSS[249] VSS_NCTF_13 E61
AL10 VSS[72] VSS[162] BC13 VSS_NCTF_14
AL13 VSS[73] VSS[163] BC5
AL17 VSS[74] VSS[164] BC57
AL21 VSS[75] VSS[165] BD12
AL25 VSS[76] VSS[166] BD16
AL28 VSS[77] VSS[167] BD19 IC,IVB_2CBGA,0P7
AL33 VSS[78] VSS[168] BD23 BGA1023_31X24
AL36 VSS[79] VSS[169] BD27
AL40 VSS[80] VSS[170] BD32
AL43 VSS[81] VSS[171] BD36
AL47 VSS[82] VSS[172] BD40
AL61 VSS[83] VSS[173] BD44
AM13 VSS[84] VSS[174] BD48
AM20 VSS[85] VSS[175] BD52
AM22 VSS[86] VSS[176] BD56
AM26 VSS[87] VSS[177] BD8
AM30 VSS[88] VSS[178] BE5
AM34 VSS[89] VSS[179] BG13
VSS[90] VSS[180]

A A
TOPSTAR TECHNOLOGY
IC,IVB_2CBGA,0P7
BGA1023_31X24 Robin
Page Name Ivy Bridge GND
Size Project Name Rev
A3 CL42 EVT
A
Date: Wednesday, January 09, 2013 Sheet 11 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

U16E

B50 N59 ns
C51 CFG[0] BCLK_ITP N58 T70
ns ICTP
B54 CFG[1] BCLK_ITP# T71 ICTP
D53 CFG[2]
A51 CFG[3] N42
D C53 CFG[4] RSVD30 L42 D
C55 CFG[5] RSVD31 L45
H49 CFG[6] RSVD32 L47
A55 CFG[7] RSVD33
H51 CFG[8]
K49 CFG[9] M13
K53 CFG[10] RSVD34 M14
F53 CFG[11] RSVD35 U14
G53 CFG[12] RSVD36 W14
L51 CFG[13] RSVD37 P13
F51 CFG[14] RSVD38
D52 CFG[15]
L53 CFG[16] AT49
CFG[17] RSVD39 K24
RSVD40

RESERVED
H43
K43 VCC_VAL_SENSE AH2
VSS_VAL_SENSE RSVD41 AG13
RSVD42 AM14
H45 RSVD43 AM15
C K45 VAXG_VAL_SENSE RSVD44 C
VSSAXG_VAL_SENSE
N50
F48 RSVD45
G48 VCC_DIE_SENSE
RSVD47
H48
K48 RSVD6
RSVD7 A4 DC_TEST_A4
DC_TEST_A4 C4
BA19 DC_TEST_C4 D3 DC_TEST_C4_D3
AV19 RSVD8 DC_TEST_D3 D1 DC_TEST_D1
AT21 RSVD9 DC_TEST_D1 A58 DC_TEST_A58
BB21 RSVD10 DC_TEST_A58 A59
BB19 RSVD11 DC_TEST_A59 C59 DC_TEST_A59_C59
AY21 RSVD12 DC_TEST_C59 A61
BRACKET1 BA22 RSVD13 DC_TEST_A61 C61 DC_TEST_A61_C61
CPU_HOLE AY22 RSVD14 DC_TEST_C61 D61 DC_TEST_D61
AU19 RSVD15 DC_TEST_D61 BD61 DC_TEST_BD61
ASSY AU21 RSVD16 DC_TEST_BD61 BE61
BD21 RSVD17 DC_TEST_BE61 BE59 DC_TEST_BE59_BE61
B B
BD22 RSVD18 DC_TEST_BE59 BG61
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

RSVD19 DC_TEST_BG61
1
2
3
4
5
6
7
8
9

BD25 BG59 DC_TEST_BG59_BG61


BD26 RSVD20 DC_TEST_BG59 BG58 DC_TEST_BG58
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

BG22 RSVD21 DC_TEST_BG58 BG4 DC_TEST_BG4


BE22 RSVD22 DC_TEST_BG4 BG3
BG26 RSVD23 DC_TEST_BG3 BE3 DC_TEST_BE3_BG3
BE26 RSVD24 DC_TEST_BE3 BG1
BF23 RSVD25 DC_TEST_BG1 BE1 DC_TEST_BE1_BG1
BE24 RSVD26 DC_TEST_BE1 BD1 DC_TEST_BD1
RSVD27 DC_TEST_BD1
Daisy Chain, for solder joint reliability
and non-critical to function. BGA only.
Followed CRB connection.
IC,IVB_2CBGA,0P7
BGA1023_31X24

TOPSTAR TECHNOLOGY
Robin
Page Name Ivy Bridge Reserved
A A
Size Project Name Rev
A4 CL42 EVT
A
Date: Wednesday, January 09, 2013 Sheet 12 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A
TOPSTAR TECHNOLOGY
杨华明(Sky Yang)
Page Name DDR3 CHA SODIMM0
Size Project Name Rev
A3 CL42 EVT
A
Date: Wednesday, January 09, 2013 Sheet 13 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

+V3.3S 7,15,16,17,18,19,20,21,22,24,25,29,30,31,32,33,34,35,40,41,42,43,44,45,47
+V1.5
+V1.5 7,40,45
+V0.75S 40,45

C237 C217 C192 C242 C241 C187 C238 C239 C236 C219
C0805 C0603 C0402 C0603 C0603 C0402 C0603 C0603 C0402 10uf/6.3V +V0.75S +V1.5
10uf/6.3V 2.2uf/10V 0.1UF/10V,X7R 2.2uf/10V 2.2uf/10V 0.1UF/10V,X7R 2.2uf/10V 2.2uf/10V 0.1UF/10V,X7R C0805
ns ns

204
203

100
105
106
111
112
117
118
123
124

145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
75
76
81
82
87
88
93
94
99
D DIMM1 D
8 MB_B_A[15:0]
公版6颗 10uF,1颗330uF,4颗1uF

VTT2
VTT1

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
MB_DATA[63:0] 8
MB_B_A0 98 5 MB_DATA0
+V1.5 MB_B_A1 97 A0 D0 7 MB_DATA1
MB_B_A2 96 A1 D1 15 MB_DATA2
MB_B_A3 95 A2 D2 17 MB_DATA3
MB_B_A4 92 A3 D3 4 MB_DATA4
C235 C218 C216 C220 C184 C234 C214 C215 C203 MB_B_A5 91 A4 D4 6 MB_DATA5
C0402 C0603 C0402 C0603 C0603 C0402 C0603 C0603 10uf/6.3V MB_B_A6 90 A5 D5 16 MB_DATA6
0.1UF/10V,X7R 2.2uf/10V 0.1UF/10V,X7R 2.2uf/10V 2.2uf/10V 0.1UF/10V,X7R 2.2uf/10V 2.2uf/10V C0805 MB_B_A7 86 A6 D6 18 MB_DATA7
ns ns ns ns MB_B_A8 89 A7 D7 21 MB_DATA8
MB_B_A9 85 A8 D8 23 MB_DATA9
MB_B_A10 107 A9 D9 33 MB_DATA10
MB_B_A11 84 A10/AP D10 35 MB_DATA11
MB_B_A12 83 A11 D11 22 MB_DATA12
MB_B_A13 119 A12/BC# D12 24 MB_DATA13
MB_B_A14 80 A13 D13 34 MB_DATA14
MB_B_A15 78 A14 D14 36 MB_DATA15
A15 D15 39 MB_DATA16
109 D16 41 MB_DATA17
8 MB_B_BS0 BA0 D17
108 51 MB_DATA18
8 MB_B_BS1 BA1 D18
79 53 MB_DATA19
8 MB_B_BS2 BA2 D19 40 MB_DATA20
114 D20 42 MB_DATA21
8 M_CS#2 121 CS0 D21 50 MB_DATA22
8 M_CS#3 CS1 D22 52 MB_DATA23
11 D23 57 MB_DATA24
28 DQM0 D24 59 MB_DATA25
C 46 DQM1 D25 67 MB_DATA26 C
Layout note:电容靠近DDR slot VDD PIN 63
136
DQM2
DQM3
D26
D27
69
56
MB_DATA27
MB_DATA28
153 DQM4 D28 58 MB_DATA29
170 DQM5 D29 68 MB_DATA30
+V0.75S 187 DQM6 D30 70 MB_DATA31
DQM7 D31 129 MB_DATA32
113 D32 131 MB_DATA33
8 MB_B_WE# WE D33
115 141 MB_DATA34
8 MB_B_CAS# 110 CAS D34 143
C198 C193 C227 C224 MB_DATA35
8 MB_B_RAS# RAS D35
C0402 C0402 C0402 C0402 130 MB_DATA36
1uf/10V 1uf/10V 1uf/10V 1uf/10V 73 D36 132 MB_DATA37
8 M_CKE2 74 CKE0 D37 140 MB_DATA38
8 M_CKE3 CKE1 D38 142 MB_DATA39
101 D39 147 MB_DATA40
8 M_CLK_DDR2 103 CK0 D40 149 MB_DATA41
8 M_CLK_DDR#2 102 CK0 D41 157 MB_DATA42
8 M_CLK_DDR3 104 CK1 D42 159 MB_DATA43
+V1.5 8 M_CLK_DDR#3 CK1 D43 146 MB_DATA44
116 D44 148 MB_DATA45
8 M_ODT2 120 ODT0 D45 158 MB_DATA46
8 M_ODT3 ODT1 D46 160 MB_DATA47
MB_DQS0 12 D47 163 MB_DATA48
MB_DQS1 29 DQS0 D48 165 MB_DATA49
R312 MB_DQS2 47 DQS1 D49 175 MB_DATA50
MB_DQS3 64 DQS2 D50 177 MB_DATA51
1K,1% DQS3 D51
R0402 MB_DQS4 137 164 MB_DATA52
MB_DQS5 154 DQS4 D52 166 MB_DATA53
DDR_WR_VREF01_D1 MB_DQS6 171 DQS5 D53 174 MB_DATA54
B 8 MB_DQS[7:0] MB_DQS7 188 DQS6 D54 176 MB_DATA55 B
DQS7 D55 181 MB_DATA56
R310 200 D56 183 MB_DATA57
16 SMB_DATA_S 202 SDA D57 191 MB_DATA58
1K,1% 16 SMB_CLK_S SCL D58
R0402 +V3.3S 193 MB_DATA59
R318 10K R0402 197 D59 180 MB_DATA60
R316 10K R0402 201 SA0 D60 182 MB_DATA61
Note: SA1 D61 192 MB_DATA62
SO-DIMM1 SPD Address is 0xA4 199 D62 194 MB_DATA63
VDDSPD D63
+V1.5 1 10 MB_DQS#0
10 DDR_WR_VREF01_D1 126 VREF_DQ DQS#0 27
C228 C226 VREFB_CA MB_DQS#1
C0402 C0603 C230 C229 VREF_CA DQS#1 45 MB_DQS#2
0.1UF/10V,X7R 2.2uf/10V C0402 C0603 198 DQS#2 62 MB_DQS#3
0.1UF/10V,X7R 2.2uf/10V 30 EVENT# DQS#3 135 MB_DQS#4
RESET# DQS#4 152 MB_DQS#5
R303 77 DQS#5 169 MB_DQS#6
122 NC1 DQS#6 186 MB_DQS#7
1K,1%
125 NC2 DQS#7
R0402 NCTEST MB_DQS#[7:0] 8

VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33

GND1
GND2
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VREFB_CA
7 DDR3_DRAMRST#
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144

205
206
DDR3_SODIMM204_0

R302 C213 C222


A 1K,1% C0402 C0603 A
R0402 0.1UF/10V,X7R 2.2uf/10V TOPSTAR TECHNOLOGY
杨华明(Sky Yang)
Page Name DDR3 CHB SODIMM0
Size Project Name Rev
A3 CL42 EVT
A
Date: Wednesday, January 09, 2013 Sheet 14 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

PCH_EC_RTC 17,22
EC_RTC 27,39,45
+V3.3S 7,14,16,17,18,19,20,21,22,24,25,29,30,31,32,33,34,35,40,41,42,43,44,45,47
+V3.3AL 7,16,17,19,20,22,24,28,31,33,40,43,45
+V1.05S 6,7,9,16,17,21,22,30,41,44,47
RTC_BAT1
+V5S 16,22,24,25,27,28,29,30,40,42,44,45,47
EC_RTC D1 + +V3.3SB 7,17,20,22,28,31,33,35,37,38,39,45
LBAT54CLT1G PCH_EC_RTC -
sot23 RTCBAT with Cable
R1 1K 1 ASSY
R0402
3

D 2 C294 D
1uf/10V
C0402
CMOS Settings J1
Clear CMOS Short C292 R377 0 32XCLK0
R334 Keep CMOS Open C0402 R0402
1K R24 20K R0402 15pF/50V,NPO
R0402 +V3.3S

2
Y1 +V3.3S
R26 20K R0402 J1 3 xd3 R394
3

C17 C16 JOPEN ASSY 10M U12A


1 1uf/10V RESISTOR_1 32.768KHz R0402
3

1
1 2 C0402 1uf/10V ns A20 C38 R23 R63 R103

2
2 RTCX1 FWH0 / LAD0 LPC_AD0 31,33
4

R22 C0402 A38 10K 10K 10K


FWH1 / LAD1 LPC_AD1 31,33
C20 B37

LPC
RTCCN1 1M C296 32XCLK1 R0402 R0402 R0402
4

RTCX2 FWH2 / LAD2 C37 LPC_AD2 31,33


Wafer R0402 C0402 15pF/50V,NPO ns ns
D20 FWH3 / LAD3 LPC_AD3 31,33
CNS2_V RTC_RST#
RTCRST# D36
G22 FWH4 / LFRAME# LPC_FRAME# 31,33
SRTC_RST#
SRTCRST# E36
K22 LDRQ0# K36

RTC
SM_INTRUDER#
INTRUDER# LDRQ1# / GPIO23 Internal PU20K
Pull High to enable PCH_EC_RTC R372 332K,1% ICH_INTVRMEN C17 V5 INT_SERIRQ
INTVRMEN SERIRQ INT_SERIRQ 33
HDA_SYNC:On-Die PLL Voltage Regulator Voltage Select internal SUS1.05V VR R0402
(Internal pull down 20K)
Low: 1.8V +V3.3S AM3
High: 1.5V(Default) SATA0RXN SATA_RXN0 27
R46 33 R0402 HDA_BCLK N34 AM1
29 AZALIA_CODEC_BITCLK HDA_BCLK SATA0RXP SATA_RXP0 27
R705 0 AP7

SATA 6G
L34 SATA0TXN AP5 SATA_TXN0 27
R0402 ns +V3.3AL R34 1K R0402 HDA_SYNC
C R706 HDA_SYNC SATA0TXP SATA_TXP0 27 C
1K T10 AM10
Q36 29 SPKR SPKR SATA1RXN AM8
R0402 SATA1RXP
ns L2N7002LT1G R44 33 R0402 HDA_RST# K34 AP11 NM70:only Port0 support 6Gb/s,port1/3 disable.
29 AZALIA_CODEC_RST# HDA_RST# SATA1TXN AP10
R707 33 R0402 2 3 HDA_SYNC SATA1TXP
29 AZALIA_CODEC_SYNC E34 AD7
29 AZALIA_SDATAIN0 HDA_SDIN0 SATA2RXN AD5
Internal PD20K
G34 SATA2RXP AH5 Port1/2/3 may not available in all SKUs
SOT23
R708 +V5S HDA_SDIN1 SATA2TXN AH4
1

1M C34 SATA2TXP
HDA_SDO:Flash Descriptor Security Overide HDA_SDIN2
R0402 AB8

IHDA
Internal pull down 20K Port1/3 not available in HM70
A34 SATA3RXN AB10
Low = Disabled(Default) HDA_SDIN3 SATA3RXP AF3
High = Enabled SATA3TXN AF1
R390 1K R0402 HDA_SDO A36 SATA3TXP
+V3.3AL HDA_SDO
ns Y7

SATA
SATA4RXN Y5
VerC:HDA_SDO:增加对声卡芯片的隔离电路,防止刷写ME是EC无法在S5下将ME_LOCK#拉高 33 EC_ME_LOCK# R374 4.7K R0402 C36 SATA4RXP AD3
+V3.3S R294 ns HDA_DOCK_EN# / GPIO33 SATA4TXN AD1
R715 0 N32 SATA4TXP
4.7K
R0402 ns HDA_DOCK_RST# / GPIO13 Y3
R0402 SATA5RXN SATA_RXN5 27
ns Y1
SATA5RXP SATA_RXP5 27
R716 AB3
SATA5TXN SATA_TXN5 27
1K Q37 ICTP ns J3 AB1
T36 JTAG_TCK SATA5TXP SATA_TXP5 27
R0402 L2N7002LT1G
ICTP ns H7 Y11 +V1.05S
T9 JTAG_TMS SATAICOMPO
R717 33 R0402 2 3 HDA_SDO

JTAG
29 AZALIA_CODEC_SDOUT ICTP ns K5 Y10 R108 37.4,1% R0402
B T13 JTAG_TDI SATAICOMPI B

SOT23 ICTP ns H1
T37 JTAG_TDO AB12
R718 +V5S +V3.3S
1

1M SATA3RCOMPO
Internal pull high for no use
+V3.3S +V3.3SB R0402 AB13 R111 49.9,1% R0402
ns SATA3COMPI

PCH_SPI_CLK T3 AH1 R438 750 OHM R0402 R422


SPI_CLK SATA3RBIAS 10K
R442 R440 PCH_SPI_MOSI_Q PCH_SPI_CS0# Y14 R0402
PCH_SPI_MOSI_Q 33 SPI_CS0#
R0402 R0402 PCH_SPI_MISO_Q
PCH_SPI_MISO_Q 33 T1
0 0 PCH_SPI_CS0#_Q
PCH_SPI_CS0#_Q 33 SPI_CS1# P3

SPI
KB3930 KB9010 PCH_SPI_CLK_Q
PCH_SPI_CLK_Q 33 SATALED# SATA_LED#
+V3.3S
R444 10K R0402 ns PCH_SPI_MOSI V4 V14 R112 10K R0402
SPI_MOSI SATA0GP / GPIO21
PCH_SPI_MISO U3 P1 R418 10K R0402 CRB pull up to 43K
U13 SPI_MISO SATA1GP / GPIO19 Internal PU20K
8 5 PCH_SPI_MOSI_Q R412 place close to PCH in 500mils
VDD SI 2 PCH_SPI_MISO_Q CPT_PPT_Rev_0p5
R447 3.3K R0402 3 SO 1 PCH_SPI_CS0#_Q +V3.3SB +V3.3S +V3.3SB +V3.3S
WP# CE# 6 PCH_SPI_CLK_Q
R439 3.3K R0402 7 SCK R724 0 R0402 KB3930 R727 0 R0402 KB3930
HOLD# 4
VSS R183 EC_OWNER R186 R188 EC_OWNER R192
W25Q32BVSSIG 4.7K 4.7K 4.7K 4.7K
SOIC8_50_208 R0402 Q8 R0402 R0402 Q9 R0402
2

2
KB9010 L2N7002DW1T1G KB9010 KB9010 L2N7002DW1T1G KB9010
A SC70_6 SC70_6 A
PCH_SPI_MOSI_Q 6 1 PCH_SPI_MOSI PCH_SPI_MISO_Q 6 1 PCH_SPI_MISO TOPSTAR TECHNOLOGY
Boot BIOS Strap 杨华明(Sky Yang)
PCH_SPI_CS0#_Q 3 4 PCH_SPI_CS0# PCH_SPI_CLK_Q 3 4 PCH_SPI_CLK
GNT1# SATA1GP Boot BIOS Location KB9010 KB9010 Page Name PCH RTC/SATA/SPI/HDA/LPC

0 0 LPC R203 R201 Size Project Name Rev


5

R202 EC_OWNER 4.7K R200 EC_OWNER 5 4.7K A3 CL42 EVT


A
0 1 Reserved 4.7K R0402 4.7K R0402
Date: Wednesday, January 09, 2013 Sheet 15 of 51
R0402 KB9010 R0402 KB9010
1 0 PCI R733 0 R0402 KB3930 R732 0 R0402 KB3930 PROPERTY NOTE: this document contains information confidential and property to
KB9010 KB9010 TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
1 1 SPI +V3.3S +V3.3S to others or used for any purpose other than that for which it was obtained without
33 EC_OWNER the expressed written consent of TOPSTAR
+V3.3SB +V3.3SB

5 4 3 2 1
5 4 3 2 1

+V3.3AL 7,15,17,19,20,22,24,28,31,33,40,43,45
+V3.3S
+V3.3S 7,14,15,17,18,19,20,21,22,24,25,29,30,31,32,33,34,35,40,41,42,43,44,45,47
+V1.05S 6,7,9,15,17,21,22,30,41,44,47
+V5S 15,22,24,25,27,28,29,30,40,42,44,45,47
U12B R196Q70 R0402 R182
+V3.3AL ns 2.2K
L2N7002LT1G
BG34
34 PCIE_RXN1_LAN PERN1
BJ34 E12 GPIO11 R35 10K R0402 SMBCLK 3 SOT23 2
34 PCIE_RXP1_LAN PERP1 SMBALERT# / GPIO11 SMB_CLK_S 14
C76 C0402 0.1UF/10V,X7R PCIE_TXN1_LAN_C AV32
34 PCIE_TXN1_LAN AU32 PETN1 H14
C83 C0402 0.1UF/10V,X7R PCIE_TXP1_LAN_C SMBCLK R187 2.2K R0402
34 PCIE_TXP1_LAN PETP1 SMBCLK +V3.3S
BE34 C9 SMBDATA R184 2.2K R0402 +V5S

1
BF34 PERN2 SMBDATA
D D
BB32 PERP2
AY32 PETN2 R174 0 R0402 R180
PETP2 A12 +V3.3AL ns

SMBUS
DRAMRST_CNTRL_PCH 7 2.2K
BG36 SML0ALERT# / GPIO60
31 PCIE_RXN4_WLAN PERN3 L2N7002LT1G
BJ36 C8 SML0CLK R368 2.2K R0402
31 PCIE_RXP4_WLAN PERP3 SML0CLK
C90 C0402 0.1UF/10V,X7R PCIE_TXN4_WLAN_C AV34 SMBDATA 3 2
31 PCIE_TXN4_WLAN PETN3 SMB_DATA_S 14
C91 C0402 0.1UF/10V,X7R PCIE_TXP4_WLAN_C AU34 G12 SML0DATA R33 2.2K R0402
31 PCIE_TXP4_WLAN PETP3 SML0DATA
BF36
BE36 PERN4 Q6 +V5S

1
AY34 PERP4 C13 GPIO74 R370 10K R0402 SOT23
BB34 PETN4 SML1ALERT# / PCHHOT# / GPIO74
PETP4 E14 R40 0 R0402 SML1CLK
SML1CLK / GPIO58 SML1CLK 33
BG37 +V3.3AL

PCI-E*
BH37 PERN5 M16 R37 0 R0402 SML1DATA
AY36 PERP5 SML1DATA / GPIO75 SML1DATA 33
BB36 PETN5 SML1CLK R31 2.2K R0402
PETP5 SML1DATA R27 2.2K R0402
BJ38
BG38 PERN6
AU36 PERP6 M7

Controller
PETN6 CL_CLK1 CL_CLK1 31
AV36
HM70/NM70 disable PCIE port 5/6/7/8 PETP6
BG40 T11

Link
BJ40 PERN7 CL_DATA1 CL_DATA1 31
AY40 PERP7
BB40 PETN7 P10
PETP7 CL_RST1# CL_RST1# 31
C BE38 C
BC38 PERN8
AW38 PERP8
AY38 PETN8 +V3.3AL
PETP8
M10 R86 10K R0402
Y40 PEG_A_CLKRQ# / GPIO47
34 PCIE_GLAN_CLKN Y39 CLKOUT_PCIE0N
34 PCIE_GLAN_CLKP CLKOUT_PCIE0P AB37
R401 10K J2 CLKOUT_PEG_A_N AB38

CLOCKS
+V3.3AL PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P
R0402

AB49 AV22 CLKOUT_DMI_N R125 0 R0402


CLKOUT_PCIE1N CLKOUT_DMI_N CLK_EXP_N 7
AB47 AU22 CLKOUT_DMI_P R124 0 R0402
CLKOUT_PCIE1P CLKOUT_DMI_P CLK_EXP_P 7

+V3.3S R411 10K M1


R0402 PCIECLKRQ1# / GPIO18 AM12
CLKOUT_DP_N AM13 120M for DP
AA48 CLKOUT_DP_P
31 CLK_PCIE_MINICARD# AA47 CLKOUT_PCIE2N
31 CLK_PCIE_MINICARD CLKOUT_PCIE2P BF18 R129 10K R0402
V10 CLKIN_DMI_N BE18 R128 10K R0402
31 minicard_CLKREQ# PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
+V3.3S R104 10K R0402
Y37 BJ30 R462 10K R0402
Y36 CLKOUT_PCIE3N CLKIN_GND1_N BG30 R463 10K R0402
CLKOUT_PCIE3P CLKIN_GND1_P
+V3.3AL R382 10K PCIECLKRQ3# A8
R0402 PCIECLKRQ3# / GPIO25 G24 R67 10K R0402
B CLKIN_DOT_96N E24 R68 10K R0402 B
Y43 CLKIN_DOT_96P
Y45 CLKOUT_PCIE4N
CLKOUT_PCIE4P AK7 R121 10K R0402
Note: R90 10K PCIECLKRQ4# L12 CLKIN_SATA_N AK5 R122 10K R0402
For free running clock, do not pull down REQ signal R0402 PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
to GND,this will increase leakage in Sx states.
V45 K45 R89 10K R0402
V46 CLKOUT_PCIE5N REFCLK14IN
CLKOUT_PCIE5P
R32 10K PCIECLKRQ5# L14 H45
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK PCI_CLKFB 19
R0402 Internal PU20K

AB42 V47 R443 0 R0402


AB40 CLKOUT_PEG_B_N XTAL25_IN V49 R437 10M R0402
CLKOUT_PEG_B_P XTAL25_OUT
R96 10K PEG_B_CLKRQ# E6 +V1.05S Y2
R0402 PEG_B_CLKRQ# / GPIO56 2 1
Y47 R109 90.9,1% 25MHz XS2_3D3
V40 XCLK_RCOMP R0402
V42 CLKOUT_PCIE6N C303 C312
CLKOUT_PCIE6P
27pF/50V,NPO 27pF/50V,NPO
R49 10K PCIECLKRQ6# T13 C0402 C0402
R0402 PCIECLKRQ6# / GPIO45
V38 K43
V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
FLEX CLOCKS

CLKOUT_PCIE7P F47
R69 10K PCIECLKRQ7# K12 CLKOUTFLEX1 / GPIO65
R0402 Internal PU20K PCIECLKRQ7# / GPIO46 H47
A CLKOUTFLEX2 / GPIO66 A
AK14 TOPSTAR TECHNOLOGY
AK13 CLKOUT_ITPXDP_N K49 R402 22 R0402
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 CLK_CR_48M 32 杨华明(Sky Yang)
Page Name PCH PCIE/CLK/SMBUS
CPT_PPT_Rev_0p5
Size Project Name Rev
A3 CL42 EVT
A
Date: Wednesday, January 09, 2013 Sheet 16 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

+V3.3AL 7,15,16,19,20,22,24,28,31,33,40,43,45
+V3.3S 7,14,15,16,18,19,20,21,22,24,25,29,30,31,32,33,34,35,40,41,42,43,44,45,47
+V1.05S 6,7,9,15,16,21,22,30,41,44,47
+V3.3AL
PCH_EC_RTC 15,22
+V3.3SB 7,15,20,22,28,31,33,35,37,38,39,45

C13
C0402
0.1UF/10V,X7R
U1

5
U12C
D 1 VCC D
7,33,43 Main_PWROK
4 SYS_PWROK
FDI_TXN[7:0] 6
2 DMI_RXN0 BC24 BJ14 FDI_TXN0
33 ICH_IMVP_PWRGD GND 6 DMI_RXN0 BE20 DMI0RXN FDI_RXN0 AY14
DMI_RXN1 FDI_TXN1
6 DMI_RXN1 BG18 DMI1RXN FDI_RXN1 BE14
SN74AHC1G08DBV DMI_RXN2 FDI_TXN2

3
6 DMI_RXN2 BG20 DMI2RXN FDI_RXN2 BH13
SOT23_5 R17 DMI_RXN3 FDI_TXN3
6 DMI_RXN3 DMI3RXN FDI_RXN3
10K BC12 FDI_TXN4
R0402 DMI_RXP0 BE24 FDI_RXN4 BJ12 FDI_TXN5
6 DMI_RXP0 DMI0RXP FDI_RXN5
ns DMI_RXP1 BC20 BG10 FDI_TXN6
6 DMI_RXP1 DMI1RXP FDI_RXN6
DMI_RXP2 BJ18 BG9 FDI_TXN7
6 DMI_RXP2 BJ20 DMI2RXP FDI_RXN7
DMI_RXP3
6 DMI_RXP3 DMI3RXP BG14 FDI_TXP[7:0] 6
R19 0 R0402 FDI_TXP0
ns DMI_TXN0 AW24 FDI_RXP0 BB14 FDI_TXP1
6 DMI_TXN0 AW20 DMI0TXN FDI_RXP1 BF14
DMI_TXN1 FDI_TXP2
6 DMI_TXN1 DMI1TXN FDI_RXP2
DMI_TXN2 BB18 BG13 FDI_TXP3
6 DMI_TXN2 AV18 DMI2TXN FDI_RXP3 BE12
DMI_TXN3 FDI_TXP4
6 DMI_TXN3 DMI3TXN FDI_RXP4 BG12

DMI
FDI
FDI_TXP5
DMI_TXP0 AY24 FDI_RXP5 BJ10 FDI_TXP6
6 DMI_TXP0 AY20 DMI0TXP FDI_RXP6 BH9
DMI_TXP1 FDI_TXP7
6 DMI_TXP1 DMI1TXP FDI_RXP7
DMI_TXP2 AY18
6 DMI_TXP2 DMI2TXP
DMI_TXP3 AU18 PCH_EC_RTC
6 DMI_TXP3 DMI3TXP AW16
FDI_INT FDI_INT 6
+V1.05S
BJ24 AV12
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 6
R373
R130 49.9,1% DMI_COMP_R BG25 BC10 300K
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 6
R0402 R0402
R131 750 OHM BH21 AV14
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 6
R0402 DSWVRMEN
C BB10 C
FDI_LSYNC1 FDI_LSYNC1 6
R388
300K
ns A18 DSWVRMEN R0402
SUSWARN# R384 0 R0402 SUSACK# DSWVRMEN R45 0 R0402 DS3 ns
PCH_DPWROK 33

System Power Management


For non-DWS support, SUSACK# can be left unconnected. SUSACK# C12 E22 DPWROK R25 0 R0402 noDS3 PM_RSMRST# VerC:Add R45 for Deep S3
33 SUSACK# SUSACK# DPWROK Swain 111206
Internal PU20K
+V3.3S Tie to RSMRST# if not support Deep S4/S5 DSWODVREN - On Die DSW VR Enable
R403 10K K3 B9 PCIE_WAKE#_R R80 0 R0402 PCIE_WAKE# HIGH Enabled (DEFAULT)
SYS_RESET# WAKE# PCIE_WAKE# 20,31,34 LOW Disabled
R0402 noDS3
VerC: Add R80 to co-lay GPIO27
SYS_PWROK P12 N3 CLKRUN# R414 8.2K Swain 111206
SYS_PWROK CLKRUN# / GPIO32 +V3.3S +V3.3AL
R0402

+V3.3AL R95 0 R0402 L22 G8


33 PCH_PWROK PWROK SUS_STAT# / GPIO61 PM_SUS_STAT# 33
PCIE_WAKE#_R R366 1K
R87 0 R0402 L10 N14 R0402
APWROK SUSCLK / GPIO62 SUSCLK 33
Non AMT Support ,tie to PWROK
R29 10K ALW_ACK
R0402 B13 D10 SLP_S5# T1 ns
7 PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63
OD,need to pull up

C21 H4 SLP_S4# R74 0 R0402


33,43 PM_RSMRST# RSMRST# SLP_S4# PCH_SLP_S4# 33
R380 10K R0402 T80
ns
R38 0 R0402 SUSWARN# K16 F4 SLP_S3# R75 0 R0402
B 33 ALW_ACK SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# 33,43 B
Use as SUSPWRDNACK function
Not support Deep sleep ns T81
+V3.3SB PM_PWRBTN# E20 G10 SLP_A#
33 PM_PWRBTN# PWRBTN# SLP_A# T7
ns
R79 0 R0402 DS3
H20 G16 PM_SLP_SUS# 33,39,45
AC_IN_PCH
33 AC_IN_PCH ACPRESENT / GPIO31 SLP_SUS# T10
R93 10K AC_IN_PCH Internal PD20K ns VerC:Add R79 for Deep S3
R0402 Swain 111206
R51 8.2K BAT_LOW# E10 AP14
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC 7
R36 10K PM_PWRBTN# R0402 Internal PU20K
R0402
+V3.3AL R369 10K RI# A10 K14 SLP_LAN# R30 10K ns +V3.3AL
R0402 RI# SLP_LAN# / GPIO29 R0402

R405 10K PCH_PWROK CPT_PPT_Rev_0p5


R0402 Default is GPI
R817 10K DPWROK
R0402

CL42 VerB: Add 10k pull down resistor for DPWROK


for RTC leakage 2012-6-27

A A
TOPSTAR TECHNOLOGY
杨华明(Sky Yang)
Page Name PCH DMI/FDI/PWRGD
Size Project Name Rev
A3 CL42 EVT
A
Date: Wednesday, January 09, 2013 Sheet 17 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

+V3.3S 7,14,15,16,17,19,20,21,22,24,25,29,30,31,32,33,34,35,40,41,42,43,44,45,47

+V3.3S

R364 100K U12D


R0402
L_DDC_DATA: LVDS detected(Internal pull down 20K) J47 AP43
High: LVDS is detected 24 LVDS_BKLTEN M45 L_BKLTEN SDVO_TVCLKINN AP45
R105 R400
Low: LVDS is not detected 24 LVDS_VDDEN L_VDD_EN SDVO_TVCLKINP
D 2.2K 2.2K D
R0402 R0402 P45 AM42
24 LVDS_BKLTCTL L_BKLTCTL SDVO_STALLN AM40
T40 SDVO_STALLP
24 EDID_CLK K47 L_DDC_CLK AP39
24 EDID_DATA L_DDC_DATA SDVO_INTN AP40
R99 2.2K R0402 LCTL_CLK T45 SDVO_INTP
+V3.3S L_CTRL_CLK
R94 2.2K R0402 LCTL_DATA P39
L_CTRL_DATA
R119 2.37K,1% AF37 P38
R0402 T14 AF36 LVD_IBG SDVO_CTRLCLK M39
ns LVD_VBG SDVO_CTRLDATA
AE48
AE47 LVD_VREFH AT49
LVD_VREFL DDPB_AUXN AT47
DDPB_AUXP AT40
AK39 DDPB_HPD
24 LVDS_CLKAM LVDSA_CLK#
AK40 AV42

LVDS
24 LVDS_CLKAP LVDSA_CLK DDPB_0N AV40
AN48 DDPB_0P AV45
24 LVDS_YAM0 LVDSA_DATA#0 DDPB_1N
AM47 AV46
24 LVDS_YAM1 LVDSA_DATA#1 DDPB_1P
AK47 AU48
24 LVDS_YAM2

Digital Display Interface


T16 AJ48 LVDSA_DATA#2 DDPB_2N AU47 DDPC_CTRLDATA: Port C Detected(Internal pull down 20K,PD will disable when PLTRST# not active)
ns LVDSA_DATA#3 DDPB_2P AV47 High: Port C is detected
AN47 DDPB_3N AV49 Low: Port C is not detected
24 LVDS_YAP0 AM49 LVDSA_DATA0 DDPB_3P
24 LVDS_YAP1 LVDSA_DATA1
AK49
24 LVDS_YAP2 LVDSA_DATA2
T15 AJ47 P46
LVDSA_DATA3 DDPC_CTRLCLK P42 GM_HDMI_DDC_CLK 25
ns
C DDPC_CTRLDATA GM_HDMI_DDC_DATA 25 C
AF40
AF39 LVDSB_CLK# AP47 SPONGE_U2
LVDSB_CLK DDPC_AUXN AP49
AH45 DDPC_AUXP AT38 ASSY
LVDSB_DATA#0 DDPC_HPD MCH_HDMI_HPD 25
AH47
AF49 LVDSB_DATA#1 AY47
LVDSB_DATA#2 DDPC_0N IN_D2- 25
AF45
LVDSB_DATA#3 DDPC_0P
AY49
AY43 IN_D2+ 25 PVC
AH43 DDPC_1N AY45 IN_D1- 25
LVDSB_DATA0 DDPC_1P IN_D1+ 25
AH49 BA47
AF47 LVDSB_DATA1 DDPC_2N BA48 IN_D0- 25
AF43 LVDSB_DATA2 DDPC_2P BB47 IN_D0+ 25
LVDSB_DATA3 DDPC_3N MCH_CLK_D4- 25
BB49
DDPC_3P MCH_CLK_D4+ 25

N48 M43
P49 CRT_BLUE DDPD_CTRLCLK M36
T49 CRT_GREEN DDPD_CTRLDATA
CRT_RED
AT45
T39 DDPD_AUXN AT43

CRT
M40 CRT_DDC_CLK DDPD_AUXP BH41
CRT_DDC_DATA DDPD_HPD
BB43
M47 DDPD_0N BB45
M49 CRT_HSYNC DDPD_0P BF44
CRT_VSYNC DDPD_1N BE44
DDPD_1P BF42
B
R106 1K,1% R0402 T43 DDPD_2N BE42 B
T42 DAC_IREF DDPD_2P BJ42
CRT_IRTN DDPD_3N BG42
DDPD_3P
CPT_PPT_Rev_0p5

A A
TOPSTAR TECHNOLOGY
杨华明(Sky Yang)
Page Name PCH Display
Size Project Name Rev
A3 CL42 EVT
A
Date: Wednesday, January 09, 2013 Sheet 18 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

+V3.3AL 7,15,16,17,20,22,24,28,31,33,40,43,45
+V3.3S 7,14,15,16,17,18,20,21,22,24,25,29,30,31,32,33,34,35,40,41,42,43,44,45,47

+V3.3S +V3.3AL U12E


AY7
RSVD1 AV7
BG26 RSVD2 AU3
BJ26 TP1 RSVD3 BG4
R378 R365 BH25 TP2 RSVD4
BJ16 TP3 AT10
0 0
R0402 R0402 BG16 TP4 RSVD5 BC8
D D
ns ns AH38 TP5 RSVD6
AH37 TP6 AU2
AK43 TP7 RSVD7 AT4
C293 R379 0 AK45 TP8 RSVD8 AT3
C0402 R0402 C18 TP9 RSVD9 AT1
0.1UF/10V,X7R N30 TP10 RSVD10 AY3
ns U10 H3 TP11 RSVD11 AT5
TP12 RSVD12

5
AH12 AV3
VCC 1 PLT_RST# AM4 TP13 RSVD13 AV1
4 AM5 TP14 RSVD14 BB1
7,31,33,34 BUF_PLT_RST# 2 Y13 TP15 RSVD15 BA3
GND R64 K24 TP16 RSVD16 BB5
R367 SN74AHC1G08DBV L24 TP17 RSVD17 BB3
10K

3
100K SOT23_5 R0402 AB46 TP18 RSVD18 BB7
R0402 ns ns AB45 TP19 RSVD19 BE8
ns TP20 RSVD20 BD4

RSVD
RSVD21 BF6
RSVD22
B21 AV5
M20 TP21 RSVD23 AV10
AY16 TP22 RSVD24
BG46 TP23 AT8
USB Port Mapping TP24 RSVD25
AY5
USB2.0 Number USB3.0 Number RSVD26 BA2
BE28 RSVD27
36 USB3_RX1_N USB3Rn1
0 1 BC30 AT12
36 USB3_RX2_N BE32 USB3Rn2 RSVD28 BF3
C 1 2 Disabled in HM70 BJ32 USB3Rn3 RSVD29 C
BC28 USB3Rn4
36 USB3_RX1_P USB3Rp1
2 3 BE30
36 USB3_RX2_P USB3Rp2
BF32
3 4 Disabled in HM70 BG32 USB3Rp3 C24
USB3Rp4 USBP0N USB_PN0 36
AV26 A24
36 USB3_TX1_N BB26 USB3Tn1 USBP0P C25 USB_PP0 36
36 USB3_TX2_N AU28 USB3Tn2 USBP1N B25 USB_PN1 36
USB3Tn3 USBP1P USB_PP1 36
Disabled in HM70 AY30 C26
AU26 USB3Tn4 USBP2N A26 VerC: Update minicard USB to port to for co_lay HM70
36 USB3_TX1_P USB3Tp1 USBP2P Swain 111206
AY26 K28
36 USB3_TX2_P AV28 USB3Tp2 USBP3N H28 CAM_USB_PN3 24
AW30 USB3Tp3 USBP3P E28 CAM_USB_PP3 24
Disabled in HM70
USB3Tp4 USBP4N D28
+V3.3S USBP4P C28
USBP5N A28
USBP5P C29 HM75/HM76 disable Port 6/7, HM70 disable port 4/5/6/7/12/13
USBP6N B29
R88 8.2K R0402 INT_PIRQA# K40 USBP6P N28 NM70 disable port 4/5/6/7/12/13
R60 8.2K R0402 INT_PIRQB# K38 PIRQA# USBP7N M28
H38 PIRQB# USBP7P L30

PCI
R62 8.2K R0402 INT_PIRQC#
G38 PIRQC# USBP8N K30 MINICARD_USB_PN1 31
R53 8.2K R0402 INT_PIRQD#
PIRQD# USBP8P MINICARD_USB_PP1 31
G30
USBP9N USB_PN9 36
GNT3/GPIO55:A16 swap override Strap R396 10K R0402 GPIO50 C46 E30
REQ1# / GPIO50 USBP9P USB_PP9 36
C44 C30

USB
Low = A16 swap R58 10K R0402 GPIO52
override E40 REQ2# / GPIO52 USBP10N A30 USB_CR_PN8 32
R48 10K R0402 GPIO54
High = Default REQ3# / GPIO54 USBP10P USB_CR_PP8 32
L32
R78 8.2K R0402 GPIO51 D47 USBP11N K32
ns T72 ICTP GPIO53 E42 GNT1# / GPIO51 USBP11P G32
B
+V3.3S R77 8.2K R0402 ns GPIO55 F46 GNT2# / GPIO53 USBP12N E32 B
Internal PU20K ns GNT3# / GPIO55 USBP12P C32 HM70 disable port 12/13
USBP13N A32
R52 10K R0402 SATA_ODD_DA# R83 8.2K R0402 INT_PIRQE# G42 USBP13P
SATA_ODD_DA# G40 PIRQE# / GPIO2 +V3.3AL
27,33 SATA_ODD_DA# C42 PIRQF# / GPIO3 C33
R395 10K R0402 INT_PIRQG# USB_BIAS R389 22.6,1%
R73 10K R0402 INT_PIRQH# D44 PIRQG# / GPIO4 USBRBIAS# R0402
+V3.3S PIRQH# / GPIO5 OC0# R787 10K R0402
B33 ns
T12 PCI_PME K10 USBRBIAS OC2# R387 10K R0402
ICTP ns Internal PU20K PME#
PLT_RST# C6 A14 OC0# R788 0 R0402 OC1# R47 10K R0402
PLTRST# OC0# / GPIO59 K20 USB_OC#0 36
OC1#
OC1# / GPIO40 B17 OC2# OC3# R371 10K R0402
H49 OC2# / GPIO41 C16 OC3#
R84 22 R0402 H43 CLKOUT_PCI0 OC3# / GPIO42 L16 OC4# OC5# R28 10K R0402
33 CLK_EC_PCI CLKOUT_PCI1 OC4# / GPIO43
R398 22 R0402 PCI_CLKFB_R J48 A16 OC5#
16 PCI_CLKFB CLKOUT_PCI2 OC5# / GPIO9
K42 D14 OC6# OC6# R41 10K R0402
R43 22 R0402 PCI_CLK_DEBUG_R H40 CLKOUT_PCI3 OC6# / GPIO10 C14 OC7#
31 PCI_CLK_DEBUG CLKOUT_PCI4 OC7# / GPIO14 OC7# R386 10K R0402

CPT_PPT_Rev_0p5 OC4# R791 10K R0402

A A
TOPSTAR TECHNOLOGY
杨华明(Sky Yang)
Page Name PCH PCI/USB
Size Project Name Rev
A3 CL42 EVT
A
Date: Wednesday, January 09, 2013 Sheet 19 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

+V3.3AL 7,15,16,17,19,22,24,28,31,33,40,43,45
+V3.3S 7,14,15,16,17,18,19,21,22,24,25,29,30,31,32,33,34,35,40,41,42,43,44,45,47
+V1.8S 10,21,40,45
+V3.3SB 7,15,17,22,28,31,33,35,37,38,39,45

+V3.3S
U12F
Internal PU20K
+V3.3S R101 10K R0402 GPIO0 T7 C40
BMBUSY# / GPIO0 TACH4 / GPIO68 SATA_ODD_PWRGT 27
EXTSMI# A42 B41 R375 10K +V3.3S
R393 10K R0402 EXTSMI# 33 EXTSMI# TACH1 / GPIO1 TACH5 / GPIO69 R0402
D D
USB30SMI# H36 C41 R392 100K
R61 10K R0402 EC_RUNTIME_SCI# TACH2 / GPIO6 TACH6 / GPIO70 R0402
33 EC_RUNTIME_SCI# EC_RUNTIME_SCI# E38 A40 R391 100K
R429 10K R0402 SATA_ODD_PRSNT# +V3.3AL TACH3 / GPIO7 TACH7 / GPIO71 R0402
T68 ns C10
R42 10K R0402 USB30SMI# ICTP Internal PU20K GPIO8
R381 10K LAN_PHY C4
R0402 LAN_PHY_PWR_CTRL / GPIO12
+V3.3SB R397 1K GPIO15 G2 P4
GPIO15 A20GATE H_A20GATE 33
+V3.3S R0402 Internal PD20K
R39 10K GPIO27 AU16 H_PECI 7
ns R0402 R427 10K SATA4GP U2 PECI
R114 10K GPIO24 R0402 SATA4GP / GPIO16 P5
RCIN# H_RCIN# 33
ns R0402
R59 10K GPIO17 D40 AY11

GPIO
TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD 7
R0402 Internal PU20K

CPU/MISC
R100 10K GPIO22 T5 AY10 THERMTRIP_R# R126 390,5%
SCLOCK / GPIO22 THRMTRIP# THERMTRIP# 7,30
GPIO8: Internal pull-up R0402 R0402
Reserved +V3.3AL R55 10K GPIO24 E8 T14
R0402 GPIO24 INIT3_3V# Internal PU20K
GPIO28 PLL on die VR enable R54 0 R0402 GPIO27 E16 AY1 DF_TVS DF_TVS: DMI and FDI Tx/Rx Termination
17,31,34 PCIE_WAKE# GPIO27 DF_TVS Voltage select(Internal pull down 20K)
Enable: High(Default) +V3.3S DS3
Disable: Low R97 10K GPIO28 P8 +V1.8S
+V3.3AL GPIO28
R0402 Internal PU20K AH8
R399 10K STP_PCI# K1 TS_VSS1
GPIO36/37: Internal pull-down 20K R0402 STP_PCI# / GPIO34 AK11
Reserved (When PWROK sampled) T73 ns K4 TS_VSS2
This signal should not be pulled high when ICTP GPIO35 AH10
C +V3.3S strap is sampled R107 20K Project_Code0 V8 TS_VSS3 R151 R160 C
The pull-up or pull-down is not active when R0402 SATA2GP / GPIO36 AK10 2.2K
1K
PLTRST# is NOT asserted. Project_Code1 M5 TS_VSS4
SATA3GP / GPIO37 R0402 R0402
Internal PD20K
Project_Code2 N2 P37 ns
SLOAD / GPIO38 NC_1 DF_TVS R152 1K
M3 H_SNB_IVB# 7
Project_Code3 R0402
R91 R410 R407 R116 SDATAOUT0 / GPIO39 Don't know how to used
200K 200K 200K 200K R110 10K R0402 GPIO48 V13 BG2 swain 100604
R0402 R0402 R0402 R0402 SDATAOUT1 / GPIO48 VSS_NCTF_15
ns ns SATA_ODD_PRSNT# V3 BG48
27 SATA_ODD_PRSNT# SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
Project_Code0
Project_Code1 GPIO57 D6 BH3
Project_Code2 GPIO57 VSS_NCTF_17
Project_Code3 BH47
VSS_NCTF_18
A4 BJ4
EC Code: +V3.3AL VSS_NCTF_1 VSS_NCTF_19
R85 R413 R408 F41 000 A44 BJ44
10K 10K 10K F42 001 VSS_NCTF_2 VSS_NCTF_20
ns ns TU142 010 A45 BJ45
TU151 011 R65 VSS_NCTF_3 VSS_NCTF_21
SU341 100 10K A46 BJ46

NCTF
CL341 0011 R0402 VSS_NCTF_4 VSS_NCTF_22
TU131 101 Normal ODD A5 BJ5
CL42 110 GPIO57 VSS_NCTF_5 VSS_NCTF_23
A6 BJ6
VSS_NCTF_6 VSS_NCTF_24
R66 B3 C2
B
10K VSS_NCTF_7 VSS_NCTF_25 B
R0402 B47 C48
Zero power ODD VSS_NCTF_8 VSS_NCTF_26
BD1 D1
VSS_NCTF_9 VSS_NCTF_27
BD49 D49
VSS_NCTF_10 VSS_NCTF_28
F42 VerB: Add gpio57 as a BIOS BE1 E1
strapping for PM/GM 20110820 VSS_NCTF_11 VSS_NCTF_29
BE49 E49
VSS_NCTF_12 VSS_NCTF_30
BF1 F1
VSS_NCTF_13 VSS_NCTF_31
BF49 F49
VSS_NCTF_14 VSS_NCTF_32

CPT_PPT_Rev_0p5

A A
TOPSTAR TECHNOLOGY
杨华明(Sky Yang)
Page Name PCH GPIO
Size Project Name Rev
A3 CL42 EVT
A
Date: Wednesday, January 09, 2013 Sheet 20 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

+V1.8S 10,20,40,45
+V3.3S 7,14,15,16,17,18,19,20,22,24,25,29,30,31,32,33,34,35,40,41,42,43,44,45,47
+VCCVRM 22
+V1.5S 7,10,31,45
+V1.05S 6,7,9,15,16,17,22,30,41,44,47

D D

+V3.3S

+V1.05S
U12G POWER
1.7A AA23 U48 68mA VCCADAC FB8 1 2 FB0603
AC23 VCCCORE[1] VCCADAC
AD21 VCCCORE[2] 120ohm@100MHz,500mA

CRT
AD23 VCCCORE[3] U47 C34 C35 C25
C102 C52 C55 C62 AF21 VCCCORE[4] VSSADAC C0402 C0402 C0805
VCCCORE[5]

VCC CORE
10uf/6.3V 1uf/10V 1uf/10V 1uf/10V AF23 0.01uF/16V,X7R 0.1UF/10V,X7R 10uf/6.3V
C0805 C0402 C0402 C0402 AG21 VCCCORE[6] +V3.3S
AG23 VCCCORE[7]
AG24 VCCCORE[8] AK36 1mA
AG26 VCCCORE[9] VCCALVDS +V1.8S
AG27 VCCCORE[10] AK37
AG29 VCCCORE[11] VSSALVDS
AJ23 VCCCORE[12]
AJ26 VCCCORE[13] AM37 VCCTX_LVDS FB11 1 2 FB0603

LVDS
40mA
AJ27 VCCCORE[14] VCCTX_LVDS[1]
AJ29 VCCCORE[15] AM38 120ohm@100MHz,500mA
AJ31 VCCCORE[16] VCCTX_LVDS[2] C69 C67 C71
VCCCORE[17] AP36 C0402 C0402 C0805
VCCTX_LVDS[3] 0.01uF/16V,X7R 0.01uF/16V,X7R 10uf/6.3V
AP37
+V1.05S AN19 VCCTX_LVDS[4]
C VCCIO[28] C
+V3.3S
FB16 1 2 FB0603 VCCAPLL BJ22
VCCAPLLEXP
120ohm@100MHz,500mA C106
V33
AN16 VCC3_3[6]

HVCMOS
ns VCCIO[15]
1uf/10V C38
C0402 AN17 0.1UF/10V,X7R
ns VCCIO[16] V34 C0402
VCC3_3[7]
AN21
+V1.05S VCCIO[17]
AN26 +VCCVRM +V1.5S
3.7A VCCIO[18] +VCCVRM
AN27 AT16 167mA
VCCIO[19] VCCVRM[3] +V1.05S
AP21 R118 0
C82 C46 C54 C48 C39 VCCIO[20] R0603
C0805 C0402 C0402 C0402 C0402 AP23 AT20 47mA
10uf/6.3V 1uf/10V 1uf/10V 1uf/10V 1uf/10V VCCIO[21] VCCDMI[1]
VCCVRM:Internal PLL and VRMs
AP24 +V1.05S

DMI
C50 1.5V for Mobile,1.8V for Desktop
VCCIO[22] C0402

VCCIO
AP26 AB36 70mA 1uf/10V
VCCIO[23] VCCCLKDMI
AT24 C78
VCCIO[24] C0402
1uf/10V
AN33 +V1.8S
VCCIO[25]
B AN34 AG16 B
2mA
+V3.3S VCCIO[26] VCCDFTERM[1]
C66
C533 BH29 AG17 C0402
C0402 VCC3_3[3] VCCDFTERM[2] 0.1UF/10V,X7R
0.1UF/10V,X7R
DFT / SPI
C540 +VCCVRM AJ16
C0402 VCCDFTERM[3]
+V1.05S 0.1UF/10V,X7R AP16
VCCVRM[2] AJ17
FB12 VCCDFTERM[4]
1 2 FB0603 VCCFDIPLL BG6
VccAFDIPLL
120ohm@100MHz,500mA +V1.05S +V3.3S
ns AP17
VCCIO[27] V1 10mA
FDI

VCCSPI
+V1.05S AU20 C63
VCCDMI[2] C0402
1uf/10V
CPT_PPT_Rev_0p5

A A
TOPSTAR TECHNOLOGY
杨华明(Sky Yang)
Page Name PCH PWR 1/2
Size Project Name Rev
A3 CL42 EVT
A
Date: Wednesday, January 09, 2013 Sheet 21 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

+V1.05S +V1.8S 10,20,21,40,45


U12J POWER +V1.05S +V3.3S
+VCCVRM
7,14,15,16,17,18,19,20,21,24,25,29,30,31,32,33,34,35,40,41,42,43,44,45,47
21
FB9
1 2 FB0603 +V1.5S 7,10,21,31,45
ns VCCACLK AD49 N26
+V3.3AL VCCACLK VCCIO[29] +V1.05S 6,7,9,15,16,17,21,30,41,44,47
120ohm@100MHz,500mA
+V3.3SB P26 +V3.3AL 7,15,16,17,19,20,24,28,31,33,40,43,45
VCCIO[30] C59 +V5AL_PCH 45
1mA R102 R0402 noDS3 T16
VCCDSW3_3 P28 1uf/10V +V5S 15,16,24,25,27,28,29,30,40,42,44,45,47
0 C37 0.1UF/10V,X7R VCCIO[31] PCH_EC_RTC 15,17
R113 R0402 DS3 C0402 C0402
+V3.3S +V3.3SB 7,15,17,20,28,31,33,35,37,38,39,45
0 S3
VerC: Add R113 tie to +V3.3SB support deep C42 V12 T27
Swain 111206 ns 0.1UF/10V,X7R DCPSUSBYP VCCIO[32]
C0402 T29 +V3.3AL
FB7 1 2 FB0603 VCC_CLK33 T38 VCCIO[33]
VCC3_3[5]
D D
120ohm@100MHz,500mA FB13 T23 95mA
C44 C31 1 2 FB0603 ns BH23 VCCSUS3_3[7]
+V1.05S VCCAPLLDMI2
C0805 C0402 120ohm@100MHz,500mA T24 C32 C29
10uf/6.3V 1uf/10V AL29 VCCSUS3_3[8] C0402 C0402
VCCIO[14] V23 0.1UF/10V,X7R 0.1UF/10V,X7R
VCCSUS3_3[9]

USB
C74 0.1UF/10V,X7R AL24 V24
C0402 DCPSUS[3] VCCSUS3_3[10]
ns P24
VCCSUS3_3[6] +V1.05S D12
AA19 +V3.3AL
VCCASW[1] T26
1
AA21 VCCIO[34] SOD323 +V5AL_PCH
VCCASW[2] LRC LMDL914T1G 100V 200mA
AA24 M26 1mA R50 10
VCCASW[3] V5REF_SUS R0402
AA26 C80 C19

Clock and Miscellaneous


+V1.05S VCCASW[4] AN23 C0402 ns C0402
AA27 DCPSUS[4] 1uf/10V 0.1UF/10V,X7R
VCCASW[5] AN24 D13
VCCSUS3_3[1] +V3.3AL
903mA CRB have two pcs 22uF ,three pcs 1uF AA29 +V3.3S
VCCASW[6] 1
+V5S
C97 C49 C57 C79 C51 AA31 SOD323
C0805 C0805 C0402 C0402 C0402 VCCASW[7] LRC LMDL914T1G 100V 200mA
10uf/6.3V 10uf/6.3V 1uf/10V 1uf/10V 1uf/10V AC26 P34 1mA R21 10
VCCASW[8] V5REF R0402
+V3.3AL
AC27 C27
VCCASW[9] N20 C0402
C AC29 VCCSUS3_3[2] 1uf/10V C

PCI/GPIO/LPC
VCCASW[10] N22 C36
AC31 VCCSUS3_3[3] C0402
VCCASW[11] P20 1uf/10V
AD29 VCCSUS3_3[4]
VCCASW[12] P22 +V3.3S
AD31 VCCSUS3_3[5]
VCCASW[13]
W21 AA16 228mA
VCCASW[14] VCC3_3[1]
W23 W16 C47 C300 C480
VCCASW[15] VCC3_3[8] C0402 C0402 C0402
W24 T34 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R
VCCASW[16] VCC3_3[4]
W26
VCCASW[17]
+V1.05S W29
VCCASW[18]
W31 AJ2 +V1.05S
FB14 1 2 FB0603 80mA VCCADPLLA VCCASW[19] VCC3_3[2]
W33
120ohm@100MHz,500mA VCCASW[20] AF13
C33 VCCIO[5]
C96 C103 C156
C0402 N16 C64
10uf/6.3V 1uf/10V ns 10uf/6.3V +VCCVRM 0.1UF/10V,X7R DCPRTC AH13 C0402
C0805 C0402 C0805 VCCIO[12] 1uf/10V
Y49 AH14 +V1.05S
VCCVRM[4] VCCIO[13]

B CRB上每路用了一个220uF AF14 B
+V1.05S VCCADPLLA BD47 VCCIO[6] FB10
VCCADPLLA AK1 VCCSATAPLL 1 2 FB0603

SATA
+V1.05S VCCADPLLB BF47 VCCAPLLSATA 120ohm@100MHz,500mA
FB15 1 2 FB0603 80mA VCCADPLLB VCCADPLLB C56 ns
AF11 +V1.05S C0805
VCCVRM[1] +VCCVRM
120ohm@100MHz,500mA AF17 10uf/6.3V
55mA AF33 VCCIO[7] ns
C101 C100 C155 VCCDIFFCLKN[1]
C75 C73 C65 AF34 AC16
10uf/6.3V 1uf/10V ns 10uf/6.3V C0402 C0402 C0402 AG34 VCCDIFFCLKN[2] VCCIO[2]
C0805 C0402 C0805 1uf/10V 1uf/10V 1uf/10V VCCDIFFCLKN[3] AC17 C43
VCCIO[3] C0402
95mA AG33 AD17 1uf/10V
VCCSSC VCCIO[4]

C40 C0402 V16


0.1UF/10V,X7R DCPSST +V1.05S

C45 C0402 T17 T21


+V1.05S 0.1UF/10V,X7R V19 DCPSUS[1] VCCASW[22]
ns DCPSUS[2]
MISC

V21
VCCASW[23]
BJ8
CPU

R782 0 1mA
R0402 V_PROC_IO T19
C321 C322 C481 PCH_EC_RTC VCCASW[21]
C0805 C0402 C0402 +V3.3AL
4.7uf/10V 0.1UF/10V,X7R 0.1UF/10V,X7R
A
A22 P32 10mA A
RTC

VCCRTC VCCSUSHDA
HDA

TOPSTAR TECHNOLOGY
C297 C295 C298 C28
C0402 C0402 C0402 CPT_PPT_Rev_0p5 C0402 杨华明(Sky Yang)
0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R Page Name PCH PWR 2/2
Size Project Name Rev
A3 CL42 EVT
A
Date: Wednesday, January 09, 2013 Sheet 22 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

U12I

AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
AY8 VSS[161] VSS[261] K39
U12H B11 VSS[162] VSS[262] K46
H5 B15 VSS[163] VSS[263] K7
VSS[0] B19 VSS[164] VSS[264] L18
AA17 AK38 B23 VSS[165] VSS[265] L2
AA2 VSS[1] VSS[80] AK4 B27 VSS[166] VSS[266] L20
AA3 VSS[2] VSS[81] AK42 B31 VSS[167] VSS[267] L26
AA33 VSS[3] VSS[82] AK46 B35 VSS[168] VSS[268] L28
AA34 VSS[4] VSS[83] AK8 B39 VSS[169] VSS[269] L36
D D
AB11 VSS[5] VSS[84] AL16 B7 VSS[170] VSS[270] L48
AB14 VSS[6] VSS[85] AL17 F45 VSS[171] VSS[271] M12
AB39 VSS[7] VSS[86] AL19 BB12 VSS[172] VSS[272] P16
AB4 VSS[8] VSS[87] AL2 BB16 VSS[173] VSS[273] M18
AB43 VSS[9] VSS[88] AL21 BB20 VSS[174] VSS[274] M22
AB5 VSS[10] VSS[89] AL23 BB22 VSS[175] VSS[275] M24
AB7 VSS[11] VSS[90] AL26 BB24 VSS[176] VSS[276] M30
AC19 VSS[12] VSS[91] AL27 BB28 VSS[177] VSS[277] M32
AC2 VSS[13] VSS[92] AL31 BB30 VSS[178] VSS[278] M34
AC21 VSS[14] VSS[93] AL33 BB38 VSS[179] VSS[279] M38
AC24 VSS[15] VSS[94] AL34 BB4 VSS[180] VSS[280] M4
AC33 VSS[16] VSS[95] AL48 BB46 VSS[181] VSS[281] M42
AC34 VSS[17] VSS[96] AM11 BC14 VSS[182] VSS[282] M46
AC48 VSS[18] VSS[97] AM14 BC18 VSS[183] VSS[283] M8
AD10 VSS[19] VSS[98] AM36 BC2 VSS[184] VSS[284] N18
AD11 VSS[20] VSS[99] AM39 BC22 VSS[185] VSS[285] P30
AD12 VSS[21] VSS[100] AM43 BC26 VSS[186] VSS[286] N47
AD13 VSS[22] VSS[101] AM45 BC32 VSS[187] VSS[287] P11
AD19 VSS[23] VSS[102] AM46 BC34 VSS[188] VSS[288] P18
AD24 VSS[24] VSS[103] AM7 BC36 VSS[189] VSS[289] T33
AD26 VSS[25] VSS[104] AN2 BC40 VSS[190] VSS[290] P40
AD27 VSS[26] VSS[105] AN29 BC42 VSS[191] VSS[291] P43
AD33 VSS[27] VSS[106] AN3 BC48 VSS[192] VSS[292] P47
AD34 VSS[28] VSS[107] AN31 BD46 VSS[193] VSS[293] P7
AD36 VSS[29] VSS[108] AP12 BD5 VSS[194] VSS[294] R2
AD37 VSS[30] VSS[109] AP19 BE22 VSS[195] VSS[295] R48
AD38 VSS[31] VSS[110] AP28 BE26 VSS[196] VSS[296] T12
AD39 VSS[32] VSS[111] AP30 BE40 VSS[197] VSS[297] T31
C AD4 VSS[33] VSS[112] AP32 BF10 VSS[198] VSS[298] T37 C
AD40 VSS[34] VSS[113] AP38 BF12 VSS[199] VSS[299] T4
AD42 VSS[35] VSS[114] AP4 BF16 VSS[200] VSS[300] W34
AD43 VSS[36] VSS[115] AP42 BF20 VSS[201] VSS[301] T46
AD45 VSS[37] VSS[116] AP46 BF22 VSS[202] VSS[302] T47
AD46 VSS[38] VSS[117] AP8 BF24 VSS[203] VSS[303] T8
AD8 VSS[39] VSS[118] AR2 BF26 VSS[204] VSS[304] V11
AE2 VSS[40] VSS[119] AR48 BF28 VSS[205] VSS[305] V17
AE3 VSS[41] VSS[120] AT11 BD3 VSS[206] VSS[306] V26
AF10 VSS[42] VSS[121] AT13 BF30 VSS[207] VSS[307] V27
AF12 VSS[43] VSS[122] AT18 BF38 VSS[208] VSS[308] V29
AD14 VSS[44] VSS[123] AT22 BF40 VSS[209] VSS[309] V31
AD16 VSS[45] VSS[124] AT26 BF8 VSS[210] VSS[310] V36
AF16 VSS[46] VSS[125] AT28 BG17 VSS[211] VSS[311] V39
AF19 VSS[47] VSS[126] AT30 BG21 VSS[212] VSS[312] V43
AF24 VSS[48] VSS[127] AT32 BG33 VSS[213] VSS[313] V7
AF26 VSS[49] VSS[128] AT34 BG44 VSS[214] VSS[314] W17
AF27 VSS[50] VSS[129] AT39 BG8 VSS[215] VSS[315] W19
AF29 VSS[51] VSS[130] AT42 BH11 VSS[216] VSS[316] W2
AF31 VSS[52] VSS[131] AT46 BH15 VSS[217] VSS[317] W27
AF38 VSS[53] VSS[132] AT7 BH17 VSS[218] VSS[318] W48
AF4 VSS[54] VSS[133] AU24 BH19 VSS[219] VSS[319] Y12
AF42 VSS[55] VSS[134] AU30 H10 VSS[220] VSS[320] Y38
AF46 VSS[56] VSS[135] AV16 BH27 VSS[221] VSS[321] Y4
AF5 VSS[57] VSS[136] AV20 BH31 VSS[222] VSS[322] Y42
AF7 VSS[58] VSS[137] AV24 BH33 VSS[223] VSS[323] Y46
AF8 VSS[59] VSS[138] AV30 BH35 VSS[224] VSS[324] Y8
AG19 VSS[60] VSS[139] AV38 BH39 VSS[225] VSS[325] BG29
AG2 VSS[61] VSS[140] AV4 BH43 VSS[226] VSS[328] N24
B AG31 VSS[62] VSS[141] AV43 BH7 VSS[227] VSS[329] AJ3 B
AG48 VSS[63] VSS[142] AV8 D3 VSS[228] VSS[330] AD47
AH11 VSS[64] VSS[143] AW14 D12 VSS[229] VSS[331] B43
AH3 VSS[65] VSS[144] AW18 D16 VSS[230] VSS[333] BE10
AH36 VSS[66] VSS[145] AW2 D18 VSS[231] VSS[334] BG41
AH39 VSS[67] VSS[146] AW22 D22 VSS[232] VSS[335] G14
AH40 VSS[68] VSS[147] AW26 D24 VSS[233] VSS[337] H16
AH42 VSS[69] VSS[148] AW28 D26 VSS[234] VSS[338] T36
AH46 VSS[70] VSS[149] AW32 D30 VSS[235] VSS[340] BG22
AH7 VSS[71] VSS[150] AW34 D32 VSS[236] VSS[342] BG24
AJ19 VSS[72] VSS[151] AW36 D34 VSS[237] VSS[343] C22
AJ21 VSS[73] VSS[152] AW40 D38 VSS[238] VSS[344] AP13
AJ24 VSS[74] VSS[153] AW48 D42 VSS[239] VSS[345] M14
AJ33 VSS[75] VSS[154] AV11 D8 VSS[240] VSS[346] AP3
AJ34 VSS[76] VSS[155] AY12 E18 VSS[241] VSS[347] AP1
AK12 VSS[77] VSS[156] AY22 E26 VSS[242] VSS[348] BE16
AK3 VSS[78] VSS[157] AY28 G18 VSS[243] VSS[349] BC16
VSS[79] VSS[158] G20 VSS[244] VSS[350] BG28
CPT_PPT_Rev_0p5 G26 VSS[245] VSS[351] BJ28
G28 VSS[246] VSS[352]
G36 VSS[247]
G48 VSS[248]
H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
A VSS[256] A
H34 TOPSTAR TECHNOLOGY
F3 VSS[257]
VSS[258] 杨华明(Sky Yang)
Page Name PCH GND
CPT_PPT_Rev_0p5 Size Project Name Rev
A3 CL42 EVT
A
Date: Wednesday, January 09, 2013 Sheet 23 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

+V3.3S 7,14,15,16,17,18,19,20,21,22,25,29,30,31,32,33,34,35,40,41,42,43,44,45,47
+VDC 37,39,40,41,44,47
D2
+V3.3S +V3.3AL 7,15,16,17,19,20,22,28,31,33,40,43,45
LRC LMDL914T1G 100V 200mA
+V5S 15,16,22,25,27,28,29,30,40,42,44,45,47
SOD323
+V5AL 33,36,39,41,43,45,46,47
33 LIDR# 1 +12V 27,39,45,46
ns R2
51K
D3 R0402
1
18 LVDS_BKLTEN
D 3 LCDCON1 D
BKLT_ON
LRC 30V 200mA 5ns WAFER Econn
R57 1K R0402 2 SOT23 CNS40_LCD_R1
33 HW_OFF_BKLT# C2 LCDVDD
C0402 R76 1K R0402
BKLT_ON_EC 33 41
1000pF/50V,X7R
LCDVDD 1 41 2
3 1 2 4
5 3 4 6
18 LVDS_YAM0 5 6 LVDS_YAM1 18
+12V CL341 VerC: Add R76 to Pretect EC 2012/12/25 7 8
+V3.3S 18 LVDS_YAP0 7 8 LVDS_YAP1 18
9 10
+V3.3AL 11 9 10 12
18 LVDS_YAM2 13 11 12 14 LVDS_CLKAP 18
18 LVDS_YAP2 15 13 14 16 LVDS_CLKAM 18
R519 17 15 16 18
100K Q2 19 17 18 20
19 20

5
6
7
8
9
R70 R0402 AON7410 +12V 21 22
21 22

D
51K SO8_26_130 F2 1.5A T-Fuse 23 24
R0603 ns 25 23 24 26
R0402 25 26
R549 200K 4 27 28
LCDVDD 18 EDID_CLK 27 28

G
R0402 1 2 FB28 29 30 EDID PWR
18 EDID_DATA 29 30

S
7V_LED_Panel(min) +5VAL_Camera 31 32 CAM_USB_PN3 19
Q4 100ohm@100MHz,3A BKLT_PWM 33 31 32 34 CAM_USB_PP3 19

3
2
1
SC70_6 R56 R242 +VDC 35 33 34 36 BKLT_ON
C 35 36 C
L2N7002DW1T1G 1K 510K C15 LCDVDD FB0805 FB27 37 38 D21 D22
37 38
6

1
R0402 R0402 0.01uF/25V,X7R 1 2 INVT_VDD 39 40
C0402 39 40 42 EGA10603V05A1-B EGA10603V05A1-B
2 5 C14 C20 C21 R72 300ohm@100MHz,2A 42 ESDPAD_R0402 ESDPAD_R0402
18 LVDS_VDDEN
2.2K FB0805 C1 C286 ns ns
1

2
C0402 10uf/6.3V C0805 R0402 6V_LED_Panel(min) C0603 0.1uF/25V,X7R
R475 0.1UF/10V,X7R C0805 10uf/6.3V ns 0.1uF/25V,X7R C0603
510K C18 ns
R0402 0.01uF/25V,X7R
c0402

LCDVDD +VDC +12V

6V_LED_Panel(min) +V5AL +V5S


R71
100 R98 R115
R0603 100K
R0402
100K
R0402
Camera R353 R354
7V_LED_Panel(min) 0 0
B Q3 R0805 R0805 B

3
SC70_6 +12V ns

LVDS_VDDEN 2 5 Stuff KBC controlled camera power. R356 0 R0805


L2N7002DW1T1G TU142 VerC. NO_CAM_SW +5VAL_Camera

100pF/50V,NPO
1

4
R357 Q26
500mA

5
6
7
8
9
C23 R92 100K AON7410

D
100K R0402 SO8_26_130
C0402 R0402 CAM_SW CAM_SW C288 C287
R4 100 R0402 ns R355 100K 4 0.1uF/10V,X7R 10uf/6.3V
33 EC_BKLT_PWM

G
R0402 C0402 C0805

S
CAM_SW
R735 100 R0402 BKLT_PWM
18 LVDS_BKLTCTL

3
2
1
3
R245
510K C536
R3 C3 R0402 0.01uF/25V,X7R
10K C0402 1 CAM_SW C0402
R0402 100pF/50V,NPO 33 Camera_ON# CAM_SW
Q27

2
R362 L2N7002LT1G
100K SOT23
+V3.3S +V3.3AL R0402 CAM_SW
CAM_SW TOPSTAR TECHNOLOGY
A R5 0 R0603 ns Robin A
Page Name
R7 0 R0603 EDID PWR LVDS&Inverter CONN
Size Project Name Rev
C4 Custom TU142 PVT
C
C0402
0.1UF/10V,X7R Date: Sunday, April 07, 2013 Sheet 24 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

+V5S 15,16,22,24,27,28,29,30,40,42,44,45,47
+V3.3S 7,14,15,16,17,18,19,20,21,22,24,29,30,31,32,33,34,35,40,41,42,43,44,45,47
+V3.3AL 7,15,16,17,19,20,22,24,28,31,33,40,43,45

GU4
C371 0.1uF/10V,X7R IFPC_TXD2N IFPC_TXD2P 1 10 IFPC_TXD2P IFPC_TXD2N
18 IN_D2- IFPC_TXD2P IFPC_TXD2N 2 D1+ NC4 9 IFPC_TXD2N IFPC_TXD2P HDMI_CON1
C370 0.1uF/10V,X7R
18 IN_D2+ D1- NC3
3 8 1
D GND_HDMI GND1 GND2 D2+ D
C364 0.1uF/10V,X7R IFPC_TXD0P 4 7 IFPC_TXD0P 2
18 IN_D0+ 5 D2+ NC2 6 3 D2 SHTELD
C365 0.1uF/10V,X7R IFPC_TXD0N IFPC_TXD0N
18 IN_D0- D2- NC1 IFPC_TXD1P 4 D2-
5 D1+
TVU1240R1A D1 SHTELD
IFPC_TXD1N 6
SON10_0D5_1 7 D1- 20 +V5_HDMI
8 D0+ GND1 21 +V5S
9 D0 SHTELD GND2
IFPC_TXC 10 D0- FB29
D23
11 CK+ 22 1 2 120ohm@100MHz,500mA
1
12 CK SHTELD GND3 23 SOD123
GU3 13 CK- GND4 1N5819W DIODESEMI FB0603
C367 0.1uF/10V,X7R IFPC_TXC# 1 10 IFPC_TXC# 14 CEC C158 R219
18 MCH_CLK_D4- IFPC_TXC 2 D1+ NC4 9 5VDDCCK_HDMI 15 RESERVED
C366 0.1uF/10V,X7R 0.1UF/10V,X7R 100K
18 MCH_CLK_D4+ D1- NC3 SCL
3 8 +V5_HDMI 5VDDCDA_HDMI 16 C0402 R0402
GND_HDMI GND1 GND2 SDA
C373 0.1uF/10V,X7R IFPC_TXD1N 4 7 17 GND_HDMI
18 IN_D1- 5 D2+ NC2 6 18 DCC/CEC_GND
C372 0.1uF/10V,X7R IFPC_TXD1P
18 IN_D1+ D2- NC1 19 +5V
HDMIHP_C
HP_DET
TVU1240R1A
hdmi_d_1b GND_HDMI GND_HDMI
SON10_0D5_1

C
GND_HDMI GND_HDMI F42 VerB: Changed HDMI_CON1 to the same with C03 20110820 C

06/08:HDMI CONN on MB-Zhouzm

+V3.3S +V3.3S +V5_HDMI

R250
GR23 4.7K

1
2.2K R0402
R0402 Q40
GND_HDMI
2 3 5VDDCCK_HDMI
18 GM_HDMI_DDC_CLK
C172
LBSS138LT1G C0402
sot23 10pF/50V,NPO

B +V5S GND_HDMI B

1
+V3.3S +V3.3S +V5_HDMI
IFPC_TXD2N R289 680 R0402 +V3.3S GQ2
3

IFPC_TXD2P R292 680 R0402 HDMIHP_C 3 2


MCH_HDMI_HPD 18
Q17 GR24 R231

1
IFPC_TXD1N R288 680 R0402 LBSS138LT1G 2.2K 4.7K
sot23 1 L2N7002LT1G R0402 Q41 R0402
IFPC_TXD1P R287 680 R0402 GR12 SOT23
100K R806 2 3 5VDDCDA_HDMI
18 GM_HDMI_DDC_DATA
2

IFPC_TXD0N R274 680 R0402 R0402 1M


R0402 C162
IFPC_TXD0P R275 680 R0402 LBSS138LT1G C0402
sot23 10pF/50V,NPO
IFPC_TXC# R272 680 R0402

IFPC_TXC R273 680 R0402


GND_HDMI GND_HDMI GND_HDMI

TOPSTAR TECHNOLOGY
A Robin A
Page Name HDMI CONN
Size Project Name Rev
B TU142 PVT
C
Date: Wednesday, January 09, 2013 Sheet 25 of 51
PROPERTY NOTE: this document contains information confidential and property to
重点注意Layout走线!!! TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

D D

C C

B B

TOPSTAR TECHNOLOGY
Robin
Page Name HDMI DB CONN
Size
A A
Project Name
TU142 PVT
Rev A
C
Date: Wednesday, January 09, 2013 Sheet 26 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1

+V5S 15,16,22,24,25,28,29,30,40,42,44,45,47
EC_RTC 15,39,45
+12V 24,39,45,46

SATA HDD Conn

D D
+V5S 21
Average 1A,Peak 1.5A 1 21 2
FB24 0 R0805 C487 0.01uF/16V,X7R C0402 3 1 2 4
V_HDD 15 SATA_TXP0 3 4
15 SATA_TXN0 C486 0.01uF/16V,X7R C0402 5 6
C11 7 5 6 8
C0805 C246 C245 C399 0.01uF/16V,X7R C0402 9 7 8 10
15 SATA_RXN0 9 10
4.7uf/10V 0.1UF/10V,X7R 0.1UF/10V,X7R 15 SATA_RXP0 C400 0.01uF/16V,X7R C0402 11 12 V_HDD
C0402 C0402 13 11 12 14
15 13 14 16
Close to connector as possible 17 15 16 18
the same distance to connector
19 17 18 20
19 20 22
22

SATA_HDD1
WAFER Econn
CNS2X10_1_R

TU142 VerB: Changed SATA_HDD1 to 20pin


Wafer CONN 620901000004 2011-12-20
C C

SATA_CON1 SATAODD_B1 SATAODD_B2

S1
SATA ODD Conn 15
15
SATA_TXP5
SATA_TXN5
C485
C484
0.01uF/16V,X7R C0402
0.01uF/16V,X7R C0402
S2
S3
S4
GND1
A+
A- GND6
14

C335 0.01uF/16V,X7R C0402 S5 GND2


15 SATA_RXN5 S6 B-
C331 0.01uF/16V,X7R C0402 Screw 2*5mm Screw 2*5mm
15 SATA_RXP5 S7 B+ ASSY ASSY
GND3
Zero power ODD
B +12V V_ODD R137 0 R0402 P1 B
20 SATA_ODD_PRSNT# P2 DP
+V5S
P3 +5V_1
R465 0 R0402 P4 +5V_2 15
19,33 SATA_ODD_DA# P5 MD GND7
EC_RTC
P6 GND4
PQ50 GND5
R471 AON7410
200K SO8_26_130
5
6
7
8
9

R469 R0402 Zero Power ODD JFS SATA ODD D_BOT


D

51K Zero Power ODD


R0402 R466 R468 SATAODD_D_50A
4 0 0 V_ODD
G

Zero Power ODD R0805 R0805


S

R472 Normal ODD Normal ODD


Q29 200K
Average 1A,Peak 1.5A
3
2
1

SC70_6 R470 R0402


L2N7002DW1T1G 1K Zero Power ODD
6

Zero Power ODD R0402


Zero Power ODD R474 C9
2 5 1M PC196 C0805 C537 C538
20 SATA_ODD_PWRGT
R0402 0.01uF/25V,X7R 4.7uf/10V 0.1UF/10V,X7R 0.1UF/10V,X7R
1

R464 Zero Power ODD C0402 C0402 C0402 TOPSTAR TECHNOLOGY


1K R467 Zero Power ODD
A R0402 510K PC203 Robin A
Zero Power ODD R0402 0.01uF/25V,X7R Page Name SATA HDD&ODD
Zero Power ODD c0402
Size Project Name Rev
ns B TU142 PVT
C
Date: Wednesday, January 09, 2013 Sheet 27 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1
+V5S 15,16,22,24,25,27,29,30,40,42,44,45,47
+V3.3AL 7,15,16,17,19,20,22,24,31,33,40,43,45
+V3.3SB 7,15,17,20,22,31,33,35,37,38,39,45

Touch Pad Conn


D
Power Button D
+V5S +V5S
IOPR2改为1M,IOPR4改为10K,
解决电池电压低时无法开机问题

R133 R132 PSW1


10K 10K 3 4 PWRSWVCC1 PR416 10K R0402
3 4 HV_Isense_SYSP 37
R0402 R0402
1 2 PR417 30K PWR_SW_VCC2
TPCLK 1 2 R0402 PWR_SW_VCC2 39
33 TPCLK
T1.5
BUTTON4_S

1
TPDAT PESD1
33 TPDAT
PC350 PC351 ESDPAD_R0402
1000pF/50V,X7R 1000pF/50V,X7R EGA1-0603-V05
C0402 C0402

2
+V5S
C C
+V5S
1
1 2 TPDAT
7 2 3 TPCLK +V3.3SB
7 3 4 C109
8 4 5 C107 1uf/10V
8 5 6 C53 C0402 C0402
6 22pF/50V,NPO 0.1UF/10V,X7R R580
C0402 10K
TP_CON1 R0402
CNS6_0D5_RA1
FPC Cotex
PWRSW# 33

3
C379
PWR_SW_VCC2 1 C0402
B 1000pF/50V,X7R B
+V3.3AL Q31

2
R543 L2N7002LT1G
1M SOT23
R0402

R135 R134
47K 47K C108
R0402 R0402 C0402
ns ns 0.1UF/10V,X7R TOPSTAR TECHNOLOGY
Robin
TPDAT Page Name TP CONN&PWRSW
TPCLK Size Project Name
A Custom TU142 PVT
Rev A
C
Date: Wednesday, January 09, 2013 Sheet 28 of 51
Install R134,R135 for KB used PROPERTY NOTE: this document contains information confidential and property to
Swain 100812 TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

+V5S 15,16,22,24,25,27,28,30,40,42,44,45,47
+V3.3S 7,14,15,16,17,18,19,20,21,22,24,25,30,31,32,33,34,35,40,41,42,43,44,45,47
R342 75 R0402 SURR_OUT_R

R627 75 R0402 SURR_OUT_L

MIC1-VREFO_R 0 R263 MIC2_REF

GND_AUD
R0402 HP_COMBO
MIC1-VREFO-L R301 4.7K R0402 HP_SENSE
ns
MIC2-VREFO Q30

3
GND_AUD
L2N7002LT1G
SOT23
+V5U_AU +V5S
In order to prevent the built-in LDO damaged from C515 C516 Place next to pin 27 0 R279 1
over-voltage on +5VD or Standby power line. Use C520 C0603 C0402 FB39 120ohm@100MHz,500mA R0402
D D
the line suppressing device. C0603 2.2uf/10V 0.1uF/10V,X7R FB0603

2
2.2uf/10V

10uf/6.3V
C0805 C524
R1015
DIGITAL ANALOG HP_COMBO 200K
+V5S C521 GND_AUD R1017 R0402
C0603 AVDD 1K

1
2.2uf/10V R0402
FB34 C525 C526 ns ns
FB0805 AVDD
48mA C0805 C0402 MIC2_REF R1019 100 2 3
U7 10uf/6.3V 0.1uF/10V,X7R ns R0402 GND_AUD GND_AUD

36

35

34

33

32

31

30

29

28

27

26

25
Q32

C0805 C386
300ohm@100MHz,2A

4.7uf/10V
1

D36 C522 C523 G4 LMBT3904LT1G

VREF
CBP

CPVEE

LDO-CAP
CBN

HP-OUT-R

MIC1-VREFO-R
MIC1-VREFO-L

MIC2-VREFO

AVSS1
HP-OUT-L

AVDD1
SOD523 C0805 C0402 G5 GND SOT23 R1021
TVN S523 10uf/6.3V 0.1uF/10V,X7R G6 GND R1020 100K
GND ns 2.2K R0402
GND_AUD
2

37 24 R0402 ns
MOAT GND_AUD AVSS2 LINE1-R MIC_SENSE
38 23
FB35 AVDD2 LINE1-L 4.7uf/10V FB38
Spilt by DGND

3
FB0805 PVDD1 39 22 C272 C0805 EXT_MIC_L 300ohm@100MHz,2A GND_AUD Q28
GND_AUD PVDD1 MIC1-R FB0805 LBSS138LT1G
300ohm@100MHz,2A +INTSPL 40 21 C269 C0805 GND_AUD sot23
C517 C442 SPK-L+ MIC1-L 4.7uf/10V EXT_MIC_L_1 R1018 22k 1
C0805 C0402 -INTSPL 41 20 R0402
10uf/6.3V 0.1uF/10V,X7R SPK-L- MONO-OUT 300ohm@100MHz,2A

2
42 19 R478 20K,1% EXT_MIC_L_1 FB37 FB0805 R1022 1K EXT_MIC_L C383

43
PVSS1

PVSS2
ALC269Q-VB6-CG JDREF

Sense-B
18
R0402
GND_AUD R0402 10uf/6.3V
C0805
HP_SENSE

100pF/50V,NPO

100pF/50V,NPO
C0402 C390

C0402 C384
-INTSPR 44 17 MIC2-R C527 C0805 INT_MIC_L R1023
SPK-R- MIC2-R 4.7uf/10V 22k
+INTSPR 45 16 MIC2-L C528 C0805 R0402
300ohm@100MHz,2A SPK-R+ MIC2-L 4.7uf/10V
FB0805 FB33 PVDD2 46 15 GND_AUD
PVDD2 LINE2-R

GPIO0/DMIC-DATA
nsT82 EAPD 47 14

GPIO1/DMIC-CLK
C529 C530 EAPD LINE2-L
C C0805 C0402 48 13 Sense_A R306 39.2K,1% HP_SENSE C

SDATA-OUT
10uf/6.3V 0.1uF/10V,X7R SPDIFO Sense A R0402

SDATA-IN

DVDD-IO
GND_AUD GND_AUD GND_AUD

PCBEEP
ICTP G7 G1

BIT-CLK

RESET#
R376 20K,1% MIC_SENSE

DVDD1

DVSS2
GND GND G2

SYNC
Place next to pin 39 G8 R0402
Audio COMBO Jack

PD#
G9 GND GND G3
GND GND
+V3.3S QFNS48_0D4_1G GND_AUD

10

11

12
i-Phone type
50mA DIGITAL ANALOG

1
A_GPIO0

A_GPIO1
PD# of Codec pull up rails change from +V5S to +V3.3S. +V3.3S D31

PD#
TU142 VerC. (Include Thermal pad) EGA1-0603-V05
ESDPAD_R0402
C441 C440 ns Audio6_s2

2
0 R276 ns R976 C0805 C0402 C262 R0402_Short Audio Jack
R0402 1K 10uf/6.3V 0.1uF/10V,X7R C0402 R329 51K EXT_MIC_L_1 R383 0 ns 2 Mic
BTL_BEEP 33 5 Left
R0402 1uf/10V R0402 SURR_OUT_L FB0805 FB36
SHUTDOWN# SOD323 1 D33 300ohm@100MHz,2A 7 Det
T8 T2 C263 C264 6 Res
LRC LMDL914T1G 100V 200mA ns ns ICTPICTP C0402 C0402 R322 75K SURR_OUT_R FB0805 FB32 4 Right
SPKR 15
100pF/50V,NPO 1uf/10V R0402 300ohm@100MHz,2A 3 Gnd

2
AZALIA_CODEC_RST# 1 D34 D37 HP_MIC_OUT1

HP_COMBO
15 AZALIA_CODEC_SDOUT C378 R6 C382 R8 EGA1-0603-V05 EGA1-0603-V05
D35 R309 R321 R324 C0402 1K C0402 1K ESDPAD_R0402 ESDPAD_R0402
15 AZALIA_CODEC_BITCLK
LRC LMDL914T1G 100V 200mA 10K 4.7K 4.7K 100pF/50V,NPO 100pF/50V,NPO R0402 ns ns

1
SOD323 R326 33 R0402 R0402 R0402 GND_AUD +V5U_AU
R0402 15 AZALIA_SDATAIN0
R0402
For VB5 and VB6
15 AZALIA_CODEC_SYNC +V3.3S R1016 22k R0402
GND_AUD GND_AUD
15 AZALIA_CODEC_RST# GND_AUD GND_AUD

<<Attention>> C531 C518 TU142 VerB: Changed Audio Combo jack to i-phone
For power_on/off de-pop circuit and system booting warning signal: C0805 type and modify peripheral circuit for jack detect
Please System BIOS Engineer Note : C532 22pF/50V,NPO AZALIA_CODEC_BITCLK 10uf/6.3V 0.1uF/10V,X7R 2011-12-20
C0402 C0402
1. If you want the system make warning signal after power on , please
let EC_MUTE# High.
B 2. If your design want to system make warning signal(for explame CPU B
or Memory haven't been plugged in), please remove Q2 transistor.

3
+INTSPR 1 +INTSPL 1

3
-INTSPR 2 1 -INTSPL 2 1
2 2

4
INTSPKL1

4
INTSPKR1 Wafer
If HD_RESET high level is 1.5V(The signal level of HDA_Link are 1.5V) , Wafer Econn CNS2_V
please moidfy gate voltage of Q2 transistor to 1.5V; and use BSS138 CNS2_R
or 2SK3018 transistor
GND GND

TU142 VerB: Seperated Speaker CONN from 4PIN to 2PIN 2011-12-20


SURR_OUT_L SURR_OUT_R
GND_AUD GND_AUD
3

+V5S
Q23 Q22
Q25 Q24
1 1 AMP_SHDW 1 1
33 AMP_SHDW
L2N7002LT1G L2N7002LT1G L2N7002LT1G L2N7002LT1G
SOT23 SOT23 SOT23 SOT23
2

R625 MIC2-VREFO R486 4.7K


10K R461 0 R0402 ns R0402
FB21
R0402 +
R804 0 R0402 INT_MIC_L R347 1K 2 1 300ohm@100MHz,2A 1
SHUTDOWN# R0402 FB0805 2
R805 0 R0402
3

1
D16 C181
Q21 FB19 ESDPAD_R0402 MIC1
L2N7002LT1G FB0805 ns EGA1-0603-V05 100pF/50V,NPO Microphone
1 SOT23 300ohm@100MHz,2A ns C0402 BZ_D6027
33 AMP_SHDW

2
R626 ASSY
100K
2

R341 R0402 C519 C0402


10K 0.1uF/10V,X7R
A R0402 ns A

GND_AUD

TOPSTAR TECHNOLOGY
TU142 VerB: Add a MIC_CON1 on motherboard for B cover
MIC and reserved a MB position 2011-12-20 Robin
Page Name
AZALIA(ALC269)
Size Project Name Rev
Custom TU142 PVT
C
Date: Wednesday, January 09, 2013 Sheet 29 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

+V5S 15,16,22,24,25,27,28,29,40,42,44,45,47
+V3.3S 7,14,15,16,17,18,19,20,21,22,24,25,29,31,32,33,34,35,40,41,42,43,44,45,47

Over temperture Protect Circuit +V1.05S 6,7,9,15,16,17,21,22,41,44,47

D FAN Controller Circuit D

+V5S

+V3.3S

C290
R361 2.2uf/10V
10K C0603
ns +V3.3S
8 1 R0402
+V1.05S 7 GND EN/FON# 2 CPUFAN1
6 GND VIN 3 Vfan 1 4
5 GND VOUT 4 2 1 4 R404
GND VSET 3 2 5 10K
U9 +V3.3S D14 3 5 R0402
R330 P2793AB0/1.6*VSET 500mA SOD323 C26 WAFER

1
10K SO8_50_150 LRC LMDL914T1G 100V
10uf/6.3V
200mA CNS3_V
R0402 C0805
FAN_BACK 33
C C
R82
SHDN_LOCK# 43 4.7K
R0402

6
R332 10K 5 2 R81 200K
7,20 THERMTRIP# R0402 FAN1_V 33
Q19 R0402
C266 LMBT3904DW1T1G
4

1
R333 1000pF/50V,X7R SC70_6 C22 C291
100K C0402 C0805
R0402 4.7uf/10V 0.1UF/10V,X7R
C0402
3

Q20

1 L2N7002LT1G
33 ALT_ON SOT23
Use for temperature alarm driver.
2

R331
100K
R0402
Shut-Down
B B

Throttling/
Un-throttling

High-5V

Shut Down
CPU
VIN Middle-4V FAN1_V=3.30V,Vfan=5V
Throttling on
FAN1_V=2.65V,Vfan=4V
THRMTRIP# SHDN#
Low-3V
FAN1_V=1.98V,Vfan=3V
AND
THERM_ALERT# CPU Temperature
Throttling Off
VDC 0 85 90 95 100 50 55 60 65 70 75 80 85 90 95 100
Thermal (Degree)
sensor
TOPSTAR TECHNOLOGY
A Robin A
Page Name FAN/OTP
Size Project Name Rev
B TU142 PVT
C
Date: Wednesday, January 09, 2013 Sheet 30 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

+V3.3AL 7,15,16,17,19,20,22,24,28,33,40,43,45
+V1.5S 7,10,21,45
+V3.3SB 7,15,17,20,22,28,33,35,37,38,39,45
+V3.3S 7,14,15,16,17,18,19,20,21,22,24,25,29,30,32,33,34,35,40,41,42,43,44,45,47
+DATA4
+V3.3LAN 34
-DATA4
+V3.3LAN +V3.3LAN

1
D28 D27 +V3.3AL
D ESDPAD_R0402 ESDPAD_R0402 +V1.5S D
EGA1-0603-V05 EGA1-0603-V05 R323 R328 +V3.3LAN +V3.3S
ns ns 0 0 R1025 0

2
R0603 R0603 R0805
+V3.3SB
+V3.3AL_PCIE
+V3.3LAN R1026 0
+V3.3S_PCIE 500mA R0805 ns R611
10K R617
MPCIE1 R0402 10K
MINIPCIE_HALF_L6 ns R0402

52

24

48
28
2

6
ns
Keep USB2.0 Signal stub short

+3.3V0
+3.3V1

+1.5V0
+1.5V1
+1.5V2
+3.3VAUX
minicard_Wake#

minicard_CLKREQ#_R

90Ω/100MHz 0.5A
CHK12

3 4 -DATA4 36 46 ns
19 MINICARD_USB_PN1 2 1 L4_0805_SHORT +DATA4 38 USB_D- LED_WPAN# 44 T49
ICTP MPCIE_HALF_NUT1
19 MINICARD_USB_PP1 ns USB_D+ LED_WLAN# 42 WIRELESS_LED# 35
ns
C LED_WWAN# T47 C
ICTP R607 0 R0402
CL_RST1# 16
ns
11 22 R606 0 R0402
16 CLK_PCIE_MINICARD# 13 REFCLK- PERST# 1 minicard_Wake# BUF_PLT_RST# 7,19,33,34
R610 0 R0402

PCIE mini Card


16 CLK_PCIE_MINICARD REFCLK+ WAKE# 7 PCIE_WAKE# 17,20,34
minicard_CLKREQ#_R R616 0 R0402 ns
CLKREQ# minicard_CLKREQ# 16
31 D_BOT
16 PCIE_TXN4_WLAN 33 PETN0 32 R601 0 R0402 ns Mylar_MPCIE1
16 PCIE_TXP4_WLAN PETP0 SMB_DATA 30 CL_DATA1 16
R600 0 R0402 ns Mylar_MPCIE
SMB_CLK CL_CLK1 16
23 R684 10K R0402 +V3.3LAN
16 PCIE_RXN4_WLAN PERN0 +V3.3LAN
25
16 PCIE_RXP4_WLAN PERP0
CHANNEL_CLK
5
3
R685 0 R0402
BT_OFF# 33 PVC
T50 17 CHANNEL_DATA T52
ns ICTP ns ICTP R604
R792 0 R0402 Debug 19 RESERVED0 10K ASSY
7,19,33,34 BUF_PLT_RST# RESERVED1 R0402
R793 0 R0402 20 R605 0 R0402
37 RESERVED_DISABLE HW_RATIO_OFF# 33
R794 0 R0402 Debug
19 PCI_CLK_DEBUG 39 RESERVED_PCIE0
+V3.3LAN R1024 0 R0603 PCIE_39
R795 0 R0402 41 RESERVED_PCIE1 16
R796 0 R0402 Debug 43 RESERVED_PCIE2 RESERVED_SIM0 14
15,33 LPC_FRAME# 45 RESERVED_PCIE3 RESERVED_SIM1 12 +V3.3S_PCIE +V3.3AL_PCIE
R797 0 R0402 Debug
15,33 LPC_AD0 47 RESERVED_PCIE4 RESERVED_SIM2 10
B R798 0 R0402 Debug B
15,33 LPC_AD1 49 RESERVED_PCIE5 RESERVED_SIM3 8
R800 0 R0402 Debug C252 C254 C261 C255 C256
15,33 LPC_AD2 51 RESERVED_PCIE6 RESERVED_SIM4
R799 0 R0402 Debug 10uf/6.3V 0.1UF/10V,X7R 10uf/6.3V 0.1UF/10V,X7R 0.1UF/10V,X7R
15,33 LPC_AD3 RESERVED_PCIE7 C0805 C0402 C0805 C0402 C0402
BT_OFF# R736 0 R0402
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

WIFI Option和Debug Option +V1.5S


不可以同时上
PCIE MINI CARD
9
15
21
27
29
35
4
18
26
34
40
50
53
54
56
57
58
59
60
61
55

C251 C250 C249 C253


10uf/6.3V 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R
C0805 C0402 C0402 C0402
ns

TOPSTAR TECHNOLOGY
A Robin A
Page Name
PCIE MINI SLO
Size Project Name Rev
B TU142 PVT
C
Date: Wednesday, January 09, 2013 Sheet 31 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

+V3.3S 7,14,15,16,17,18,19,20,21,22,24,25,29,30,31,33,34,35,40,41,42,43,44,45,47
+V3.3AL 7,15,16,17,19,20,22,24,28,31,33,40,43,45

D D

2IN1 CONN

SD_D2_MS_D5
SD_D3_MS_D1
16 CLK_CR_48M
PWR_SW2
J2
SD_CD# 10 4
SD_CMD 2 CD VDD
C388 CMD 3 C260

24
23
22
21
20
19
ns C0402 U28 SD_D0_MS_D7 7 VSS1 6 C259 1uf/10V
100pF/50V,NPO SD_D1 8 DAT0 VSS2 0.1uF/10V,X7R C0402

XD_D7
SP14
SP13
SP12
SP11
CLK_IN
SD_D2_MS_D5 9 DAT1 12 C0402
R120 RREF 1 18 SD_CMD SD_D3_MS_D1 1 DAT2 G1 13
+V3.3S 6.2k,1% 2 RREF SP10 17 CD/DAT3 G2 14
C 19 USB_CR_PN8 3 DM GPIO0 16 5 G3 15
C
R0402 RTS5138-GR SD_CLK_MS_D2
19 USB_CR_PP8 4 DP SP9
QFNS24_0D5_0D9G 15 SD_CLK_MS_D2 SD_WP_MS_CLK 11 CLK G4
3V3_IN QFN24 SP8 SD_WP
5 14
PWR_SW2 CARD_3V3 SP7
VREG 6 13 SD_CD#
V18 SP6

XD_CD#
2in1 Cardreader Black
C391 C389 C394 G1
GND

SP1
SP2
SP3
SP4
SP5
C0805 C0402 C0402 G2 SD_MMC
4.7uf/10V 0.1UF/10V,X7R 1uf/10V GND
621001500002

7
8
9
10
11
12
SD_WP_MS_CLK

SD_D0_MS_D7
IC Bottom Ground
SD_D1

B B

TOPSTAR TECHNOLOGY
A Robin A
Page Name Cardreader(RTS5138)
Size Project Name Rev
B TU142 PVT
C
Date: Wednesday, January 09, 2013 Sheet 32 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR

5 4 3 2 1
5 4 3 2 1

+V3.3S 7,14,15,16,17,18,19,20,21,22,24,25,29,30,31,32,34,35,40,41,42,43,44,45,47
与3926不同点 +V3.3SB 7,15,17,20,22,28,31,35,37,38,39,45
+V3.3S +V3.3AL 7,15,16,17,19,20,22,24,28,31,40,43,45
+V5AL 24,36,39,41,43,45,46,47
Pin109与Pin114增加电压输入功能
R277 Pin103作为比较后的输出
10K +V3.3SB
R0402
Pin100/101增加FANFB2/3的功能 KB3930 KB9010
D17 Pin74增加PECI输入功能 GPIO function Pin68&70&71&72 Only GPO All GPIO

2
A20GATE Pin83/84/85/86增加配置为SMBUS2/3的功能 Pin63&64&65&66&75&76 Only GPI
20 H_A20GATE 1
Pin16增加配置为OWM的功能 R296 AD function 6 PCS AD 8PCS AD
+V3.3S 0 新增Pin73 AD6 & Pin74 AD7
LRC LMDL914T1G 100V 200mA EC_V3.3AL
FB22 R0805 PECI function at Pin74 at Pin118
SOD323 Pin109 VCIN0 Pin109 VCIN0

1
120ohm@100MHz,500mA HW Voltage Pin114 VCIN1 Pin102 VCIN1
R271 1 2 comparator PIn103 VCOUT PIn103 VCOUT1
10K Pin104 VCOUT0
R0402 V18R FB0603 C206 C225 C244 C223 C212 C232 GWG function No support Pin108 support
D D
D15 C0805 C0402 C0402 C0402 C0402 C0402 SPI function No Internal flash Internal flash 128KB
RCIN# C243 C211 C210 10uf/6.3V 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R Pin128&119&120 Add GPIO function
20 H_RCIN# 1
C0402 C0402 C0402 Pin127 Have TEST_CLKSPICLK1 No TEST_CLKSPICLK1
0.1UF/10V,X7R 0.1UF/10V,X7R 1uf/10V PWR fail No support Pin32 POWER_FAIL1
LRC LMDL914T1G 100V 200mA Pin100 POWER_FAIL0
SOD323

124

111

125
67

96
33
22
9
U27 C385
C0402

V18R

AVCC

VCC
VCC
VCC
VCC
VCC
VCC
3300pF/50V,X7R
EC_V3.3AL
63 SYS_I_Sense
AD0/GPI38 SYS_I_Sense 37 EC_V3.3AL

ADC
64 EC_Code0
R572 4.7K R0402 A20GATE 1 AD1/GPI39 65 EC_Code1
ns RCIN# 2 GA20/GPIO00 AD2/GPI3A 66 EC_Code2
20 KBRST#/GPIO01 AD3/GPI3B
20 EC_RUNTIME_SCI# SCI#/GPIO0E

MSIC
0 R573 EC_PCI_RST# EC_V3.3AL
37
7,19,31,34 BUF_PLT_RST# ECRST#
R0402 R602 47K R0402
C387 0.01uF/16V,X7R R738 R737 R739
C0402 10K 10K 10K
12 21 R0402 R0402 R0402
19 CLK_EC_PCI PCICLK PWM0/GPIO0F BTL_BEEP 29

PWM
3 23 ns
15 INT_SERIRQ SERIRQ PWM1/GPIO10 POWERLED# 35
4 25 EC_Code0
15,31 LPC_FRAME# LFRAME# PWM2/GPIO11 BT_OFF# 31
10 34 EC_Code1
15,31 LPC_AD0 LAD0 PWM3/GPIO19 EC_BKLT_PWM 24
KBCON1 8 EC_Code2
15,31 LPC_AD1 LAD1
FPC 7
15,31 LPC_AD2 LAD2
CNS26_1_R_2D5 5 D26

LPC
15,31 LPC_AD3 LAD3
EC_PCI_RST# 13 28 1 EC Code: R783 R784 R785
PCIRST#/GPIO05 FANFB0/GPIO14 FAN_BACK 30

FAN
26 EC_V3.3AL
R603 4.7K R0402 CLKREQ 38 29 SOD323 F41 000 10K 10K 10K
26 25 CLKRUN#/GPIO1D FANFB1/GPIO15 26 LRC LMDL914T1G 100V 200mA F42 001 R0402 R0402 R0402
25 FANPWM0/GPIO12 FAN1_V 30
24 SCANOUT15 27 R585 1K R586 TU142 010 ns ns
24 FANPWM1/GPIO13 Camera_ON# 24
23 SCANOUT10 R0402 100K TU151 011
23 22 SCANOUT11 SCANIN7 62 R0402 SU341 100
22 21 SCANOUT14 SCANIN6 61 KSI7/GPIO37 TU131 101
21 20 SCANOUT13 SCANIN5 60 KSI6/GPIO36 Vin>=1.5V turn on the cup FAN. CL42 110
20 19 SCANOUT12 SCANIN4 59 KSI5/GPIO35
19 18 SCANOUT3 SCANIN3 58 KSI4/GPIO34
C
18 17 SCANOUT6 SCANIN2 57 KSI3/GPIO33 83 C
17 KSI2/GPIO32 PSCLK1/GPIO4A/SCL2 TPCLK 28
16 SCANOUT8 SCANIN1 56 84
16 KSI1/GPIO31 PSDAT1/GPIO4B/SDA2 TPDAT 28
15 SCANOUT7 SCANIN0 55 85
15 14 KSI0/GPIO30/E51_TXD(ISP) PSCLK2/GPIO4C/SCL3 86 SM_CHG_SCL2 37
SCANOUT4
14 PSDAT2/GPIO4D/SDA3 SM_CHG_SDA2 37 EC_V3.3AL

PS2
13 SCANOUT2 82 87
13 KSO17/GPIO49 PSCLK3/GPIO4E PM_SLP_SUS# 17,39,45
12 SCANIN7 81 88 PM_STATE R311 0 R0402
12 17 AC_IN_PCH KSO16/GPIO48 PSDAT3/GPIO4F EXTSMI# 20
11 SCANOUT1 SCANOUT15 54 ns
11 10 SCANOUT5 SCANOUT14 53 KSO15/GPIO2F/E51_RXD(ISP) R305 10K R0402 SM_BAT_SDA2 R315 2.2K R0402
10 9 SCANIN4 SCANOUT13 52 KSO14/GPIO2E
9 8 51 KSO13/GPIO2D

KB3930
SCANIN5 SCANOUT12 SM_BAT_SCL2 R317 2.2K R0402
8 7 SCANOUT0 SCANOUT11 50 KSO12/GPIO2C

KB
28 7 6 SCANIN2 SCANOUT10 49 KSO11/GPIO2B AMP_SHDW R562 10K R0402 ns
27 28 6 5 SCANIN3 SCANOUT9 48 KSO10/GPIO2A
27 5 4 SCANOUT9 SCANOUT8 47 KSO9/GPIO29 EC_ME_LOCK# R719 10K R0402 ns
4 KSO8/GPIO28

SMBUS
3 SCANIN1 SCANOUT7 46 80
3 KSO7/GPIO27 SDA1/GPIO47 SML1DATA 16
2 SCANIN0 SCANOUT6 45 79 CHG_ON R300 10K
2 KSO6/GPIO26 SCL1//GPIO46 SML1CLK 16
1 SCANIN6 SCANOUT5 44 78 SM_BAT_SDA2
1 KSO5/GPIO25 SDA0/GPIO45 SM_BAT_SDA2 38
SCANOUT4 43 77 SM_BAT_SCL2
KSO4/GPIO24 SCL0/GPIO44 SM_BAT_SCL2 38
SCANOUT3 42
SCANOUT2 41 KSO3/GPIO23/TP_ISP
SCANOUT1 40 KSO2/GPIO22/TP_ANA_TEST
ns SCANOUT0 39 KSO1/GPIO21/TP_PLL 97
KSO0/GPIO20/TP_TEST GPXIOA00/SDICS# HW_RATIO_OFF# 31
+V3.3AL R570 1K 98 CHG_LED# 35
GPXIOA01/SDICLK 99
GPXIOA02/SDIMOSI BTL_LED# 35
EC_V3.3AL

GPXIOA
0 ns 6 R571 100 PM_PWRBTN# 17
17 PM_SUS_STAT# 14 GPIO04 GPXIOA03/FANFAB2 101 AMP_SHDW
17 PCH_DPWROK GPIO07/i_clk_8051 GPXIOA04/FANFB3 AMP_SHDW 29
15 102 R299 0 EC_ME_LOCK# EC_ME_LOCK# 15 CL341 VerC: Change PCB mark to VerC 2012/12/25
37 AC_IN GPIO08/i_clk_peri GPXIOA05
VerC: update GPIO07 to PCH_DPWROK output 16 103 R0402 CHG_ON CHG_ON 37
Swain 111206 17,43 PM_RSMRST# 17 GPIO0A/CIR_RX2/OWM GPXIOA06/VCOUT 104
LIDR# R578 1K R0402 PCH_PWROK 17