A1321 2 3 Datasheet PDF

A1321, A1322, and A1323
Ratiometric Linear Hall Effect Sensor ICs

for High-Temperature Operation
Discontinued Product
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: October 31, 2011
• for the A1321EUA-T and the A1321LUA-T use the A1324LUA-T

• for the A1321ELHLT-T and the A1321LLHLT-T use the A1324LLHLX-T
• for the A1322LUA-T use the A1325LUA-T
• for the A1322LLHLT-T use the A1325LLHLX-T
• for the A1323EUA-T and the A1323LUA-T use the A1326LUA-T
• for the A1323LLHLT-T use the A1326LLHLX-T
NOTE: For detailed information on purchasing options, contact your

local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A1321, A1322, and A1323
Ratiometric Linear Hall Effect Sensor ICs
for High-Temperature Operation
Features and Benefits Description
▪ Temperature-stable quiescent output voltage The A132X family of linear Hall-effect sensor ICs are optimized,
▪ Precise recoverability after temperature cycling sensitive, and temperature-stable. These ratiometric Hall-effect
▪ Output voltage proportional to magnetic flux density sensor ICs provide a voltage output that is proportional to the
▪ Ratiometric rail-to-rail output applied magnetic field. The A132X family has a quiescent
▪ Improved sensitivity output voltage that is 50% of the supply voltage and output
▪ 4.5 to 5.5 V operation sensitivity options of 2.5 mV/G, 3.125 mV/G, and 5m V/G.
▪ Immunity to mechanical stress The features of this family of devices are ideal for use in the
▪ Solid-state reliability harsh environments found in automotive and industrial linear
▪ Robust EMC protection and rotary position sensing systems.
Each device has a BiCMOS monolithic circuit which integrates
a Hall element, improved temperature-compensating circuitry
to reduce the intrinsic sensitivity drift of the Hall element,
Packages: 3 pin SOT23W (suffix LH), and a small-signal high-gain amplifier, and a rail-to-rail low-
3 pin SIP (suffix UA) impedance output stage.
A proprietary dynamic offset cancellation technique, with
an internal high-frequency clock, reduces the residual offset
voltage normally caused by device overmolding, temperature
dependencies, and thermal stress. The high frequency clock
allows for a greater sampling rate, which results in higher
accuracy and faster signal processing capability. This technique
produces devices that have an extremely stable quiescent output
voltage, are immune to mechanical stress, and have precise
Continued on the next page…
Not to scale
Functional Block Diagram

V+
VCC
Dynamic Offset
Cancellation
VOUT
Filter
Amp Out
Gain Offset
0.1 μF
Trim
Control
GND
A1321-DS, Rev. 23
A1321, A1322, Ratiometric Linear Hall Effect Sensor ICs
and A1323 for High-Temperature Operation
Description (continued)
recoverability after temperature cycling. Having the Hall element The A132X family is provided in a 3-pin single in-line package
and an amplifier on a single chip minimizes many problems normally (UA) and a 3-pin surface mount package (LH). Each package is
associated with low-level analog signals. available in a lead (Pb) free version (suffix, –T) , with a 100% matte
tin plated leadframe.
Output precision is obtained by internal gain and offset trim adjustments
made at end-of-line during the manufacturing process.
Selection Guide
Ambient, TA Sensitivity,
Part Number Packing1 Mounting
(ºC) Typ. (mV/G)
A1321ELHLT-T2 7-in. reel, 3000 pieces/reel Surface Mount
–40 to 85
A1321EUA-T3 Bulk, 500 pieces/bag SIP through hole
5.000
A1321LLHLT-T2 7-in. reel, 3000 pieces/reel Surface Mount
–40 to 150
A1321LUA-T3 Bulk, 500 pieces/bag SIP through hole
A1322LLHLT-T2 7-in. reel, 3000 pieces/reel Surface Mount
–40 to 150 3.125
A1323EUA-T3 Bulk, 500 pieces/bag SIP through hole –40 to 85
A1323LLHLT-T2 7-in. reel, 3000 pieces/reel Surface Mount 2.500
–40 to 150
1Contact Allegro for additional packing options.
2This variant is in production, however, it has been deemed Pre-End of Life. The product is approaching end of life. Within a minimum of 6 months,
the device will enter its final, Last Time Buy, order phase. Status change: January 31, 2011. Suggested replacements: for the A1321ELHLT-T and
the A1321LLHLT-T use the A1324LLHLX-T, for the A1322LLHLT-T use the A1325LLHLX-T, and for the A1323LLHLT-T use the A1326LLHLX-T.
3Variant is in production but has been determined to be NOT FOR NEW DESIGN. This classification indicates that sale of the variant is currently
restricted to existing customer applications. The variant should not be purchased for new design applications because obsolescence in the near
future is probable. Samples are no longer available. Status change: January 31, 2011.
Absolute Maximum Ratings

Characteristic Symbol Notes Rating Units
*Additional current draw may be observed at
voltages above the minimum supply Zener
Supply Voltage VCC 8 V
clamp voltage, VZ(min), due to the Zener diode
turning on.
Output Voltage VOUT 8 V
Reverse Supply Voltage VRCC –0.1 V
Reverse Output Voltage VROUT –0.1 V
Output Sink Current IOUT 10 mA
Operating Ambient Temperature TA Range L –40 to 150 ºC
Maximum Junction Temperature TJ(max) 165 ºC
Storage Temperature Tstg –65 to 170 ºC
Allegro MicroSystems, Inc. 2

115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Pin-out Drawings
Package LH Package UA
1 2 1 2 3
Terminal List
Number
Symbol Description
Package LH Package UA
VCC 1 1 Connects power supply to chip
VOUT 2 3 Output from circuit
GND 3 2 Ground

DEVICE CHARACTERISTICS1 over operating temperature (TA) range, unless otherwise noted
Characteristic Symbol Test Conditions Min. Typ.2 Max. Units
Electrical Characteristics; VCC = 5 V, unless otherwise noted
Supply Voltage Vcc(op) Operating; Tj < 165°C 4.5 5.0 5.5 V
Supply Current Icc B = 0, Iout = 0 – 5.6 8 mA
Quiescent Voltage Vout(q) B = 0, TA = 25ºC, Iout = 1 mA 2.425 2.5 2.575 V
Vout(H) B = +X, Iout = –1 mA – 4.7 – V
Output Voltage3
Vout(L) B = –X, Iout = 1 mA – 0.2 – V
Output Source Current Limit 3 Iout(LM) B = –X, Vout → 0 –1.0 –1.5 – mA
Supply Zener Clamp Voltage VZ Icc = 11 mA = Icc(max) + 3 6 8.3 – V
Output Bandwidth BW – 30 – kHz
Clock Frequency fC – 150 – kHz
Output Characteristics; over VCC range, unless otherwise noted
A1321; Cbypass = 0.1 μF, no load – – 40 mV
Noise, Peak-to-Peak4 VN A1322; Cbypass = 0.1 μF, no load – – 25 mV
A1323; Cbypass = 0.1 μF, no load – – 20 mV
Output Resistance Rout Iout ≤ ±1 mA – 1.5 3 Ω
Output Load Resistance RL Iout ≤ ±1 mA, VOUT to GND 4.7 – – kΩ
Output Load Capacitance CL VOUT to GND – – 10 nF
1 Negative current is defined as conventional current coming out of (sourced from) the specified device terminal.
2 Typical data is at TA = 25°C. They are for initial design estimations only, and assume optimum manufacturing and application
conditions. Performance may vary for individual units, within the specified maximum and minimum limits.
3 In these tests, the vector X is intended to represent positive and negative fields sufficient to swing the output driver between fully OFF
and saturated (ON), respectively. It is NOT intended to indicate a range of linear operation.
4 Noise specification includes both digital and analog noise.

MAGNETIC CHARACTERISTICS1,2 over operating temperature range, TA; VCC = 5 V, Iout = –1 mA; unless otherwise noted
Characteristics Symbol Test Condition Min Typ3 Max Units4
A1321; TA = 25ºC 4.750 5.000 5.250 mV/G
Sensitivity 5 Sens A1322; TA = 25ºC 2.969 3.125 3.281 mV/G
A1323; TA = 25ºC 2.375 2.500 2.625 mV/G
Delta Vout(q) as a func-
Vout(q)(ΔT) Defined in terms of magnetic flux density, B – – ±10 G
tion of temperature
Ratiometry, Vout(q) Vout(q)(ΔV) – – ±1.5 %
Ratiometry, Sens ΔSens(ΔV) – – ±1.5 %
Positive Linearity Lin+ – – ±1.5 %
Negative Linearity Lin– – – ±1.5 %
Symmetry Sym – – ±1.5 %
UA Package
Delta Sens at TA = max5 ΔSens(TAmax) From hot to room temperature –2.5 – 7.5 %
Delta Sens at TA = min5 ΔSens(TAmin) From cold to room temperature –6 – 4 %
Sensitivity Drift6 SensDrift TA = 25°C; after temperature cycling and over time – ±2 – %
LH Package
Delta Sens at TA = max5 ΔSens(TAmax) From hot to room temperature –5 – 5 %
Delta Sens at TA = min5 ΔSens(TAmin) From cold to room temperature –3.5 – 8.5 %
Sensitivity Drift6 SensDrift TA = 25°C; after temperature cycling and over time – ±2 – %
1 Additional information on characteristics is provided in the section Characteristics Definitions, on the next page.
2 Negative current is defined as conventional current coming out of (sourced from) the specified device terminal.
3 Typical data is at T = 25°C, except for ΔSens, and at x.x Sens. Typical data are for initial design estimations only, and assume optimum
A
manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits.
In addition, the typical values vary with gain.
4 10 G = 1 millitesla.
5 After 150ºC pre-bake and factory programming.
6 Sensitivity drift is the amount of recovery with time.

Characteristic Definitions
Quiescent Voltage Output. In the quiescent state (no Ratiometric. The A132X family features a ratiometric output.
magnetic field), the output equals one half of the supply voltage The quiescent voltage output and sensitivity are proportional to
over the operating voltage range and the operating temperature the supply voltage (ratiometric).
range. Due to internal component tolerances and thermal con-
The percent ratiometric change in the quiescent voltage output is
siderations, there is a tolerance on the quiescent voltage output
defined as:
both as a function of supply voltage and as a function of ambient
Vout(q)(VCC) Vout(q)(5V)
temperature. For purposes of specification, the quiescent voltage ΔVout(q)(ΔV) = × 100% (4)
output as a function of temperature is defined in terms of mag- VCC 5 V
netic flux density, B, as:
and the percent ratiometric change in sensitivity is
Vout(q)(ΤΑ) – Vout(q)(25ºC) defined as:
ΔVout(q)(ΔΤ) = (1)
Sens(25ºC) Sens(VCC) Sens(5V)
ΔSens(ΔV) = × 100% (5)
This calculation yields the device’s equivalent accuracy, VCC 5 V
over the operating temperature range, in gauss (G).
Linearity and Symmetry. The on-chip output stage
Sensitivity. The presence of a south-pole magnetic field per- is designed to provide a linear output with a supply voltage of
pendicular to the package face (the branded surface) increases 5 V. Although application of very high magnetic fields will not
the output voltage from its quiescent value toward the supply damage these devices, it will force the output into a non-linear
voltage rail by an amount proportional to the magnetic field region. Linearity in percent is measured and defined as:
applied. Conversely, the application of a north pole will decrease
the output voltage from its quiescent value. This proportionality Vout(+B) – Vout(q) (6)
is specified as the sensitivity of the device and is defined as: Lin+ = × 100%
2(Vout(+B / 2) – Vout(q) )
Vout(–B) – Vout(+B) (2)
Sens = Vout(–B) – Vout(q) (7)
2B
Lin– = × 100%
The stability of sensitivity as a function of temperature is 2(Vout(–B / 2) – Vout(q) )
defined as: and output symmetry as:
Sens(ΤΑ) – Sens(25ºC)
ΔSens(ΔΤ) = × 100% (3) Vout(+B) –Vout(q)
Sens(25ºC) (8)
Sym = × 100%
Vout(q) – Vout(–B)

Typical Characteristics
(30 pieces, 3 fabrication lots)
Average Supply Current (ICC) vs Temperature

Vcc = 5 V
8
7.5
7
6.5
6
5.5
5
ICC (mA)
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
115
125
150
-40
-20
25
85
0
TA (°C)
Average Positive Linearity (Lin+) vs Temperature Average Negative Linearity (Lin–) vs Temperature
Vcc = 5 V Vcc = 5 V
105 105
104 104
103 103
102 102
101
Lin+ (%)
101
Lin– (%)
100
100
99
99
98
98
97
97
96
96
95
115
125
150
-40
-20
25
85
0
95
-40
-20
25
85
115
125
150
TA (°C)
TA (°C)
Average Ratiometry, VOUT(q)(ΔV) vs Temperature Average Ratiometry, ΔSens(ΔV), vs Temperature

101 101
100.8 100.8 4.5 to 5.0V

4.5 to 5.0 V 5.5 to 5.0V
100.6 100.6
5.5 to 5.0 V
100.4 100.4
Ratiometry (%)
Ratiometry (%)
100.2 100.2
100 100
99.8 99.8
99.6 99.6
99.4 99.4
99.2 99.2
99 99
115
125
150
-40
-20
25
85
115
125
150
0
-40
-20
25
85
0
TA (°C) TA (°C)
Continued on the next page...

Typical Characteristics, continued
(30 pieces, 3 fabrication lots)
Average Absolute Quiescent Output Voltage, Vout(q), vs Temperature Quiescent Output Voltage, Vout(q), vs Vcc
Vcc = 5 V TA = 25°C
2.575
3
2.55 2.9
2.8
2.525 2.7
Vout(q) (V)
Vout(q) (V)
2.6 1321
2.5
2.5 1322
1323
2.475 2.4
2.3
2.45 2.2
2.1
2.425
2
-40
-20
25
85
115
125
150
0
4.5 5 5.5
TA (°C)
Vcc (V)
Average Absolute Sensitivity, Sens, vs Temperature Average Sensitivity, Sens, vs Vcc

Vcc = 5 V TA = 25°C
6
6
5.5 5.5
5 5
1321
4.5 1322
Sens (mV/G)
4.5
A1322
4 1323
Sens (mV/G)
A1321
4
A1323
3.5
3.5 3
3 2.5
2
2.5
1.5
2 1
-40
-20
25
85
115
125
150
0
4.5 5 5.5
TA (°C) Vcc (V)
Average Delta Quiescent Output Voltage, Vout(q)(ΔT), vs Temperature Average Delta Sensitivity, ΔSens, vs Temperature
Δ in readings at each temperature are relative to 25°C
Δ in readings at each temperature are relative to 25°C
Vcc = 5 V
10 Vcc = 5 V
10
8
8
6
6
Vout(q)(ΔT) (G)
4 4
2
ΔSens (%)
2
0 0
-2 -2
-4 -4
-6 -6
-8 -8
-10 -10
-40
-20
25
85
115
125
150
0
-40
-20
25
85
115
125
150
0
TA (°C) TA (°C)

THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Value Units

Package LH, 1-layer PCB with copper limited to solder pads 228 ºC/W
Package LH, 2-layer PCB with 0.463 in.2 of copper area each side
Package Thermal Resistance RθJA 110 ºC/W
connected by thermal vias
Package UA, 1-layer PCB with copper limited to solder pads 165 ºC/W
*Additional thermal information available on Allegro website.
Power Derating Curve
VCC(max)
Maximum Allowable VCC (V)
5 1-layer PCB, Package LH

(RQJA = 228 ºC/W)
VCC(min)
1-layer PCB, Package UA
4
(RQJA = 165 ºC/W)
2-layer PCB, Package LH
3
(RQJA = 110 ºC/W)
0
20 40 60 80 100 120 140 160 180
Temperature (ºC)
Power Dissipation versus Ambient Temperature
1900
1800
1700
1600
1500
1400
1300
Power Dissipation, PD (mW)
1200 2-
l
1100 (R aye
QJ rP
A = C
1000 11 B, P
1-la 0 º ac
900 C/ ka
(R yer PC W
) ge L
800 QJA = B, P H
165 ack
700 ºC/ a
W) ge U
600 A
500 1-lay
400 er P
(R CB,
300 QJA =
228 Packag
ºC/W e LH
200 )
100
0
20 40 60 80 100 120 140 160 180
Temperature (°C)

Power Derating
The device must be operated below the maximum junction Example: Reliability for VCC at TA = 150°C, package UA, using
temperature of the device, TJ(max). Under certain combinations of minimum-K PCB.
peak conditions, reliable operation may require derating sup- Observe the worst-case ratings for the device, specifically:
plied power or improving the heat dissipation properties of the RJA = 165°C/W, TJ(max) = 165°C, VCC(max) = 5.5 V, and
application. This section presents a procedure for correlating ICC(max) = 8 mA.
factors affecting operating TJ. (Thermal data is also available on
the Allegro MicroSystems Web site.) Calculate the maximum allowable power level, PD(max). First,
invert equation 3:
The Package Thermal Resistance, RJA, is a figure of merit sum-
marizing the ability of the application and the device to dissipate Tmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C
heat from the junction (die), through all paths to the ambient air. This provides the allowable increase to TJ resulting from internal
Its primary component is the Effective Thermal Conductivity, power dissipation. Then, invert equation 2:
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, RJC, is PD(max) = Tmax ÷ RJA = 15°C ÷ 165 °C/W = 91 mW
relatively small component of RJA. Ambient air temperature,
TA, and air motion are significant external factors, damped by Finally, invert equation 1 with respect to voltage:
overmolding.
VCC(est) = PD(max) ÷ ICC(max) = 91 mW ÷ 8 mA = 11.4 V
The effect of varying power levels (Power Dissipation, PD), can
The result indicates that, at TA, the application and device can
be estimated. The following formulas represent the fundamental
dissipate adequate amounts of heat at voltages ≤VCC(est).
relationships used to estimate TJ, at PD.
Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reli-
PD = VIN × IIN (1) able operation between VCC(est) and VCC(max) requires enhanced
RJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and
 T = PD × RJA (2) VCC(max) is reliable under these conditions.
TJ = TA + ΔT (3)
For example, given common conditions such as: TA= 25°C,

VCC = 12 V, ICC = 4 mA, and RJA = 140 °C/W, then:
PD = VCC × ICC = 12 V × 4 mA = 48 mW
 T = PD × RJA = 48 mW × 140 °C/W = 7°C
TJ = TA + T = 25°C + 7°C = 32°C
A worst-case estimate, PD(max), represents the maximum allow-

able power level (VCC(max), ICC(max)), without exceeding TJ(max),
at a selected RJA and TA.

Package LH, 3-Pin (SOT-23W)
+0.12
2.98 –0.08
1.49 D
4°±4°
3 A
+0.020
0.180–0.053
0.96 D
+0.10 +0.19 2.40

2.90 –0.20 1.91 –0.06
0.70
D
0.25 MIN
1.00
1 2
0.55 REF 0.25 BSC 0.95

Seating Plane
Gauge Plane B PCB Layout Reference View
8X 10° REF Branded Face
1.00 ±0.13
NNT
+0.10 1
0.05 –0.05
0.95 BSC C Standard Branding Reference View
0.40 ±0.10
N = Last two digits of device part number
T = Temperature code
For Reference Only; not for tooling use (reference dwg. 802840)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Active Area Depth, 0.28 mm REF
B Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
C Branding scale and appearance at supplier discretion
D Hall element, not to scale

Package UA, 3-Pin SIP
+0.08
4.09 –0.05
45°
B
C
E
2.04
1.52 ±0.05
1.44 E
Mold Ejector
+0.08 Pin Indent NNT
3.02 –0.05
E
Branded 45°
Face 1
2.16 D Standard Branding Reference View
0.79 REF
MAX
= Supplier emblem
N = Last two digits of device part number
A T = Temperature code
0.51
REF
1 2 3
For Reference Only; not for tooling use (reference DWG-9049)

Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
+0.03 Exact case and lead configuration at supplier discretion within limits shown
0.41 –0.06
15.75 ±0.51
A Dambar removal protrusion (6X)

B Gate burr area
C Active Area Depth, 0.50 mm REF
D Branding scale and appearance at supplier discretion
E Hall element, not to scale
+0.05 1.27 NOM

0.43 –0.07
Copyright ©2004-2010, Allegro MicroSystems, Inc.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:

www.allegromicro.com

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A1321, A1322, and A1323

Ratiometric Linear Hall Effect Sensor ICs

Date of status change: October 31, 2011

• for the A1321EUA-T and the A1321LUA-T use the A1324LUA-T

NOTE: For detailed information on purchasing options, contact your

Continued on the next page…

Functional Block Diagram

Absolute Maximum Ratings

Allegro MicroSystems, Inc. 2

Allegro MicroSystems, Inc. 3

Allegro MicroSystems, Inc. 4

Allegro MicroSystems, Inc. 5

Allegro MicroSystems, Inc. 6

Average Supply Current (ICC) vs Temperature

Average Ratiometry, VOUT(q)(ΔV) vs Temperature Average Ratiometry, ΔSens(ΔV), vs Temperature

100.8 100.8 4.5 to 5.0V

Continued on the next page...

Allegro MicroSystems, Inc. 7

Average Absolute Sensitivity, Sens, vs Temperature Average Sensitivity, Sens, vs Vcc

Allegro MicroSystems, Inc. 8

Characteristic Symbol Test Conditions* Value Units

Power Derating Curve

5 1-layer PCB, Package LH

Power Dissipation versus Ambient Temperature

Allegro MicroSystems, Inc. 9

For example, given common conditions such as: TA= 25°C,

 T = PD × RJA = 48 mW × 140 °C/W = 7°C

TJ = TA + T = 25°C + 7°C = 32°C

A worst-case estimate, PD(max), represents the maximum allow-

Allegro MicroSystems, Inc. 10

Package LH, 3-Pin (SOT-23W)

+0.10 +0.19 2.40

0.55 REF 0.25 BSC 0.95

8X 10° REF Branded Face

D Hall element, not to scale

Allegro MicroSystems, Inc. 11

Package UA, 3-Pin SIP

For Reference Only; not for tooling use (reference DWG-9049)

A Dambar removal protrusion (6X)

+0.05 1.27 NOM

Copyright ©2004-2010, Allegro MicroSystems, Inc.

For the latest version of this document, visit our website:

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