CHAPTER 1

INTRODUCTION TO VHDL

In the mid-1980’s the U.S. Department of Defense and the IEEE sponsored the
development of the hardware description language with the goal to develop very high-
speed integrated circuit, which brought result in the form of VHDL. It has become now
one of industry’s standard languages used to describe digital systems. The other widely
used hardware description language is Verilog. Both are powerful languages that allow you
to describe and simulate complex digital systems. A third HDL language is ABEL
(Advanced Boolean Equation Language) which was specifically designed for
Programmable Logic Devices (PLD). ABEL is less powerful than the other two languages
and is less popular in industry.

What’s VHDL

VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description
Language. It’s a hardware description language that is specifically designed to describe the
organization & function of digital hardware system.

1.2 Capabilities Of VHDL

 Implementation of any circuit idea like complete robot design.

 Microprocessor of your own configuration.
 Direct hardware interaction.

1.3 Specific Features Of VHDL

 Portability
 Each level of abstraction.
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 Not technology specific.
 IEEE & ANSI standardized.
 Large projects can be easily designed.

1.4 VHDL Design Hierarchy

Entity Declaration

The entity declaration defines the NAME of the entity and lists the input and output ports.
The general form is as follows,

entity NAME_OF_ENTITY is [ generic generic_declarations);]

port (signal_names: mode type;
signal_names: mode type;
signal_names: mode type);
end [NAME_OF_ENTITY] ;

An entity always starts with the keyword entity, followed by its name and the keyword
is. Next are the port declarations using the keyword port. An entity declaration always
ends with the keyword end, optionally [] followed by the name of the entity.

Architecture Body

The architecture body specifies how the circuit operates and how it is implemented. As
discussed earlier, an entity or circuit can be specified in a variety of ways, such as
behavioral, structural (interconnected components), or a combination of the above.
The architecture body looks as follows,

architecture architecture_name of NAME_OF_ENTITY is

-- Declarations
-- components declarations
2
 -- signal declarations
-- constant declarations
-- function declarations
-- procedure declarations
-- type declarations
begin
Statements
end architecture_name;

1.4.3 Constant

A constant can have a single value of a given type and cannot be changed during the
simulation. A constant is declared as follows,
constant list_of_name_of_constant: type [ := initial value] ;
where the initial value is optional. Constants can be declared at the start of an architecture
and can then be used anywhere within the architecture. Constants declared within a
process can only be used inside that specific process.
constant RISE_FALL_TME: time := 2 ns;
constant DELAY1: time := 4 ns;
constant RISE_TIME, FALL_TIME: time:= 1 ns;
constant DATA_BUS: integer:= 16;

1.4.4 Variable

A variable can have a single value, as with a constant, but a variable can be updated using
a variable assignment statement. The variable is updated without any delay as soon as the
statement is executed. Variables must be declared inside a process. The variable
declaration is as follows:
variable list_of_variable_names: type [ := initial value] ;
A few examples follow:

variable CNTR_BIT: bit :=0;

variable VAR1: boolean :=FALSE;
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variable SUM: integer range 0 to 256 :=16;
variable STS_BIT: bit_vector (7 downto 0);
The variable SUM, in the example above, is an integer that has a range from 0 to 256 with
initial value of 16 at the start of the simulation. The fourth example defines a bit vector or
8 elements: STS_BIT(7), STS_BIT(6),… STS_BIT(0).
A variable can be updated using a variable assignment statement such as
Variable_name := expression;

1.4.5 Signals

Signals connect design entities together and communicate changes in values between
processes.They can be interpreted as wires or busses in an actual circuit.Signals
can be declared in packages , entities , architectures and blocks. The syntax is :

Signal signal_name {signal_name} :type[:=value];

1.4.6 Package Declaration

package name_of_package is
package declarations
end package name_of_package;
-- Package body declarations
package body name_of_package is
package body declarations
end package body name_of_package;

For instance, the basic functions of the AND2, OR2, NAND2, NOR2, XOR2, etc.
components need to be defined before one can use them. This can be done in a package,
e.g. basic_func for each of these components, as follows:

-- Package declaration

library ieee;
use ieee.std_logic_1164.all;

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package basic_func is
-- AND2 declaration
component AND2
generic (DELAY: time :=5ns);
port (in1, in2: in std_logic; out1: out std_logic);
end component;
-- OR2 declaration
component OR2
generic (DELAY: time :=5ns);
port (in1, in2: in std_logic; out1: out std_logic);
end component;
end package basic_func;

1.4.7 Package Body Declaration

library ieee;
use ieee.std_logic_1164.all;
package body basic_func is
-- 2 input AND gate
entity AND2 is
generic (DELAY: time);
port (in1, in2: in std_logic; out1: out std_logic);
end AND2;
architecture model_conc of AND2 is
begin
out1 <= in1 and in2 after DELAY;
end model_conc;
-- 2 input OR gate
entity OR2 is
generic (DELAY: time);
port (in1, in2: in std_logic; out1: out std_logic);
end OR2;
architecture model_conc2 of AND2 is

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 begin
out1 <= in1 or in2 after DELAY;
end model_conc2;
end package body basic_func;

1.5 Design Description Methods

A digital system can be represented at different levels of abstraction [1]. This keeps the
description and design of complex systems manageable. Figure 1 shows different levels of
abstraction.

Figure 1.1 Levels of abstraction: Behavioral, Structural and Physical

The highest level of abstraction is the behavioral level that describes a system in terms of
what it does (or how it behaves) rather than in terms of its components and interconnection
between them. A behavioral description specifies the relationship between the input and
output signals. This could be a Boolean expression or a more abstract description such
VHDL allows one to describe a digital system at the structural or the behavioral level. The
behavioral level can be further divided into two kinds of styles: Data flow and
Algorithmic. The dataflow representation describes how data moves through the system.
This is typically done in terms of data flow between registers (Register Transfer level). The
data flow model makes use of concurrent statements that are executed in parallel as soon as
data arrives at the input. On the other hand, sequential statements are executed in the
sequence that they are specified. VHDL allows both concurrent and sequential signal

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assignments that will determine the manner in which they are executed. Examples of both
representations will be given later. as the Register Transfer or Algorithmic level. As an
example, let us consider a simple circuit that warns car passengers when the door is open
or the seatbelt is not used whenever the car key is inserted in the ignition lock At the
behavioral level this could be expressed as,
Warning = Ignition_on AND ( Door_open OR Seatbelt_off)
The structural level, on the other hand, describes a system as a collection of gates and
components that are interconnected to perform a desired function. A structural description
could be compared to a schematic of interconnected logic gates. It is a representation that
is usually closer to the physical realization of a system. For the example above, the
structural representation is shown in Figure 2 below.

Figure 1.2: Structural representation of a “buzzer” circuit.

1.6 Sequential Statements

1.6.1 If Statements

The if statement executes a sequence of statements whose sequence depends on one or

more conditions. The syntax is as follows:

if condition then
sequential statements
[elsif condition then
sequential statements ]

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 [else
sequential statements ]
end if;

1.6.2 Case statements

The case statement executes one of several sequences of statements, based on the value of
a single expression. The syntax is as follows,
case expression is
when choices =>
sequential statements
when choices =>
sequential statements
-- branches are allowed
[ when others => sequential statements ]
end case;

1.6.3 Loop statements

A loop statement is used to repeatedly execute a sequence of sequential statements. The

syntax for a loop is as follows:
[ loop_label :]iteration_scheme loop
sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop [loop_label];
Labels are optional but are useful when writing nested loops. The next and exit statement
are sequential statements that can only be used inside a loop.
 The next statement terminates the rest of the current loop iteration and execution will
proceed to the next loop iteration.
 The exit statement skips the rest of the statements, terminating the loop entirely, and
continues with the next statement after the exited loop.
 There are three types of iteration schemes:

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 basic loop
 while … loop
 for … loop

1.6.4 Basic Loop statement

This loop has no iteration scheme. It will be executed continuously until it encounters an
exit or next statement.

[ loop_label :] loop
sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop [ loop_label];

The basic loop (as well as the while-loop) must have at least one wait statement. As an
example, lets consider a 5-bit counter that counts from 0 to 31. When it reaches 31, it will
start over from 0. A wait statement has been included so that the loop will execute every
time the clock changes from ‘0’ to ‘1’.

1.6.5 While-Loop statement

The while … loop evaluates a Boolean iteration condition. When the condition is TRUE,
the loop repeats, otherwise the loop is skipped and the execution will halt. The syntax for
the while…loop is as follows,

[ loop_label :] while condition loop

sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop[ loop_label ];

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1.6.6 For-Loop statement

The for-loop uses an integer iteration scheme that determines the number of iterations. The
syntax is as follows,

[ loop_label :] for identifier in range loop

sequential statements
[next [label] [when condition];
[exit [label] [when condition];
end loop[ loop_label ];

1.7 Dataflow Modeling

1.7.1 Concurrent Statements

Behavioral modeling can be done with sequential statements using the process construct or
with concurrent statements. The first method was described in the previous section and is
useful to describe complex digital systems. In this section, we will use concurrent
statements to describe behavior. This method is usually called dataflow modeling. The
dataflow modeling describes a circuit in terms of its function and the flow of data through
the circuit. This is different from the structural modeling that describes a circuit in terms of
the interconnection of components. Concurrent signal assignments are event triggered and
executed as soon as an event on one of the signals occurs. In the remainder of the section
we will describe several concurrent constructs for use in dataflow modeling.

1.7.2 Simple Concurrent signal assignments.

We have discussed several concurrent examples earlier in the tutorial. In this section we
will review the different types of concurrent signal assignments.
A simple concurrent signal assignment is given in the following examples,
Sum <= (A xor B) xor Cin;

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 Carry <= (A and B);
Z <= (not X) or Y after 2 ns;
The syntax is as follows:
Target_signal <= expression;
in which the value of the expression transferred to the target_signal. As soon as an event
occurs on one of the signals, the expression will be evaluated. The type of the target_signal
has to be the same as the type of the value of the expression.

1.7.3 Conditional Signal assignments

The syntax for the conditional signal assignment is as follows:

Target_signal <= expression when Boolean_condition else
expression when Boolean_condition else
expression;

The target signal will receive the value of the first expression whose Boolean condition is
TRUE. If no condition is found to be TRUE, the target signal will receive the value of the
final expression. If more than one condition is true, the value of the first condition that is
TRUE will be assigned.

1.7.4 Selected Signal assignments

The selected signal assignment is similar to the conditional one described above. The
syntax is as follows,

with choice_expression select

target_name <= expression when choices,
target_name <= expression when choices,
target_name <= expression when choices;

1.8 Structural Modeling

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Structural modeling was described briefly in the section Structural Modeling in “Basic
Structure of a VHDL file”. A structural way of modeling describes a circuit in terms of
components and its interconnection. Each component is supposed to be defined earlier (e.g.
in package) and can be described as structural, a behavioral or dataflow model. At the
lowest hierarchy each component is described as a behavioral model, using the basic logic
operators defined in VHDL. In general structural modeling is very good to describe
complex digital systems, though a set of components in a hierarchical fashion.A structural
description can best be compared to a schematic block diagram that can be described by
the components and the interconnections. VHDL provides a formal way to do this by

 Declare a list of components being used

 Declare signals which define the nets that interconnect components
 Label multiple instances of the same component so that each instance is uniquely
defined.

The components and signals are declared within the architecture body,
architecture architecture_name of NAME_OF_ENTITY is
-- Declarations
component declarations
signal declarations
begin
-- Statements
component instantiation and connections
end architecture_name;

1.8.1 Component declaration

Before components can be instantiated they need to be declared in the architecture

declaration section or in the package declaration. The component declaration consists of
the component name and the interface (ports). The syntax is as follows:

component component_name [is]

[port (port_signal_names: mode type;
port_signal_names: mode type;

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 :
port_signal_names: mode type);]
end component [component_name];
The component name refers to either the name of an entity defined in a library or an entity
explicitly defined in the VHDL file (see example of the four bit adder).

The list of interface ports gives the name, mode and type of each port, similarly as is done
in the entity declaration.

A few examples of component declaration follow:

component OR2
port (in1, in2: in std_logic;
out1: out std_logic);
end component;
component PROC
port (CLK, RST, RW, STP: in std_logic;
ADDRBUS: out std_logic_vector (31 downto 0);
DATA: inout integer range 0 to 1024);
component FULLADDER
port(a, b, c: in std_logic;
sum, carry: out std_logic);
end component;
As mentioned earlier, the component declaration has to be done either in the architecture
body or in the package declaration. If the component is declared in a package, one does not
have to declare it again in the architecture body as long as one uses the library and use
clause.

1.9 Data Types

Each data object has a type associated with it. The type defines the set of values that the
object can have and the set of operations that are allowed on it. The notion of type is key to
VHDL since it is a strongly typed language that requires each object to be of a certain type.
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In general one is not allowed to assign a value of one type to an object of another data type
(e.g. assigning an integer to a bit type is not allowed). There are four classes of data types:
scalar, composite, access and file types. The scalar types represent a single value and are
ordered so that relational operations can be performed on them. The scalar type includes
integer, real, and enumerated types of Boolean and Character. Examples of these will be
given further on.

1.9.1 User-defined Types

One can introduce new types by using the type declaration, which names the type and
specifies its value range. The syntax is
type identifier is type_definition;
Here are a few examples of type definitions,

1.9.2 Integer types

type small_int is range 0 to 1024;

type my_word_length is range 31 downto 0;
subtype data_word is my_word_length range 7 downto 0;

A subtype is a subset of a previously defined type. The last example above illustrates the
use of subtypes. It defines a type called data_word that is a sybtype of my_word_length of
which the range is restricted from 7 to 0. Another example of a subtype is,
subtype int_small is integer range -1024 to +1024;

1.9.3 Floating-point types

type cmos_level is range 0.0 to 3.3;

type pmos_level is range -5.0 to 0.0;
type probability is range 0.0 to 1.0;
subtype cmos_low_V is cmos_level range 0.0 to +1.8;

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Note that floating point data types are not supported by the Xilinx Foundation synthesis
program.

1.9.4 Physical types

The physical type definition includes a units identifier as follows,

type conductance is range 0 to 2E-9
units
mho;
mmho = 1E-3 mho;
umho = 1E-6 mho;
nmho = 1E-9 mho;
pmho = 1E-12 mho;
end units conductance;

1.9.5 Enumerated Types

An enumerated type consists of lists of character literals or identifiers. The enumerated

type can be very handy when writing models at an abstract level. The syntax for an
enumerated type is,

type type_name is (identifier list or character literal);

1.9.6 Type Conversions

Since VHDL is a strongly typed language one cannot assign a value of one data type to a
signal of a different data type. In general, it is preferred to the same data types for the
signals in a design, such as std_logic (instead of a mix of std_logic and bit types).
Sometimes one cannot avoid using different types. To allow assigning data between
objects of different types, one needs to convert one type to the other. Fortunately there are
functions available in several packages in the ieee library, such as the std_logic_1164 and

15
the std_logic_arith packages. As an example, the std_logic_1164 package allows the
following conversions:

TABLE 1.1 Conversions supported by std_logic_1164 package

Conversions supported by std_logic_1164 package

Conversion
std_ulogic to bit
std_logic_vector to bit_vector
std_ulogic_vector to bit_vector
bit to std_ulogic
bit_vector to std_logic_vector
bit_vector to std_ulogic_vector
std_ulogic to std_logic_vector
std_logic to std_ulogic_vector
Function
to_bit(expression)
to_bitvector(expression)
to_bitvector(expression)
To_StdULogic(expression)
To_StdLogicVector(expression)
To_StdUlogicVector(expression)
To_StdLogicVector(expression)
To_StdUlogicVector(expression)

1.10 Atributes

VHDL supports 5 types of attributes. Predefined attributes are always applied to a prefix
such as a signal name, variable name or a type. Attributes are used to return various types
of information about a signal, variable or type. Attributes consist of a quote mark (‘)
followed by the name of the attribute.

1.10.1 Signal attributes

The following table gives several signal attributes.

TABLE 1.2

Attribute Function
signal_name’event returns the Boolean value True if an event on the
signal occurred, otherwise gives a False
signal_name’active returns the Boolean value True there has been a
transaction (assignment) on the signal, otherwise
gives a False
signal_name’transaction returns a signal of the type “bit” that toggles (0 to 1
or 1 to 0) every time there is a transaction on the

16

signal_name’last_event
signal_name’last_active
signal_name’last_value
signal_name’delayed(T)
signal_name’stable(T)
signal_name’quiet(T)
signal.
returns the time interval since the last event on the
signal
returns the time interval since the last transaction on
the signal
gives the value of the signal before the last event
occurred on the signal
gives a signal that is the delayed version (by time
T) of the original one. [T is optional, default T=0]
returns a Boolean value, True, if no event has
occurred on the signal during the interval T,
otherwise returns a False. [T is optional, default
T=0]
returns a Boolean value, True, if no transaction has
occurred on the signal during the interval T,
otherwise returns a False. [T is optional, default
T=0]

An example of an attribute is

if (CLOCK’event and CLOCK=’1’) then …

This expression checks for the arrival of a positive clock edge. To find out how much time
has passed since the last clock edge, one can use the following attribute:
CLOCK’last_event

1.10.2 Scalar attributes

Several attributes of a scalar type, scalar-type, are supported. The following table shows
some of these attributes.

TABLE 1.3

Attribute Value
scalar_type’left returns the first or leftmost value of scalar-
type in its defined range
scalar_type’right returns the last or rightmost value of scalar-
type in its defined range
scalar_type’low returns the lowest value of scalar-type in its

17
 defined range
scalar_type’high returns the greatest value of scalar-type in
its defined range
scalar_type’ascending True if T is an ascending range, otherwise
False
scalar_type’value(s) returns the value in T that is represented by
s (s stands for string value).

1.10.3 Array Attributes

By using array attributes one can return an index value corresponding to the array range.
The following attributes are supported:

TABLE 1.4

Attribute Returns
MATRIX‘left(N) left-most element index
MATRIX’right(N) right-most index
MATRIX’high(N) upper bound
MATRIX’low(N) lower bound
MATRIX’length(N) the number of elements
MATRIX’range(N) range
MATRIX’reverse_range(N) reverse range
MATRIX’ascending(N) a Boolean value TRUE if index is an
ascending range, otherwise FALSE

1.11 Operators

VHDL supports different classes of operators that operate on signals, variables and
constants. The different classes of operators are summarized below.

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TABLE 1.5

Class
1. Logical operators And Or nand nor xor xnor
2. Relational = /= < <= > >=
operators
3. Shift operators Sll Srl sla sra rol ror
4.Addition operators + = &
5. Unary operators + -
6. Multiplying op. * / mod rem
7. Miscellaneous op. ** Abs not

1.11.1 Logic Operators

The logic operators (and, or, nand, nor, xor and xnor) are defined for the “bit”, “boolean”,
“std_logic” and “std_ulogic” types and their vectors. They are used to define Boolean logic
expression or to perform bit-per-bit operations on arrays of bits. They give a result of the
same type as the operand (Bit or Boolean). These operators can be applied to signals,
variables and constants.

1.11.2 Relational operators

The relational operators test the relative values of two scalar types and give as result a
Boolean output of “TRUE” or “FALSE”.

TABLE 1.6

Operator Description Operand Types Result Type

= Equality any type Boolean
/= Inequality any type Boolean
< Smaller than scalar or discrete array Boolean
types
<= Smaller than or equal scalar or discrete array Boolean
types
> Greater than scalar or discrete array Boolean
types

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>= Greater than or equal scalar or discrete array Boolean
types

1.11.3 Shift Operators

These operators perform a bit-wise shift or rotate operation on a one-dimensional array of

elements of the type bit (or std_logic) or Boolean.

TABLE 1.7 SHIFT OPERATORS

Operator Description Operand Type Result Type

Sll Shift left logical (fill right Left: Any one-dimensional Same as left
vacated bits with the 0) array type with elements of type
type bit or Boolean; Right:
integer
Srl Shift right logical (fill left same as above Same as left
vacated bits with 0) type
Sla Shift left arithmetic (fill right same as above Same as left
vacated bits with rightmost type
bit)
Sra Shift right arithmetic (fill left same as above Same as left
vacated bits with leftmost type
bit)
Rol Rotate left (circular) same as above Same as left
type
Ror Rotate right (circular) same as above Same as left
type

The operand is on the left of the operator and the number (integer) of shifts is on the right
side of the operator. As an example,
variable NUM1 :bit_vector := “10010110”;
NUM1 srl 2;
will result in the number “00100101”.
When a negative integer is given, the opposite action occurs, i.e. a shift to the left will be a
shift to the right.

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1.11.4 Addition Operators

The addition operators are used to perform arithmetic operation (addition and subtraction)
on operands of any numeric type. The concatenation (&) operator is used to concatenate
two vectors together to make a longer one. In order to use these operators one has to
specify the ieee.std_logic_unsigned.all or std_logic_arith package package in addition to
the ieee.std_logic_1164 package.

TABLE 1.8 ADDITION OPERATORS

Operator Description Left Operand Right Operand Result Type

Type Type
+ Addition Numeric type Same as left Same type
operand
- Subtraction Numeric type Same as left Same type
operand
& Concatenation Array or element Same as left Same array type
type operand

1.11.5 Unary operators

The unary operators “+” and “-“ are used to specify the sign of a numeric type.

TABLE 1.9 UNARY OPERATORS

Operator Description Operand Type Result Type

+ Identity Any numeric type Same type
- Negation Any numeric type Same type

1.11.6 Multiplying Operators

The multiplying operators are used to perform mathematical functions on numeric types
(integer or floating point).

TABLE 1.10

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Operator Description Left Operand Right Operand Result Type
Type Type
Any integer or Same type Same type
* Multiplication floating point
Any physical Integer or real Same as left
type type
Any integer or Any physical Same as right
real type type
/ Division Any integer or Any integer or Same type
floating point floating point
Any physical Any integer or Same as left
type real t ype
Any physical Same type Integer
type
Mod Modulus Any integer type Same type
Rem Remainder Any integer type Same type

The multiplication operator is also defined when one of the operands is a physical type and
the other an integer or real type.
The remainder (rem) and modulus (mod) are defined as follows:
A rem B = A –(A/B)*B (in which A/B in an integer)
A mod B = A – B * N (in which N is an integer)
The result of the rem operator has the sign of its first operand while the result of the mod
operators has the sign of the second operand.
Some examples of these operators are given below.
11 rem 4 results in 3
(-11) rem 4 results in -3
9 mod 4 results in 1
7 mod (-4) results in –1 (7 – 4*2 = -1).

22
 CHAPTER 2

INTRODUCTION TO CODING TECHNIQUES

X1

Encoded bits

Msg bit Commutator switch

X2

states
Figure 2.1 CONVOLUTIONAL ENCODER WITH n=2,k=1,l=2

 It is a convolutional encoder with n=2,k=1 and l=2

Where n=no of encoded bit per message bit

K=no of message bit taken at a time
L= encoder memory
23
  This is achieved by using two or more mod 2 adders to the register and
interleaving the encoded bits via commutator switch.
 X1=m0 (+) m1 (+) m2
 X2=m0 (+) m2
 Commutator switch select the encoded bits alternately to produce the stream of
encoded bits .
Sourc Bitstrea Bitstream
information m with
e Source Channel Modulat
redundancy
Encoder Encoder or
Convolution
al noise
encoder

Source Channel DeModul

Sink Decoder Decoder ator
Bitstrea Viterb
m
Figure 2.1 DIGITAL TRANSMISSION
i
2.2 Algorithm To Generate VHDL Code

2.2.1 Entity

 A clock
 n- bit input for message.
 2n bit output for encoded data.
 A shift register which contains message bits.

2.2.2 Architecture

 Shift reg initially contains Ist message bit[m(0)] and all the elements zero.
 In next step it is shifted by 1 place and it’s 1 bit

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 m(0) 0 0

1 bit shifting

m(0)
m(1) 0
0

m(2) m(1) m(0)

0

And so on….
Figure 2.2 Shifting In Convolutional Codes

 Calculate x1 and x2
 Store in output vector.
2.3 The Viterbi Algorithm

 Finds a bit-sequence in the set of all possible transmitted bit-sequences that most
closely resembles the received data.

 Maximum likelihood algorithm

o Each bit received by decoder associated with a measure of correctness.
o Practical for short constraint length convolutional codes

 State
o Encoder memory
 Branch
o k/ij,

25
 where i and j represent the output bits associated with input bit k

0/0
0
0
0/1 0 1/1
1 1/0 1
0
0 1
1 0
0/1 1/0
0/0 0 1
1 1
1

1/10

Figure 2.3 STATE DIAGRAM

00

10

01

11

Figure 2.4 TRELLIS DIAGRAM

 Motivation
o Extremely large memory and logic for Viterbi
 Algorithm
o Fewer number of paths retained

26
 o Reduced memory and computation
 Definitions
o Path – Bit sequence
o Path metric or cost – Accumulated error metric of a path
o Survivor – Path which I s retained for the subsequent time step

2.4 Hamming Codes

 In the late 1940’s Richard Hamming recognized that the further evolution of
computers required greater reliability, in particular the ability to not only detect
errors, but correct them.
 His search for error-correcting codes led to the Hamming Codes, perfect 1-error
correcting codes, and the extended Hamming Codes, 1-error correcting and 2-error
detecting codes.

2.4.1 Uses

 Hamming Codes are still widely used in computing, telecommunication, and other
applications.
 Hamming Codes also applied in
o Data compression
o Some solutions to the popular puzzle
o Block Turbo Codes

2.4.2 Working Of Hamming Code

 The Hamming_Encoder is the (11, 7, 1) Hamming code encoder that converts a 7-

bit ASCII code into an 11-bit code word and the Ham-ming_ Decoder is the (11, 7,
1)Ham-ming code decoder that converts an 11-bit code word back into a
7-bitASCII code after correcting the single bit error, if any.

e.g. a 7 bit message bit is encoded as…

27
  Parity bits are added at the even position in the pattern of
First parity bit at 2
Second parity bit at 2
Third parity bit at 2
And so on…

Message bits D6 D5 D4 D3 D2 D1 D0

11 10 9 8 7 6 5 4 3 2 1

P0 FIRST PARITY

P1 P0 SECOND PARITY

P2 P1 P0 THIRD PARITY

P3 P2 P1 P0 FOURTH PARITY

11 10 9 8 7 6 5 4 3 2 1

NOW MESSAGE BITS ARE

D6
D5 D4 P3 D3 D2 D1 P2 D0 P1 P0

This is the encoded data.

Where P0 is calculated as
D6
- D4 - D3 - D1 - D0 - P0

28
 P0 =D0 XOR D1 XOR D3 XOR D4 XOR D6

P1 is calculated as
D6
D5 - - D3 D2 - - D0 P1

P1 =D0 XOR D2 XOR D3 XOR D5 XOR D6

P2 is calculated as
-
- - - D3 D2 D1 P2

P2 =D1 XOR D2 XOR D3

P3 is calculated as
D6
D5 D4 P3

P3 =D4 XOR D5 XOR D6

SO THE ENCODED 11 BIT DATA IS

D6
D5 D4 P3 D3 D2 D1 P2 D0 P1 P0

CHAPTER 3

ENCODER IMPLEMENTATION USING VHDL

3.1 Vhdl Code For Hamming Encoder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
29
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity enco is
port(data : in std_logic_vector(0 to 6 );
y : out std_logic_vector(0 to 10));
end enco;

architecture Behavioral of enco is

begin
process(data)

variable r: std_logic_vector(0 to 3) ;
variable j,k,l : integer;
begin
k:=1;
j:=1;
l:=0;

r(0):=data(0) xor data(1) xor data(3) xor data(4) xor data(6);

r(1):=data(0) xor data(2) xor data(3) xor data(5) xor data(6);
r(2):=data(1) xor data(2) xor data(3);
r(3):=data(4) xor data(5) xor data(6);

y(0)<=r(0);
for i in 1 to 10 loop

if(i=((2*k)-1)) then
y(i)<=r(j);

30
j:=j+1;
k:=2*k;
else
y(i)<=data(l);
l:=l+1;
end if;
end loop;
end process;
end Behavioral;

31
Fig. RTL view of Hamming Encoder as individual ckt

32
33
3.2 Vhdl Code For Convolutional Encoder

3.2.1 Intermediate clock

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

34
 entity intermclk is
port(clock,r : in std_logic;
q: out std_logic);
end intermclk;

architecture Behavioral of intermclk is

begin
process(clock,r)
variable v: integer;
begin
if(r='1')then
v:=0;
q<='0';
elsif(clock'event and clock='1')then
v:=v+1;
if(v=2048)then
q<='1';
elsif(v=4086)then
q<='0';
v:=0;
else
null;
end if;
else
null;
end if;
end process;
end Behavioral;

3.2.2 Shifter

35
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity piso is
port(clk,r : in std_logic;
d: in std_logic_vector(0 to 2);
p: out std_logic);
end piso;

architecture Behavioral of piso is

component intermclk is
port(clock,r : in std_logic;
q: out std_logic);
end component intermclk;
signal iclk : std_logic;

begin
u1: intermclk port map (clk,r,iclk);

process(iclk,r,d)
variable v: natural;
variable vdata,vodata : std_logic_vector(0 to 2);
begin

if(r='1')then
v:=0;

36
 vdata:=d;
p<='Z';
elsif(iclk'event and iclk='1')then
v:=v+1;
if(v<4) then
p<=vdata(2);
--for j in 0 to 1 loop
vodata:='0' & vdata(0 to 1);
--end loop;
--vodata(0):='0';
vdata:=vodata;
--end if;
elsif(v>=4)then

p<='Z';
null;
end if;
else
null;
end if;
end process;
end Behavioral;

3.2.3 Main Programme of Convolutional

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity encoder is
port(ck,rt : in std_logic;
37
 data: in std_logic_vector(0 to 2);
endata : out std_logic_vector(0 to 5));
end encoder;

architecture Behavioral of encoder is

component piso is
port(clk,r : in std_logic;
d: in std_logic_vector(0 to 2);
p: out std_logic);
end component piso;

component intermclk is
port(clock,r : in std_logic;
q: out std_logic);
end component intermclk;

type state is (a,b,c,d);

signal ps,ns : state;
signal ot : std_logic_vector(0 to 1);
signal pisot,ick : std_logic;

begin

u1: piso port map (ck,rt,data,pisot);

u2: intermclk port map (ck,rt,ick);
process(ick,rt,ot)
variable aa : std_logic_vector(0 to 7) ;
variable j :integer:=0;
begin
if(rt='1')then
aa:="ZZZZZZZZ" ;
j:=0;
ps<=a;
else
null;
end if;
endata<= aa(2) & aa(3) & aa(4) & aa(5) & aa(6) & aa(7);
end process;
process(ps,ns,pisot)
begin
case ps is
when a =>
if(pisot='0')then
ot<="00";
ns<=a;
elsif(pisot='1')then
ot<="11";
ns<=b;

38
else
null;
end if;
elsif(pisot='1')then
ot<="01";
ns<=d;
else
null;

end if;
when c=>
if(pisot='0')then
ot<="11";
ns<=a;
elsif(pisot='1')then
ot<="00";
ns<=b;
else
null;
end if;
null;
end if;
when others=>
null;
end case;
end process;
end Behavioral;

39
40
3.3 ENCODER FOR BOTH HAMMING & CONVOLUTIONAL

3.3.1 Intermediate clock

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

41
 entity clock is
port(clk,r:in std_logic;
clk1: out std_logic);
end clock;

architecture Behavioral of clock is

begin
process(clk,r)
variable v: integer :=0;
begin
if (r='1') then
v:=0;
clk1<='0';
elsif(clk'event and clk='1' and r='0') then
v:=v+1;
if(v<=2044 and v>=1)then
clk1<='0';
elsif(v=2045) then
clk1<='1';
elsif(v=4090)then
clk1<='0';
v:=0;
else null;
end if;
end if;
end process;
end Behavioral;

3.3.2 Encoder

library IEEE;

42
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
--ch=0 for hamming and 1 for comvolution;
entity encoder is
port(clk2,ch:in std_logic;
in7:in std_logic_vector(6 downto 0);
conv:out std_logic_vector(0 to 1);
hamm:out std_logic_vector(10 downto 0));
end encoder;
architecture Behavioral of encoder is
begin
process(clk2,ch,in7)
variable m:std_logic_vector(2 downto 0):="000";
variable v:integer range 0 to 7:=0;
begin
if(clk2'event and clk2='1'and ch='1')then
if(v<7)then
m(0):=m(1);
m(1):=m(2);
m(2):=in7(v);
conv(1)<=m(2) xor m(0);
conv(0)<=m(2) xor m(1) xor m(0);
v:=v+1;
else null;
end if;
else null;
end if;
if(ch='0') then

43
 hamm(0)<=in7(0) xor in7(1) xor in7(3) xor in7(4) xor in7(6);
hamm(1)<=in7(0) xor in7(2) xor in7(3) xor in7(5) xor in7(6);
hamm(2)<=in7(0);
hamm(3)<=in7(1) xor in7(2) xor in7(3);
hamm(4)<=in7(1);
hamm(5)<=in7(2);
hamm(6)<=in7(3);
hamm(7)<=in7(4) xor in7(5) xor in7(6);
hamm(8)<=in7(4);
hamm(9)<=in7(5);
hamm(10)<=in7(6);
else null;
end if;
end process;
end Behavioral;

3.3.3 MAIN PROGRAMME

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity link is

44
port (clk,r,ch : in std_logic;
in7:in std_logic_vector(6 downto 0);

conv: out std_logic_vector(0 to 1);

hamm: out std_logic_vector(0 to 10));
end link;

architecture Behavioral of link is

component clock is

port(clk,r:in std_logic;
clk1: out std_logic);
end component clock;

component encoder is

port(clk2,ch:in std_logic;
in7:in std_logic_vector(6 downto 0);
conv:out std_logic_vector(0 to 1);
hamm:out std_logic_vector(0 to 10));

end component encoder;

signal clks :std_logic;

begin
U1:clock
port map(clk,r,clks);
U2:encoder
port map(clks,ch,in7(6 downto 0),conv(0 to 1),hamm(0 to 10));

end Behavioral;

45
46
47
 CHAPTER 4

DECODER IMPLEMENTATION USING VHDL

4.1 VHDL Code For Convolutional Decoder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

48
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity deco is
port( clk,r : in std_logic;
m :in std_logic_vector(0 to 7);
de_m: out std_logic_vector(0 to 3 ));
end deco;
architecture Behavioral of deco is
function compar(a,b,m,n :std_logic) return natural is
variable va1: natural;
begin
if(a=m and b=n)then
va1:=0;
elsif(a/=m and b=n)then
va1:=1;
elsif(a=m and b/=n)then
va1:=1;
elsif(a/=m and b/=n)then
va1:=2;
else
null;
end if;
return va1;
end compar;
type last is array (0 to 3)of natural;

signal vaa1,vb2,vbb1,vd2: natural;

type state is (s0,a1,b1,s1,a2,b2,c2,d2,s2,a3,b3,c3,d3,ndvalue,endst);
signal ps,ns : state;

49
begin

process(clk,r)
begin
if(r='1')then
ps<=s0;
elsif(clk'event and clk='1')then
ps<=ns;
else
null;
end if;
end process;
process(ps,m)
variable vaaa1,va1,vb1,v3a2,vb3,v3b2,vc3,v3c2,vd3,v3d2,i : natural;
variable w: integer :=2;
variable ot1,ot2,ot3,ot4,ot11,ot22,ot33,ot44: std_logic_vector(0 to (m'length/2)-1);
variable last_fr : last;
variable min:natural;
begin
case ps is
when s0=>
ns<=a1;
when s1=>
ns<=a2;
i := i+2;
when s2 =>
ns <= a3;
i := I +2;
when others=>
null;
end case;
case ps is

50
when a1=>
va1 := compar(m(i), m(i+1),'0','0') ;
ns<=b1;
when b1=>
vb1 := compar(m(i), m(i+1),'1','1') ;
ns<=s1;

when a2=>
vaa1 <= va1 + compar(m(i), m(i+1),'0','0') ;
--here va1 is updated if return value is 0 then...?
ns<=b2;

when b2=>

--if --this fun returns 0 value

-- then signal va1 will nt change
-- and 'last value is the value of

vb2 <= (va1) + compar(m(i), m(i+1),'1','1') ;

-- 2 clock back so we will take same value.
-- and we'll do same thing everywhere
ns<=c2;

when c2=>
vbb1 <= vb1 + compar(m(i), m(i+1),'1','0') ;
ns<=d2;

when d2=>
vd2<=vb1 + compar(m(i), m(i+1),'0','1');
ns<=s2;
--IIIrd stage-- for each node two values will b calculated.

when a3 =>

51
if(i>(m'length-2))then
--if encoded msg length is 6 bit then for i=4 ,bit 4 n 5 r calulated.
--so for 8 bit i should be 6 and for 10 bit i=8 and so on.........
min:=vaa1;
ns<=endst;
else
vaaa1:= (vaa1) + compar(m(i), m(i+1),'0','0') ;
v3a2:=vbb1 + compar(m(i), m(i+1),'1','1') ;
ns<=b3;
end if;

when b3=>
vb3:= vaa1 + compar(m(i), m(i+1),'1','1');
v3b2:= vbb1 + compar(m(i), m(i+1),'0','0') ;
ns<=c3;

when c3=>
vc3 := vb2 + compar(m(i), m(i+1),'1','0') ;
v3c2:= vd2+compar(m(i), m(i+1),'0','1') ;
ns<=d3;

when d3=>
vd3 := vb2 + compar(m(i), m(i+1),'0','1') ;
v3d2:= vd2 + compar(m(i), m(i+1),'1','0') ;
ns<=ndvalue;

for u in 0 to ((m'length/2)-1 )loop

ot1(u):=ot3(u);
end loop;
ot1(w):='0';
end if;

52
else -- vaa1<=vaaa1;
if(w=2)then
ot1(0):='0';
ot1(1):='0';
ot1(2):='0';
else
ot11:=ot1;

for u in 0 to ((m'length/2)-1) loop

ot1(u):=ot1(u);
end loop;
ot1(w):='0';
end if;
end if;
-- vb1--- nd c3 ---vb1 ----vc3,v3c2
--vd2---- nd d3 ---vd2 --- vd3,v3d2 r the two values at each node.
if(vb3>v3b2)then
vb2<=v3b2;
--again stored value in vb2 coz all caculation at stage 3 are done by nodes
va1,vb2,vb1,vd2.
--vb2 as IInd node in calculation
ot2(w):='1';
end if;

else
vb2<=vb3;
if(w=2)then
ot2(0):='0';
(1):='0';
ot2(2):='1';
else
ot22:=ot2;
for u in 0 to ((m'length/2)-1 ) loop

53
ot2(u):=ot11(u);
end loop;
ot2(w):='1';
end if;
end if;
if(vc3>v3c2)then
vbb1<=v3c2;
----again stored value in vb1 coz all caculation at stage 3 are done by nodes
va1,vb2,vb1,vd2.
--vb1 as III node in calcu.

if(w=2)then
ot3(0):='1';
ot3(1):='1';
ot3(2):='0';

else
ot33:=ot3;
for u in 0 to ((m'length/2)-1) loop
ot3(u):=ot4(u);
end loop;
ot3(w):='0';
end if;

else
vbb1<=vc3;
if(w=2)then
ot3(0):='0';
ot3(1):='1';
ot3(2):='0';

else
ot33:=ot3;

54
for u in 0 to ((m'length/2)-1) loop
ot3(u):=ot22(u);
end loop;
ot3(w):='0';
end if;
end if;

if (vd3 > v3d2) then

vd2 <= v3d2;
if(w=2)then
ot4(0):='1';
ot4(1):='1';
ot4(2):='1';

else
ot44:=ot4;
for u in 0 to ((m'length/2)-1)loop

ot4(u):=ot4(u);
end loop;

ot4(w):='1';
end if;

else
vd2 <= vd3 ;
if(w=2)then
ot4(0):='0';
ot4(1):='1';
ot4(2):='1';

else

55
ot44:=ot4;
for u in 0 to (m'length/2)-1 loop
ot4(u):=ot22(u);
end loop;
ot4(w):='1';
end if;
end if;
w:=w+1;
ns<=s2;

when endst=>
last_fr(0):=vaa1;
last_fr(1):=vb2;
last_fr(2):=vbb1;
last_fr(3):=vd2;

for q in 1 to 3 loop
if(min>last_fr(q))then
min:=last_fr(q);
else
min:=min;
end if;
end loop;

if(min=last_fr(0) )then
de_m<=ot1;
elsif(min=last_fr(1))thende_m<=ot2;
elsif(min=last_fr(2))then
de_m<=ot3;

elsif(min=last_fr(3))then
de_m<=ot4;

56
else
de_m<=ot1;
end if;

when others=>
null;
end case;
end process;
end Behavioral;

57
 CONCLUSION & future scope of work
4.1 CONCLUSION
4.2 LIMITATION
4.3 FUTURE SCOPE OF WORK

VHDL has been at the heart of electronic design productivity since initial ratification
by the IEEE in 1987.It can be said that VHDL fueled modern synthesis technology
and enabled the development of ASIC semiconductor companies.From the beginning
VHDL has been a powerful language with numerous language constructs that are
capable of describing very complex behavior ,this leadership of the VHDL
community has assured open and internationally accredited for the electronic design

58
engg. community. The legacy of this team’s work continues to benefit the design
community today as the benchmark by which one measures openness.

59