IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO.
4, APRIL 2010
Accurate EM-Based Modeling of Cascode FETs
Davide Resca, Member, IEEE, Julio A. Lonac, Rafael Cignani, Antonio Raffo, Member, IEEE,
Alberto Santarelli, Member, IEEE, Giorgio Vannini, Member, IEEE, and Fabio Filicori
Abstract—Cascode field-effect transistors (FETs) are widely
used in the design of monolithic microwave integrated circuits
(MMICs), owing to their almost unilateral and broadband be-
havior. However, since a dedicated model of the cell is rarely
provided by foundries, a suboptimal description built by repli-
cating the standard foundry model for both the common source
and common gate device is often adopted. This might limit the
success of the MMIC design at the first foundry run.
This paper describes an electromagnetic-based empirical model
of cascode cells, covering topics from the formulation and iden-
tification procedures to the corresponding validation described in
an exhaustive experimental section. A MMIC low-noise distributed
amplifier case is then presented and the proposed model is used for
circuit analysis and instability detection. Clear indication is pro-
vided about the improvement in the prediction of critical behaviors
with respect to conventional modeling approaches. A cascode cell
with a symmetric layout is also successfully modeled.
Index Terms—Electromagnetic (EM) analysis, microwave field-
effect transistors (FETs), monolithic microwave integrated circuits
(MMICs), semiconductor device modeling.
I. INTRODUCTION
F IELD-EFFECT transistors (FETs) connected in a cascode
configuration (cascode FETs) have widespread usage in
monolithic microwave integrated circuits (MMICs), such as
in gain controlled amplifiers, phase shifters, broadband power
amplifiers, traveling-wave distributed amplifiers, and mixers
[1]–[5]. A cascode cell is composed of a common source
(CS) stage cascaded by a common gate (CG) stage. This is
implemented either using a double-gate device or using two
single-gate transistors.
As is well known, the first successful design of MMICs re-
quires empirical active device models, which must be accurate,
computationally efficient, and easily identifiable. In the case of
cascode FETs, the design of the circuit is complicated since the
design kit provided by the foundries usually include neither the
cascode FET model, nor a CG FET model. In the same way,
Manuscript received July 28, 2009; revised October 13, 2009. First published
March 08, 2010; current version published April 14, 2010. This work was sup-
ported by MEC s.r.l., carried out jointly with the University of Bologna and the
University of Ferrara.
D. Resca and J. A. Lonac are with Microwave Electronics for Communica-
tions, MEC s.r.l., 40123 Bologna, Italy (e-mail: davide.resca@mec-mmic.com;
julio.lonac@mec-mmic.com).
R. Cignani, A. Santarelli, and F. Filicori are with the Department of Elec-
tronics, Computer Science and Systems (DEIS), University of Bologna, 40136
Bologna, Italy (e-mail: rafael.cignani@unibo.it; alberto.santarelli@unibo.it;
fabio.filicori@unibo.it).
A. Raffo and G. Vannini are with the ENDIF, University of Ferrara, 44100
Ferrara, Italy (e-mail: antonio.raffo@unife.it; giorgio.vannini@unife.it).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2010.2041576
0018-9480/$26.00 © 2010 IEEE
719
cascode or CG device samples to be characterized are not usu-
ally readily available, as it would be needed for the identifica-
tion of many empirical models found in the literature [6]–[11].
As the only viable alternative, a cascode FET model is often
built by exploiting the only resource available from the foundry,
which is typically the CS FET model (direct -parameter mea-
surements can also be used when a device sample is available).
On this basis, a rough model of the CG device can be obtained
by means of simple admittance matrix transformations [8], [12]
or by simple rotation once the source electrode has been floated.
The cascode cell model is then eventually obtained by intercon-
nection of the CS and CG descriptions. However, this proce-
dure was found not accurate enough since the extrinsic para-
sitic network identified for the CS FET (defined at the intrinsic
gate–source and drain–source reference planes) could be very
different from that of the CG FET in the cascode cell [13]. In
turn, model inaccuracies of the CG stage affect the prediction
accuracy of the whole cascode cell [13].
In order to overcome the above problems, an accurate
EM-based empirical model of cascode FETs is proposed in this
paper. In particular, Section II deals with model definition and
identification procedures. In Section III, the proposed cascode
FET model is applied to a conventional cascode cell layout.
Its predictions are compared to both measurements and sim-
ulations obtained through a conventional modeling approach.
A practical application to the analysis of a 0.8–20-GHz GaAs
MMIC distributed amplifier based on six cascaded stages is
discussed. Finally, an additional experimental validation is pre-
sented in Section IV, where the electromagnetic (EM)-based
modeling approach is applied to a nonstandard cascode cell
with symmetric layout.
II. EM-BASED MODELING APPROACH
The EM-based modeling methodology described in [14] has
been successfully adopted in the past for the linear and non-
linear modeling of a single transistor. Despite its simplicity, the
approach provides high prediction accuracy and scaling capa-
bilities.
According to this methodology, a general CS device, consid-
ered here as a reference sample, can be modeled by an equiva-
lent two-port intrinsic device (EqID) connected to a linear dis-
tributed four-port passive network, which accounts for the ex-
trinsic parasitics related to the metallization layout [14]. In par-
ticular, according to Fig. 1(c), the latter can be described by its
[4 4] admittance matrix such that
(1)
where
.
720 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 4, APRIL 2010
Fig. 1. Single transistor EM-based empirical model. Device layout EM
simulation setup: (a) where N equivalent intrinsic devices, EIDs, are defined.
(b) Empirical model (c) composed of a compact four-port distributed parasitic
network connected to a single EqID.
Accordingly to [14], in order to identify the matrix, the
device geometry is preliminary divided into a number of el-
ementary intrinsic devices (EIDs) placed along the fingers. A
single EID per finger is typically chosen, as shown in Fig. 1(a).
The EIDs are then interconnected by a linear multiport “pas-
sive distributed structure,” whose admit-
tance matrix is directly obtained through accurate EM
simulations [15], [16]. This multiport description is eventually
compacted into a four-port network by calculating the elements
of through closed-form linear combinations of the ele-
ments of . The main relationships are briefly recalled in
the Appendix for the sake of completeness.
Two basic hypotheses are involved in this port compacting
procedure, which are: 1) the EIDs are considered equal to each
other (both from a geometrical and electrical point of view) and
2) the EIDs are considered equally excited. In particular, relative
differences of both attenuation and delay of signals traveling
across the device active region are assumed to be negligible.
This has been proved quite reasonable in “well-designed” small/
medium size devices, since either nonuniform current densities
along the fingers or strongly not-in-phase current combinations
from different device fingers correspond to suboptimal device
performance [14], [17].
A compact model is proposed in this work for the cascode
FET [13]. In this case, two CS and CG stages are closely con-
nected, as depicted, for instance, in Fig. 2, and act as a single
functional cell.
According to the same EM-based methodology, we propose
to model the cascode cell by means of two EqIDs (i.e., EqID ,
EqID ), one for the CS and the other for the CG stage, con-
nected to a linear distributed six-port passive network describing
the extrinsic parasitics related to the metallization layout of the
overall cell. According to Fig. 2(b), the admittance matrix
of this six-port network is defined as
(2)
Fig. 2. Cascode transistor EM-based empirical model. Device layout EM sim-
N
ulation setup: (a) where ( + N ) EIDs are defined. (b) Empirical model
composed of a compact six-port distributed parasitic network connected to two
EqIDs one for the CS FET, and the other for the CG FET.
where
.
In order to identify the matrix, both the CS and CG
device geometries may be preliminary partitioned into a number
and of EIDs, respectively. These are placed along
the layout fingers of both the CS and CG FETs. The EIDs are
interconnected by a linear passive distributed structure, which is
described in terms of a
admittance matrix , which can still be obtained directly
through EM simulation.
The compacting procedure of the linear distributed multiport
network into a minimal six-port one can be carried out by ap-
plying the same assumptions made for the single transistor in a
local way, i.e., by considering the CS and CG stages one by one
(EIDs inside the CS stage are equal and equally excited and sim-
ilar conditions hold for the EIDs into the CG). According to this
criterion, the matrix can be identified on the basis of the
closed-form relationships in (3), shown at the bottom of the fol-
lowing page, where (with
are the elements of the matrix . Analytical derivation is re-
ported in the Appendix for the sake of completeness.
The proposed model of the cascode FET is thus obtained
according to the flowchart shown in Fig. 3(a)–(c). The proce-
dure consists in three phases, which are: a) data acquisition
for model identification through EM-simulations and measure-
ments; b) data manipulation leading to the identification of the
extrinsic and intrinsic parts of the model; and c) linear scaling of
the intrinsic CS and CG elementary device models (if needed)
and cascode cell model implementation. The three phases will
be now described individually in more detail.
RESCA et al.: ACCURATE EM-BASED MODELING OF CASCODE FETs
Fig. 3. Flowchart describing the EM-based cascode model identification pro-
cedure.
A. Data Acquisition for Model Identification
The cascode configuration consists of a CS FET cascaded
with a CG FET, where the two devices may have different
peripheries and may operate in different bias conditions. Let
and be the number of gate fingers
and the unit gatewidths of the CS FET and CG FET, respec-
tively. Let and represent the selected quiescent
conditions of the CS and CG FETs, respectively, within the
cascode cell.
The following data are needed to identify the model proposed.
• Single transistor representative of the foundry process (a
conventional CS FET) to be treated as reference device or,
at least, an empirical model of it. Let m be
its periphery (not necessarily equal to that of the cascode
CS and CG FETs thanks to the scaling capabilities offered
by the EM-based model [14]).
• Layout of the reference device.
• Layout of the cascode cell.
• Technological process parameters such as substrate/pas-
sivation oxide dielectric characteristics and metallization
conductivities.
The EM simulation of the reference device and the cascode
cell passive structures are performed according to the setup of
721
Figs. 1(a) and 2(a), respectively. “Internal” kind of ports (see
Section III) offered by commercial EM simulators, are exploited
to define the EIDs attachment points into the CS and CG regions.
It is worth pointing out that these EM simulations have to be
performed just once during the model identification phase and
do not represent a limitation of the numerical efficiency of the
final model.
-parameters of the reference device are then measured (or
simulated through the foundry model) for each bias condition
. The loop in the bias conditions shown in Fig. 3 will cover the
required quiescent conditions and of the CS and CG
devices.
According to Fig. 3, the admittance matrix represents
the multiport descrip-
tion of the cascode cell interconnecting structure, the admittance
matrix is the multiport description of
the reference device interconnecting structure, while
corresponds to the measured (or simulated) admittance matrix
of the intrinsic reference device biased at the quiescent condi-
tion .
Although the admittance matrices defined in the following
are functions of frequency, explicit dependence notation will be
omitted in the following for the sake of simplicity.
B. Matrix Manipulation and De-Embedding
The compact and admittance matrices, describing
the reference device and cascode cell extrinsic parasitic net-
works, respectively, are identified in this phase on the basis
of the multiport admittance matrices and . Details
on the algebraic manipulations needed for these operations are
given in the Appendix.
Moreover, the reference device broadband -parameters
(measured or simulated) are de-embedded from the extrinsic
parasitic network described by the matrix. This leads to an
intrinsic reference device described by the admittance matrix
for each required bias condition . Details on the
de-embedding procedure can also be found in the Appendix.
C. EqID Scaling and Cascode Model Implementation
The admittance matrices describe the strictly in-
trinsic behavior of the m reference device. These
722 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 4, APRIL 2010
data can be easily linearly scaled to obtain and
as follows:
(4)
The extrinsic and the intrinsic parts of the proposed cascode
cell empirical model (see Fig. 2) have been identified so far. The
model can be now easily implemented into any linear frequency
domain simulator by circuit connecting the identified CS and
CG EqIDs to the six-port distributed parasitic network described
by the matrix. For the purpose of this work, the blocks of
Fig. 2(b) are implemented through frequency-dependent lookup
tables ( -parameter blocks, Touchstone file based). However,
any available lumped equivalent circuit, describing either the ex-
trinsic parasitic network (by using, for example, automated syn-
thesis techniques [18]) and/or the intrinsic device (linear equiv-
alent circuit or mathematical model [19]–[23]) could be adopted
according to the designer preferences.
The proposed procedure can be easily extended to the case
of nonlinear modeling after indentifying the EqID frequency
response over a dense grid of different bias conditions.
III. MODEL VALIDATION: CONVENTIONAL CASCODE CELL
In order to validate the EM-based modeling approach pre-
sented in Section II, a MMIC cascode cell based on the 0.25- m
XKu pseudomorphic HEMT (pHEMT) 3MI GaAs process of
Triquint Semiconductors has been considered.
The EM simulator accuracy was first verified by simulating
some passive test structures such as lines, capacitors, and in-
ductors, by using the physical parameters available from the
foundry manual. Good agreement between the simulated and
measured behavior was obtained. No tuning of the parameters
was needed in this phase.
The cascode cell consists of two 150- m devices having
and m. Both the
CS and CG FETs are biased in the same class A operating
condition, at V and mA (thus, according to
the Section II notation, ). The cell, whose layout
is shown in Fig. 4, was manufactured and fully characterized
by means of -parameter measurements in the frequency range
of 1.5–45 GHz.
A reference device was chosen with
and . Instead of experimentally charac-
terize a device sample, we used the simulated -parameters of
the available CS foundry model. This actually corresponds to
the worst case where a designer does not have a device sample
to be characterized. An EM simulation of the reference device
was first carried out, leading to the distributed [10 10] matrix
and to the compact [4 4] description of the ex-
trinsic parasitic network. De-embedding of the small-signal pa-
rameter measurements from this distributed parasitic network
under the two CS and CG bias conditions (equal in the present
case) leads to the [2 2] matrices and . of the CG FET at RF frequencies (see Fig. 4). They were re-
The whole cascode interconnecting structure was described
by the distributed [18 18] matrix , simulated through a
Fig. 4. Layout of the cascode cell adopted in this work. The cascode cell com-
2
prehensive of the stabilizing network has dimension of 0.38 mm 0.42 mm.
commercial 3-D planar EM simulator [24], where a single EID
per finger was considered. The compact [6 6] matrix
was then obtained after applying the hypotheses of equal and
equally fed EIDs within the cell. Circuit connection between the
six-port extrinsic parasitic network and the identified CS
and CG frequency responses completed the
linear model of the cascode FET.
It is worth mentioning that, owing to the peripheries of the
device samples available for measurements, this particular ex-
perimental validation did not require any scaling at all. However,
the scaling capabilities of the EM-based approach, within a cer-
tain range of peripheries, have been widely proven in [14].
As it is well known, EM simulations used in the identification
phase described in Section II-A might take quite a long time.
The minimum mesh cell dimension is indeed strongly related
to the gate channel length and unit finger width in the actual
application and it has to be defined in order to have the gate
transmission line properly simulated. For example, a rectangular
cell having dimensions 0.125 m 2.5 m was used for the
device considered. This leads to a total number of meshes in
the order of 15 000–20 000. EM simulation times are obviously
platform dependent, but they typically are in the order of hours
for a single frequency step on a medium power PC. However,
extremely accurate models are obtainable in this case, as shown,
for instance, in Fig. 5, where the magnitude of is shown
versus frequency up to 45 GHz. Similar accuracy was found on
the other parameters.
In the effort of reducing the costs related to the meshing [25],
one could be tempted by dropping some “big” structure from
the EM simulation after replacement with equivalent lumped
models or with dedicated EM simulation results. The cascode
cell passive structure was thus re-simulated by dropping the
via-hole and the large over-via capacitor, which grounds the gate
placed by lumped-circuit models in this case. A total number of
meshes in the order of 6000 was obtained leading to a dramatic
RESCA et al.: ACCURATE EM-BASED MODELING OF CASCODE FETs
Fig. 5. Two different cascode cell models S 21 prediction compared to de-
vice measurements. The bias condition is for class-A operation: V = 6 V,
I = 15 mA. Frequency range from 1.5 to 45 GHz. Crosses: device measure-
ments. Line: EM-based model where the whole structure is EM simulated. Dots:
EM-based model where the large structure has been cut away from the EM sim-
ulation.
Fig. 6. Every EID attachment point is defined as a different group (i.e., group A
and B in the figure) of floating co-calibrated ports [24]. Blue (in online version)
depicts the global local ground (GLG) meshes used for the ports calibration
procedure described in detail in [26].
reduction (about 90%) in the simulation time required to collect
the data needed for the extrinsic parasitic network identifica-
tion. Corresponding modeling results are also reported in Fig. 5,
showing very good accuracy up to almost 30 GHz. Beyond that
frequency, the coupling effects between the large structures and
the remaining device metallization cannot be neglected any-
more. Particular care must, therefore, be paid in EM-analysis
simplification, depending on the particular application consid-
ered.
Concerning the EIDs definition, floating co-calibrated in-
ternal ports available within the simulator were used in this
work [24]. They allow to define the EID attachment points
into the device passive structure without perturbing the simu-
lation with their discontinuity. Details about the co-calibrated
ports, the way to use them, and the way their discontinuities are
de-embedded from the simulated response are clearly explained
in [24] and [26]. Fig. 6 shows the subsections made by the EM
simulator in the finger region of the device, where the floating
co-calibrated ports are placed.
In order to compare the predictive capabilities of the proposed
model with other more conventional approaches, we also sim-
ulated the cascode-FET behavior by using a conventional CS
device model. To this aim, the CS linear model provided by
the foundry was modified in order to make the source floating
(by de-embedding the via-hole inductance and resistance). The
723
Fig. 7. Cascode-cell model S -parameters predictions compared to device mea-
surements. The bias condition is for class-A operation: V = 6 V, I =
15 mA. Frequency range from 1.5 to 45 GHz. Crosses: device measurements.
Lines: EM-based model. Dots: conventional model.
Fig. 8. Photograph of the manufactured low-noise wideband distributed ampli-
2
fier. The manufactured MMIC LNA has a dimension of 4 mm 2 mm, while
the die, which includes the CS FET, CG FET, and cascode cells used for the
2
model validation, as well as other test structures, is 4 mm 4 mm.
source-floating model was then connected in the CG configura-
tion following a standard CS stage. The other surrounding struc-
tures were taken into account through their design-kit circuit
models.
The cascode-FET models are compared to -parameter mea-
surements up to 45 GHz in Fig. 7. A good agreement is achieved
by means of the EM-based approach over the whole frequency
range. Instead, by far, more inaccurate predictions are obtained
with the conventional model.
As a further example, we refer now to the case of a
0.8–20-GHz GaAs MMIC low-noise broadband distributed
amplifier (LNA) based on six cascode FETs equal to the one
presented in Fig. 4. The photograph of the distributed amplifier
is shown in Fig. 8.
As it is well known, the design of the gate and drain trans-
mission lines is typically carried out on the basis of the cascode
FET input and output capacitances [27]–[29], while the input
and output conductance values strongly affect the stability of
the overall amplifier. The two capacitances
and are shown in Fig. 9. They are practi-
cally coincident with the input and output capacitances, respec-
tively, due to the almost unilateral behavior of the cascode cell.
The EM-based and conventional models are compared to mea-
surements versus frequency in the figure. The corresponding ca-
pacitance values at the passband center frequency (useful for a
first-guess gate and drain line design) are instead reported in
Table I. In addition, and
are shown in Fig. 10. It is clearly noticeable how, out of the
724 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 4, APRIL 2010

Fig. 9. Cascode cell model predictions of its input (C ) and output (C ) Fig. 10. Cascode cell model predictions of its input (G ) and output (G )
capacitances compared to their measured values. The bias condition is for
class-A operation: V = 6 V, I
conductances compared to their measured values. The bias condition is for
= 15 mA. Frequency range from 1.5
class-A operation: V = 6 V, I = 15 mA. Frequency range from 1.5
to 45 GHz. Crosses: device measurements. Lines: EM-based model. Dots: to 45 GHz. Crosses: device measurements. Lines: EM-based model. Dots:
conventional model. conventional model.

TABLE I
ACTUAL AND PREDICTED VALUES OF C AND C

two models considered, the EM-based only predicts the critical

slightly negative values of between 15–30 GHz.
The MMIC LNA, realized after being designed by means
of the conventional model, exhibits a spurious oscillation at
25 GHz. This was unfortunately not detected during the design
phase when stability tests [30], [31] were performed in order to
stabilize the amplifier. Thanks to the insertion into the elemen-
tary cascode cell of the stabilizing network, shown in Fig. 4, the
amplifier should have been stable even when considering the
whole statistical dispersion of process parameters. After an in-
vestigation made on the basis of measurements on both the final
LNA and some other related circuit cutouts, we found that the
differences between measurements and simulations of the entire
amplifier were strongly dependent on the cascode cell model. In
fact, a rather good agreement between measurements and simu-
lations was found for the lumped and distributed passive struc-
tures, while on the other hand, the conventional active device
model led to the major discrepancies highlighted in Figs. 7, 9,
and 10.
Fig. 11. Ohtomo analysis [27] of the monolithic LNA (grey conventional
model, black EM-based model).
Lately, the stability test described by Ohtomo [30] was re-
peated by using our EM-based model. As shown by the re-
sults reported in Fig. 11, a potential instability was detected at
25.28 GHz, which was completely missed by the conventional
model.
In successive tests made both experimentally and through
simulations performed by means of the EM-based model, we
found that the amplifier could be stabilized by slightly mod-
ifying the bias applied to each cascode cell (modified biases:
CS FET: V; mA, CG FET: V,
RESCA et al.: ACCURATE EM-BASED MODELING OF CASCODE FETs
Fig. 12. Ohtomo stability analysis of the stabilized amplifier (EM-based
model).
Fig. 13. Magnitude of the S -parameters of the LNA in the stabilized configura-
tion. Measurements (symbols) compared to the model predictions (lines): S 21:
crosses and red line (in online verson). S 11: circles and blue line (in online ver-
sion). S 22: diamonds and black line.
mA) at some expense of the unilateral cascode cell
behavior and, thus, of the overall amplifier performances.
The plot in Fig. 12 refers to the stability analysis made in
the modified bias condition. The amplifier is now stable, and
this was also confirmed by the experiments after measuring the
LNA sample (see Fig. 13). These additional experimental results
confirm that the EM-based model will be an extremely good tool
for future designs.
IV. SYMMETRIC-LAYOUT CASCODE CELL
In order to assess the validity of the proposed approach, it has
also been applied to the specifically designed symmetric-layout
cell shown in Fig. 14. The long air bridge (AB) in this layout
provides the cascode-like connection in a symmetric fashion by
joining the drain of the CS FET to the source of the CG FET
passing over its gate electrode.
The cell was manufactured and fully characterized in terms
of -parameters in the frequency range of [1.5–45 GHz]. It was
then modeled by means of both the EM-based model and a con-
ventional model, despite this, the latter is expected to introduce
quite rough approximations. In fact, in order to provide the sym-
metry of the layout, both the source and gate layout of the CG
stage are modified with respect to the conventional one.
725
Fig. 14. Layout of the designed symmetric cascode cell. This figure shows the
detail of the long AB, which realizes the cascode connection. The cascode cell
2
has a dimension of 0.28 mm 0.33 mm.
The cell is supposed to work under the same bias condition
as the other (both CS and CG FETs biased at V and
mA, i.e., ).
The identification procedure described in Section II was re-
peated. To this aim, the and matrices describing
the intrinsic CS and CG FETs had not to be re-extracted since
they are the same as in the previous case. The simulation of
the new metallization structure corresponding to the symmetric
layout of Fig. 14 had only to be carried out. According to the ar-
guments discussed in Section III, the two large over-via capac-
itors were taken into account into the EM simulation of the cell
to guarantee accurate predictions even at the higher frequencies.
Thus, the [18 18] matrix was obtained from the EM
simulation setup with a single EID per gate finger. The compact
[6 6] matrix was then identified and used along with the
available and matrices to complete the linear
model.
Full validation in terms of -parameters and input/output ca-
pacitance/conductance is reported in Figs. 15–17 and Table II.
The conventional model provides quite more inaccurate results
with respect to the EM-based model, as was expected.
V. CONCLUSION
An EM-based model of cascode FETs has been proposed in
this paper. The extraction procedure presents the great advan-
tage of being carried out on the basis of conventional -param-
eters of a single CS device belonging to the selected techno-
logical process. Standard information about the process, mostly
deducible from GDSII device layouts, is needed for the setting
of the EM simulations. The wide experimental validation pro-
vided shows dramatic improvements over standard modeling
approaches based on commonly available foundry data.
APPENDIX A
In order to obtain the and admittance matrices, a
procedure, which is consistent with the EqID concept defined in
Section II, is briefly exposed here [14].
726 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 4, APRIL 2010

Fig. 15. Symmetric cascode-cell model S -parameters predictions compared to

device measurements. The bias condition is for class-A operation: V =6 V,
I = 15mA. Frequency range from 1.5 to 45 GHz. Crosses: device measure-
ments. Lines: EM-based model. Dots: conventional model.

(
Fig. 17. Symmetric cascode cell model predictions of its input G ) and
(
output G ) conductances compared to their measured values. The bias
=6
condition is for class-A operation: V V, I = 15 mA. Frequency range
from 1.5 to 45 GHz. Crosses: device measurements. Lines: EM-based model.
Dots: conventional model.

TABLE II
ACTUAL AND PREDICTED VALUES OF C AND C

Fig. 16. Symmetric cascode cell model predictions of its input C( ) and
output C( ) capacitances compared to their measured values. The bias
condition is for class-A operation: V=6 V, I = 15 mA. Frequency range Two basic assumptions are made, which are: 1) the EIDs are
from 1.5 to 45 GHz. Crosses: device measurements. Lines: EM-based model.
Dots: conventional model.
considered equal one to another and 2) they are equally excited.
The two 2-port distributed parasitic network of Fig. 18
can then be compacted into either a four-port description of
The active regions of both the reference device (Fig. 1) and parasitic effects, in the case of the reference device, or into
cascode cell (Fig. 2) are partitioned in a given number of two- a six-port description of parasitic effects in the case of the
port EIDs. Every EID is interconnected to each other through a cascode cell.
distributed passive -port network, which can be charac-
terized by a admittance matrix. According A. Identification (Reference Device,
to Section II, such a matrix is either the matrix of the ref- According to Fig. 18, the two main assumptions are translated
erence device, when , or the matrix of the cas- into the following relations:
code cell, when , both obtained on the
basis of accurate EM simulations. A schematic representation
of this - port parasitic description is shown in Fig. 18,
where are the phasors of extrinsic gate–source and
drain–source voltages and extrinsic gate and drain currents, re-
spectively. Analogously,
are the phasors of the EID voltages and currents. (A.1)
RESCA et al.: ACCURATE EM-BASED MODELING OF CASCODE FETs 727

(A.4)
and

(A.5)

where are the phasors of voltages and cur-

rents at the ports of the yet unknown matrix of Fig. 2. The
Fig. 18. Distributed parasitic network (gray pattern) directly obtained from the latter can be eventually evaluated through (3), which is obtained
2
EM simulation of the device passive structure (described by a 2n + 2 2n + 2 on the basis of (A.4) and (A.5) after simple algebraic manipu-
admittance matrix). Voltage and current phasors at the external gate and drain
terminals and at the gate and drain EID terminals are also shown. lations. Thus, the elements of are linear combinations of
the elements of the
matrix representing the multiport EM description of the cascode
and cell passive structure.

C. De-Embedding of From
According to the matrix relations defined by (1), we have

(A.2) (A.6)
where are the phasors of voltages and cur-
rents at the ports of the yet unknown matrix of Fig. 1. This where
latter can be eventually evaluated on the basis of (A.1) and (A.2)
after simple algebraic manipulation, through (A.3), shown at the
bottom of this page, where are the el-
ements of the matrix.

(A.7)
B. Identification (Cascode Cell, )
According to Figs. 2 and 18, the two main assumptions are and are the elements of the matrix.
applied locally to each active area corresponding to the CS and Let and be the [2 2] matrices rep-
CG FETs. This leads to the following relations: resenting the measured extrinsic admittance and the unknown
intrinsic reference device admittance such as

(A.8)

By substituting (A.8) into (A.6), after simple matrix manipula-

tions, the unknown matrix is obtained through

(A.9)

(A.3)
728 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 58, NO. 4, APRIL 2010
ACKNOWLEDGMENT
The authors gratefully acknowledge Prof. V. A. Monaco,
MEC s.r.l., Bologna, Italy, for supporting the research reported
in this paper.
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Davide Resca (S’05–M’09) was born in Bologna,
Italy, in 1979. He received the Laurea degree in elec-
tronic engineering from the University of Ferrara,
Ferrara, Italy, in 2004, and the Ph.D. degree in elec-
tronics and computer science from the University of
Bologna, Bologna, in 2007.
Following a post doctorate grant from the Depart-
ment of Electronics, Computer Science and Systems
(DEIS), University of Bologna), in 2008, since 2009
he has been a MMIC Design Engineer with MEC
s.r.l., Bologna, Italy. His research activity is mainly
oriented to linear and nonlinear device modeling and circuit design techniques
for nonlinear microwave and millimeter-wave applications.
Julio A. Lonac was born in La Plata, Argentina, on
July 8, 1976. He received the M.S degree in elec-
tronics from the University of La Plata, La Plata, Ar-
gentina, in 2001, and the Ph.D. degree in electronics,
informatics, and telecommunications from the Uni-
versity of Bologna, Bologna, Italy, in 2005.
He was a Researcher involved with the ambit of
the European project TARGET. He has collaborated
as a MMIC Designer in the Italian Space Agency
(ASI) and Argentinean Space Agency (CONAE)
SAOCOM project. He is currently an MMIC De-
signer with MEC s.r.l., Bologna, Italy. His major field of study concerns the
modeling and design of MMICs for telecommunication and radar applications.
Rafael Cignani was born in Ravenna, Italy, in 1975.
He received the Laurea degree in telecommunica-
tions engineering from the University of Bologna,
Bologna, Italy, in 2000, and the Ph.D. degree in
information engineering from the University of
Ferrara, Ferrara, Italy, in 2004.
During his doctoral studies, he collaborated with
the Department of Electronics, Computer Science
and Systems (DEIS), University of Bologna. He is
currently a Graduated Technician with the DEIS,
University of Bologna. His research activity is
mainly oriented to MMIC design and nonlinear circuit modeling and design
techniques.
RESCA et al.: ACCURATE EM-BASED MODELING OF CASCODE FETs
Antonio Raffo (S’04–M’07) was born in Taranto,
Italy, in 1976. He received the M.S. degree (with
honors) in electronic engineering and Ph.D. degree
in information engineering from the University of
Ferrara, Ferrara, Italy, in 2002 and 2006, respec-
tively.
Since 2002, he has been with the Electronic De-
partment, University of Ferrara, Ferrara, Italy, where
he is currently a Contract Professor of electronic in-
strumentation and measurement. His research mainly
concerns nonlinear electron device characterization
and modeling and circuit-design techniques for nonlinear microwave and mil-
limeter-wave applications.
Dr. Raffo is a member of the Italian Association on Electrical and Electronic
Measurements.
Alberto Santarelli (M’97) received the Laurea de-
gree in electronic engineering and Ph.D. degree in
electronics and computer science from the University
of Bologna, Bologna, Italy, in 1991 and 1996, respec-
tively.
From 1996 to 2001, he was a Research Assistant
with the Research Center for Computer Science and
Communication Systems, Italian National Research
Council, Bologna, Italy. Since 2001, he has been
with the Department of Electronics, Computer
Science and Systems (DEIS), University of Bologna,
where he is currently an Associate Professor. His main research interests
are electron device nonlinear modeling and circuit design for microwave
applications.
Giorgio Vannini (S’87–M’92) received the Laurea
degree in electronic engineering and Ph.D. degree in
electronic and computer science engineering from the
University of Bologna, Bologna, Italy, in 1987 and
1992, respectively.
In 1992, he joined the Department of Electronics,
University of Bologna, as a Research Associate.
From 1994 to 1998, he was with the Research Centre
on Electronics, Computer Science and Telecommu-
nication Engineering, National Research Council
(CSITE), Bologna, Italy, where he was responsible
729
for MMIC testing and the CAD Laboratory. In 1998, he joined the University
of Ferrara, Ferrara, Italy, as an Associate Professor, and since 2005, as a
Full Professor of electronics. He is also currently Head of the Engineering
Department, University of Ferrara. During his academic career, he has been a
Teacher of applied electronics, electronics for communications, and industrial
electronics. He is a cofounder of the academic spin-off Microwave Electronics
for Communications (MEC). He has coauthored over 160 papers devoted to
electron device modeling, computer-aided design techniques for MMICs, and
nonlinear circuit analysis and design.
Dr. Vannini is a member of the Gallium Arsenide Application Symposium
(GAAS) Association. He was the recipient of the Best Paper Awards presented
at the 25th European Microwave Conference, GAAS98, and GAAS2001 con-
ferences.
Fabio Filicori received the Dr. Ing. degree in elec-
tronic engineering from the University of Bologna,
Bologna, Italy, in 1974.
In 1974, he joined the Faculty of Engineering, Uni-
versity of Bologna, as an Assistant Researcher, and
then becoming an Associate Professor. In 1990, he
became a Full Professor of electronics with the Uni-
versity of Perugia. In 1991, he rejoined the University
of Ferrara, where he was Coordinator of the degree
course in “Electronic Engineering.” He is currently a
Full Professor with the University of Bologna, where
he has been Coordinator of the Ph.D. course in “Electronics, Computer Science
and Telecommunications.” He has been the Coordinator of research projects in
electronic engineering promoted by the Ministry of University and Research.
In 2007, he became a member of the Technology Commission, Italian Space
Agency. He has authored or coauthored approximately 200 papers. His research
concerns nonlinear microwave circuit design, electron device modeling, elec-
tronic measurements, and industrial electronics.
Dr. Filicori has been a workpackage leader for the European NoE TARGET.
He has been Technical Program Committee (TPC) chairman for the EUMIC
Conference. He is a member of the Editorial Board for the IEEE TRANSACTIONS
ON MICROWAVE THEORY AND TECHNIQUES.