HCMC UNIVERSITY OF TECHNOLOGY &

EDUCATION

Assignment Front Sheet

Qualification Unit Code / Unit number and title

Pearson BTEC Level 5 HND Diploma in Electrical K/601/1362

& Electronic Engineering Unit 71: Combinational & Sequential Logic
Student name / BTEC Registration Number Assessor name

Nguyen Vu Lan

Date issued Hand in deadline Submitted on

31 Oct 2016 24 Nov 2016

Assignment 1:
Assignment title
Circuits using combinational logic
In this assessment you will have opportunities to provide evidence against the following criteria.
Indicate the page numbers where the evidence can be found.

In this assessment you Evidence

Learning Learning Assessment will have the opportunity Task
(Page
Outcome outcome Criteria to present evidence that no.
no)
shows you
Interpret are able to:
manufacturer's
data sheets to select
1.1 appropriate combinational 1c, 2
logic devices for specific
Be able to purposes
design and Compare the characteristics
build circuits 1.2 of similar devices using 1c
LO1 different technologies
using
combinational
Design, construct and test 1a, 1b,
logic 1.3 1e, 2
combinational circuits
Use computer software
1.4 package to simulate logic 1d, 2
circuits

Student declaration

I certify that the work submitted for this assignment is my own. I have clearly referenced any sources
used in the work. I understand that false declaration is a form of malpractice.

Student signature: Date:

EEE Assignment brief 2016 1

 HCMC UNIVERSITY OF TECHNOLOGY &
EDUCATION

In addition to the above PASS criteria, this assignment gives you the opportunity to
submit evidence in order to achieve the following MERIT and DISTINCTION grades

Indicative
Grade Descriptor Contextualisation
characteristic/s
M1 Identify and An effective approach to To achieve M1, select and apply suitable
apply strategies to study and research has been solution to solve given Task 1 and 2 with
find appropriate applied. clear and logical reason.
solutions

M2 Select / design Relevant theories and To achieve M2, from the data interpreted
and apply techniques have been from manufacturing data sheet choose the
appropriate applied. suitable components, state the reasons of
methods / selection clearly (Task1c)
Appropriate learning
techniques
methods/techniques have
been applied.

M3 Present and The appropriate structure and
communicate approach has been used.
appropriate
The communication is
findings
appropriate for unfamiliar
audiences and appropriate
media have been used.
D1 Use critical Conclusions have been
reflection to arrived at through synthesis
evaluate own work of ideas and have been
and justify valid justified.
conclusions
The validity of results have
been evaluated using defined
criteria.
To achieve M3,calculate voltage levels,
propagation delay, power dissipation, limit
current resistor values and compare the
values for 2 technologies(TTL and
CMOS);complete the Class work-Lab
session; clearly fill in all the data observed
during experiment and attach to assignment
(Task 1c).
To achieve D1,test the Schematic diagram
of Task 1 and 2 using simulation software,
attach the simulation results

D2 Take Autonomy / Independence To achieve D2,show good practical

responsibility for has been demonstrated understanding in solving task effectively, for
managing and given specifications, responsive in lab
organising activities

D3 Demonstrate Ideas have been generated To achieve D3,Solve task 2 with suitable
convergent / lateral and decisions taken. method for 14-segment letter display
/ creative thinking
Problems have been solved.

EEE Assignment brief 2016 2

 HCMC UNIVERSITY OF TECHNOLOGY &
EDUCATION

Assignment Brief
Pearson BTEC Level 5 HND Diploma in Electrical & Electronic
Qualification Engineering

Unit number and title Unit 71: Combinational & Sequential Logic
Assessor name Nguyen Vu Lan

Date issued 31 October 2016

Hand in deadline 24 November 2016

Assignment 1:
Assignment title
Circuits using combinational logic

Purpose of this assignment

This assignment is a combination of Practical and Theoretical exercises This assignment will
give you the opportunity to show your knowledge of basic problems of CSLcircuits. You will
come from the problem to finding out the suitable solutions, creating designs,
calculating/choosing components and simulating the designed circuits.

Scenario
You are working as a Project Engineer in “Omega Integration Pte Ltd.” You are attending a
training session arranged for the Project Engineers by your sister company “Alpha
Integrations”. After the training you have been asked by your trainer to solve the following
tasks in order to assess your level of knowledge and understanding. You are given a WiFi
equipped notebook and you can use any information you may need.

Task 1:

Design a combinational circuit satisfying the following siren at the presence of

digital input of an alarm (A):0001, 0011,0100,0101,1000, 1010 and 1101.
a) Identify the Input and Output variables and develop the truth table for
circuit
to perform the required output operations.
b) Use reduction techniques (SOP, POS or K-map) to identify a NAND
solutionwith minimum number of NAND gates. Design the circuit using only 2
inputs NAND gates.
c) Compare IC with identical function and different technologies in terms
ofvoltage levels, power dissipation, propagation delay; select more
compatibleIC, selection criteria and reason must be clearly cited in
assignment.
d) Develop the schematic diagram using Multisim or Proteus or Orcadsoftware
and testthe circuit. Indicate the observed conditions in Multisim observation
table.
e) Connect and test the Circuit using selected IC and indicate the
observedconditions in Practical observation table.

EEE Assignment brief 2016 3

 HCMC UNIVERSITY OF TECHNOLOGY &
EDUCATION

Task 2:

By using minimum number of gates, design and develop schematic circuit for
a 14-Segment LEDdisplay showingthe word “ENGINEERING”:

* For "E" : A, D, E, F, G, K on
* For "N" : B, C, E, F, H, L on
* For "G" : A, C, D, E,F, G, K on
* For "I" : I, M on
* For "R" : A, B, E, F, G, K, L on

The invalid combinations should result in a blank display. Use

suitablereduction technique to minimise the number of gates and identify
solution with minimum propagation delay (Interpret manufacturing data sheet
for minimum 02 IC technologies).Test the developed circuit using simulation
software.

Note: All Students should get lecturer sign to verify your simulation results.
Otherwise results won’t be accepted

Evidence Evidence
Summary of evidence required by student
checklist presented

 A report written in a formal style, including a

contents page indicating the different report
chapters and sections.

Task 1, 2
 Attach your simulation report and witness statement
to your results for Task 1c,Task2.

EEE Assignment brief 2016 4

 HCMC UNIVERSITY OF TECHNOLOGY &
EDUCATION

 A bibliography with references must be supplied

using the Harvard System of referencing.

 An electronic copy of your reports on either a

memory stick or CD. Label the memory stick or CD
with your name, unit title and assignment name.

Sources of information

PRESENTATION

1. The assignment should have a cover pagethat includes the assignment

title, assignment number, course title, module title, Lecturer/tutor
name and student’s name. Attach all the pages of assignment
brief/achievement summary with your report and leave them blank for
official use.

2. Ensure that authenticity declaration has been signed.

3. This is an individual assignment.

4. Content sheet with a list of all headings and page numbers.

5. A fully typed up professionally presented report document. Use 12 point

Arial or Times New Roman script.

6. Your assignment should be word-processed and should not exceed from

2,000 to 2,500 words in length.

7. Use the Harvard referencing system.

8. Exhibits/appendices are outside this limit.

9. The assignment should contain a list of any references used in the report.

NOTES TO STUDENTS FOR SUMMISSION

 Check carefully the submission date and the instructions given with the
assignment. Late assignments will not be accepted.

EEE Assignment brief 2016 5

 HCMC UNIVERSITY OF TECHNOLOGY &
EDUCATION

 Ensure that you give yourself enough time to complete the assignment by
the due date.
 Do not leave things such as printing to the last minute – excuses
of this nature will not be accepted for failure to hand-in the work
on time.
 You must take responsibility for managing your own time effectively.
 If you are unable to hand in your assignment on time and have valid
reasons such as illness, you may apply (in writing) for an extension.
 Failure to achieve a PASS grade will results in a REFERRAL grade being
given.
 Take great care that if you use other people’s work or ideas in your
assignment, you properly reference them in your text and any
bibliography.
 NOTE: If you are caught plagiarizing, the University policies and
procedures will apply.

EEE Assignment brief 2016 6

 HCMC UNIVERSITY OF TECHNOLOGY &
EDUCATION

Achievement Summary
Pearson BTEC Level 5 HND Nguyen Vu Lan
Assessor
Qualification Diploma in Electrical & Electronic
name
Engineering
Unit Number Unit 71: Combinational & Student
and title Sequential Logic name
Criteria To achieve the criteria the evidence must Achieved?
Reference show that the student is able to: (tick)
First IV
Redo
attempt check
LO 1

Interpret manufacturer's data sheets to select

1.1 appropriate combinational logic devices for specific
purposes

Compare the characteristics of similar devices using

1.2
different technologies

1.3 Design, construct and test combinational circuits

Use computer software packages to simulate logic

1.4
circuits
Higher Grade achievements (where applicable)
Achieved? Achieved?
(tick) (tick)
Grade descriptor Grade descriptor
First IV First IV
attempt check attempt check

D1: Use critical

M1: Identify and apply
reflection to evaluate
strategies to find appropriate
own work and justify
solutions
valid conclusions

M2: Select/design and apply D2: Take responsibility

appropriate for managing and
methods/techniques organising activities

D3: Demonstrate
M3: Present and communicate
convergent/lateral
appropriate findings
/creative thinking

EEE Assignment brief 2016 7

 HCMC UNIVERSITY OF TECHNOLOGY &
EDUCATION

Assignment Feedback
Formative Feedback: Assessor to Student

Action Plan

Summative feedback

Feedback: Student to Assessor

Assessor Signature Date

Student Signature Date

FOR INTERNAL USE ONLY

VERIFIED YES  NO 
DATE : ...............................................................
VERIFIED BY : ................................................................
NAME : ................................................................

EEE Assignment brief 2016 8