ECE-E434

Digital Electronics

Lecture # 5&6: CMOS Inverters

Instructor: Pouya Dianat
Oct 10 & 12 2017
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Announcements
•  HW#3 is due on Friday, Oct 21 2017.
–  Hand in your HW to your TA during the lab sessions.
•  Examples 14.6 and 14.7 for the next quiz on
Thursday Oct 19 2017
•  Facebook group for the course at:
hWps://www.facebook.com/groups/138885006748167/

Drexel University, ECEE-434 Digital Electronics
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Transistor Sizing in CMOS Inverters

For a BASIC INVERTER:
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Transistor Sizing in CMOS Logic Gates

For Logic Gates:

•  Goal: Select W/L for transistors in PUN and PDN.

•  How: The discharge current of PDN has to be equal to the charging current of PUN.
•  Why: This guarantees a worst-case gate delay equal to that of a basic inverter.
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Equivalent W/L of a network of MOSFETs

For MOSFETs connected in SERIES or in PARALLEL:

•  n MOSFETS with (W/L)1, (W/L)2, … , (W/L)n

For conneccon in SERIES For conneccon in PARALLEL

 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

The cases of a NOR and NAND gates

•  The PUN should be able to charge a load, similar to the PMOS with (W/L)p=p in a basic
inverter.
•  The PDN should be able to discharge a load, similar to the NMOS with (W/L)n=n in a basic
inverter.

Ques@on: Which design takes more area/space on the substrate?

 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Power Dissipacon
•  Sources of power dissipacon:
1.  Stacc Power Dissipacon
•  Zero for CMOS inverter
•  Non-zero for NMOS inverter
2.  Dynamic Power Dissipacon
•  Charging and discharging of the load capacitance
3.  Current flow in NMOS and PMOS during the switching transicon
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Dynamic Power Dissipacon

•  In each cycle of the inverter:
•  (½)CVDD2 is dissipated in the pull-up + (½)CVDD2 is dissipated in the pull-down
•  Therefore the total energy dissipacon per cycle is:

•  In the inverter is switched at a frequency f Hz, then, the total dynamic power dissipated is:

•  Observacons:
•  Smaller C would result in smaller dynamic power dissipacon; is that feasible?
•  Smaller VDD reduces power dissipacon
•  Smaller f reduces power dissipacon; is that desirable?
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Power Dissipacon due to transicon current

•  The width of this pulse depends on
how fast vI switches.
•  It is generally much smaller than
Pdyn, therefore typically ignored.
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Power-Delay Product

High-speed operacon (short delay, tP) Lower Power Dissipacon

These two do not get along!!

The lower PDP, the beNer!

For CMOS inverter:
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Energy-Delay Product
•  PDP is valuable for comparing different inverter technologies.
•  PDP is not useful to opcmize a given inverter as a design parameter
•  PDP does not include informacon about tP à It basically implies that for lower PDP VDD
should be reduced and disregards the cme delay.
 ECE-E434
Digital Electronics
CMOS Logic Circuits – Ch. 14

Summary of CMOS Inverter