Advance STA Concept:

Onchip Variation (OCV)

Static timing analysis of a design is performed to estimate its working frequency after the design has been
fabricated. Nominal delays of the logic gates as per characterization are calculated and some pessimism
is applied above that to see if there will be any setup and/or hold violation at the target frequency.
However, all the transistors manufactured are not alike. Also, not all the transistors receive the same
voltage and are at same temperature. The characterized delay is just the delay of which there is
maximum probability. The delay variation of a typical sample of transistors on silicon follows the curve as
shown in figure 1. As is shown, most of the transistors have nominal characteristics. Typically, timing
signoff is carried out with some margin. By doing this, the designer is trying to ensure that more number
of transistors are covered. There is direct relationship between the margin and yield. Greater the margin
taken, larger is the yield. However, after a certain point, there is not much increase in yield by increasing
margins. In that case, it adds more cost to the designer than it saves by increase in yield. Therefore,
margins should be applied so as to give maximum profits.

Number of transistors v/s delay for a typical silicon transistors sample

We have discussed above how variations in characteristics of transistors are taken care of in STA. These
variations in transistors’ characteristics on as fabricated on silicon are known as OCV (On-Chip
Variations). The reason for OCV, as discussed above also, is that all transistors on-chip are not alike in
geometry, in their surroundings, and position with respect to power supply. The variations are mainly
caused by three factors:

Process variations: The process of fabrication includes diffusion, drawing out of metal wires, gate drawing
etc. The diffusion density is not uniform throughout wafer. Also, the width of metal wire is not constant.
Let us say, the width is 1um +- 20 nm. So, the metal delays are bound to be within a range rather than a
single value. Similarly, diffusion regions for all transistors will not have exactly same diffusion
concentrations. So, all transistors are expected to have somewhat different characteristics.
Voltage variation: Power is distributed to all transistors on the chip with the help of a power grid. The
power grid has its own resistance and capacitance. So, there is voltage drop along the power grid. Those
transistors situated close to power source (or those having lesser resistive paths from power source)
receive larger voltage as compared to other transistors. That is why, there is variation seen across
transistors for delay.
Temperature variation: Similarly, all the transistors on the same chip cannot have same temperature. So,
there are variations in characteristics due to variation in temperatures across the chip.

How to take care of OCV: To tackle OCV, the STA for the design is closed with some margins. There
are various margining methodologies available. One of these is applying a flat margin over whole
design. However, this is over pessimistic since some cells may be more prone to variations than
others. Another approach is applying cell based margins based on silicon data as what cells are
more prone to variations. There also exist methodologies based on different theories e.g. location
based margins and statistically calculated margins. As advances are happening in STA, more
accurate and faster discoveries are coming into existence.
Advance Onchip Variation
What is Advanced OCV -

AOCV uses intelligent techniques for context specific derating instead of a single global derate value,
thus reducing the excessive design margins and leading to fewer timing violations. This represents a
more realistic and practical method of margining, alleviating the concerns of overdesign, reduced design
performance, and longer timing closure cycles.

Advanced OCV determines derate values as a function of logic depth and/or cell, and net location. These
two variables provide further granularity to the margining methodology by determining how much a
specific path in a design is impacted by the process variation.

There are two kinds of variations.

1) Random Variation
2) Systematic Variation

Random Variation-
Random variation is proportional to the logic depth of each path being analyzed.
The random component of variation occurs from lot-to-lot, wafer-to-wafer, on-die and die-to-die.
Examples random variation are variations in gate-oxide thickness, implant doses, and metal or dielectric
thickness.
Systematic Variation-
Systematic variation is proportional to the cell location of the path being analyzed.

The systematic component of variation is predicted from the location on the wafer or the nature of the
surrounding patterns. These variations relate to proximity effects, density effects, and the relative
distance of devices. Examples of systematic variation are variations in gate length or width and
interconnect width.

Take the example of random variation, given the buffer chain shown in Figure 1, with nominal cell delay of
20, nominal path delay @ stage N = N * 20. In a traditional OCV approach, timing derates are applied to
scale the path delay by a fixed percentage, set_timing_derate –late 1.2;set_timing_derate –early 0.8
 Statistical analysis shows that the random variation is less for deeper timing paths and not all
cells are simultaneously fast or slow. Using statistical HSPICE models, Monte-Carlo analysis can be
performed to measure the accurate delay variation at each stage. Advanced OCV derate factors can then
be computed as a function of cell depth to apply accurate, less pessimistic margins to the path.

Figure 2a shows an example of how PrimeTime Advanced OCV would determine the path depth for both
launch and capture. These values index the derate table, as shown in Figure 7, to select the appropriate
derate values.

Fig 2a-Depth Based Advanced OCV

Effects of systematic variation shows that paths comprised of cells in close proximity exhibit less variation
relative to one another. Using silicon data from test-chips, Advanced OCV derate factors based on
relative cell-location are then applied to further improve accuracy and reduce pessimism on the path.
Advanced OCV computes the length of the diagonal of the bounding box, as shown in Figure 2b, to select
the appropriate derate value from the table.
PrimeTime Advanced OCV Flow -
PrimeTime internally computes depth and distance metrics for every cell arc and net arc
in the design. It picks the conservative values of depth and distance thus bounding the
worst-case path through a cell.