Multilevel Multiphase Space Vector PWM

Algorithm With Switching State Redundancy

Applied to Three-Phase Converters
Óscar López, Jacobo Álvarez, Francisco D. Freijedo, Alejandro G. Yepes, Pablo Fernández-Comesaña,
Jano Malvar, Jesús Doval-Gandoy, Andrés Nogueiras, Alfonso Lago and Carlos M. Peñalver

Electronics Technology Department

University of Vigo
Vigo, Spain ES-36210
Email: olopez@uvigo.es

Abstract—This paper presents the particularization of a re-
cent multilevel multiphase space vector pulse-width modulation
algorithm for three-phase converters. This modulation technique
takes advantage of the switching state redundancy, which permits
to achieve different goals like extending the modulation index
range and reducing the number of switchings. The particularized
algorithm is then compared with an existing multilevel space
vector modulation technique showing many similarities. Finally,
the algorithm is implemented in a low cost FPGA and it is tested
in laboratory with a real prototype by using a neutral point
clamped inverter.
I. I NTRODUCTION
The space vector pulse-width modulation (SVPWM) is a
very common modulation technique that is still in focus of the
research community attention [1]–[5] because it offers a great
flexibility to optimize the switching waveforms. This technique
represents the reference voltage and the switching states of
the converter in a vectorial space. In this space, the reference
vector is approximated by means of a sequence of switching
vectors. Complexity and computational cost of traditional mul-
tilevel SVPWM techniques increase with the number of levels
of the converter, and most of them use trigonometric functions
or precomputed tables [6], [7]. In the two-dimensional (2D)
and the three-dimensional (3D) SVPWM algorithms proposed
in [8] and [9], respectively, the calculation of the switching
vectors and the switching times is reduced to a few comparison
and addition operations, which do not depend on the number
of levels. Consequently, those multilevel techniques are very
suitable for real-time implementation [10].
Recently, in [11] and [12], two new multiphase SVPWM
techniques with low computational complexity, which makes
them suitable for on-line implementation using low-cost de-
vices, were presented. Both techniques can be used with the
typical multilevel topologies such as diode-clamped, flying
capacitor, cascaded full-bridge or even hybrid converters. The
modulation technique of [11] is suitable for converters with
neutral wire. In the case of converters with floating neutral,
this algorithm shows a poor performance because it does
not take into account the switching state redundancy. The
modulation technique of [12] takes advantage of redundancy,
which allows extending the linear region of the modulation
index, reducing the number of switchings, and balancing
capacitors in multilevel converters.
Those two multiphase SVPWM algorithms are valid for any
number of phases and consequently they can be applied to
the standard three-phase converters. In [13], the multiphase
algorithm in [11] was particularized to three-phase converters,
and it was shown that in this case the obtained algorithm
is nearly the same as the former generalized 3D SVPWM
algorithm presented in [9]. In this paper, the multilevel mul-
tiphase SVPWM algorithm with switching state redundancy
in [12] is particularized for three-phase converters. The re-
sulting algorithm is compared with the fast 2D SVPWM
technique presented in [8]. Finally, it is implemented in a
field-programmable gate array (FPGA) and it is tested with
a neutral-point clamped (NPC) inverter feeding and induction
motor.
II. M ULTILEVEL M ULTIPHASE SVPWM A LGORITHM
W ITH S WITCHING S TATE R EDUNDANCY
In multiphase converters the SVPWM is a multidimensional
problem where the vector selection can be carried out directly
in a multidimensional space. In [12], the modulation problem
of a 𝑃 -phase converter is formulated in a 𝑃 -dimensional
space and it is solved for multilevel topologies in which
the output level of every phase is an integer multiple of
a fixed voltage step 𝑉dc . Flying capacitor, diode-clamped,
cascaded full-bridge and hybrid converters are included in such
topologies. The solution is an algorithm based on a two-level
multiphase SVPWM modulator that is valid for any number
of levels and phases. This multiphase modulation technique
is able to handle all switching states of the inverter, without
discard any one, and it provides a sorted switching vector
sequence that minimizes the number of switchings. In addition,
the algorithm proves suitable for real-time implementation due
to its low computational complexity.

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 Since the switching states of any power converter topology triangular matrix made with ones. The dwell times are
stay at discrete states, the SVPWM technique is used to syn- calculated as
thesize a reference voltage vector v𝑟 = [𝑣𝑟 1 , 𝑣𝑟 2 , . . . , 𝑣𝑟 𝑃 ]T
⎧
⎨1 − 𝜔
 ˆ𝑓 1, if 𝑗 = 1
by means of a sequence of several switching vectors 𝑗−1 𝑗
𝜏𝑗 = 𝜔 ˆ𝑓 − 𝑣ˆ𝑓 , if 2 ≤ 𝑗 ≤ 𝑃 (9)
v𝑠𝑗 = [𝑣𝑠 1𝑗 , 𝑣𝑠 2𝑗 , . . . , 𝑣𝑠 𝑃 T
𝑗 ] during the modulation cycle. Each ⎩ 𝑃

switching vector must be applied during an interval 𝑡𝑗 in 𝜔ˆ𝑓 , if 𝑗 = 𝑃 + 1
accordance with the following modulation law where 𝜔 ˆ 𝑓 𝑘 are the components of the vector that results
𝑃
∑ +1 𝑃
∑ +1 of sorting the vector 𝝎 𝑓 .
𝝎𝑟 = 𝝎 𝑠𝑗 𝑡𝑗 , 𝑡𝑗 = 1 (1) 5) From the integer part, obtain the value of 𝑞𝑖 as
𝑗=1 𝑗=1 𝑃 −1
∑
1 2
where 𝝎 𝑟 = [𝜔𝑟 , 𝜔𝑟 , . . . , 𝜔𝑟 𝑃 −1 T
] is the reference space 𝑞𝑖 = 𝜔𝑖 𝑘 . (10)
vector that corresponds to the reference vector v𝑟 , and 𝝎 𝑠𝑗 = 𝑘=1
[𝜔𝑠 1 , 𝜔𝑠 2 , . . . , 𝜔𝑠 𝑃 −1 ]T are the space vectors that correspond 6) Calculate the intervals [𝑞min 𝑘 , 𝑞max 𝑘 ] that correspond to
to the switching vectors v𝑠𝑗 . each phase 𝑘 by means of
The modulation problem in (1) is solved in [12] by an
algorithm with the following steps: 𝑞min 𝑘 = Δ𝑞 𝑘 + 𝑁min 𝑘 𝑃 (11)
𝑘 𝑘 𝑘
1) Normalize the reference vector respect to the voltage 𝑞max = Δ𝑞 + 𝑁max 𝑃 + (𝑃 − 1) (12)
step of the multilevel converter 𝑉dc : 𝑘 𝑘
where 𝑁min and 𝑁max are the minimum and maxi-
V𝑟 mum levels available in the phase 𝑘 of the inverter, and
v𝑟 = . (2)
𝑉dc { ∑𝑃
𝑘 𝑞𝑖 − 𝜔𝑖 𝑘 𝑃 − 𝑗=1 𝜔𝑑 𝑘𝑗 if 𝑘 < 𝑃
2) Calculate the reference space vector 𝝎 𝑟 from v𝑟 by Δ𝑞 = (13)
𝑞𝑖 if 𝑘 = 𝑃.
using the expression
7) Determine the bounding indices 𝑞min and 𝑞max by using
𝝎 𝑟 = T𝝎 v𝑟 . (3)
expressions
where T𝝎 is the following (𝑃 − 1) × 𝑃 matrix 𝑞min = max(𝑞min 1 , 𝑞min 2 , . . . , 𝑞min 𝑃 ) (14)
⎡ ⎤
1 2 𝑃
1 0 . . . 0 −1 𝑞max = min(𝑞max , 𝑞max , . . . , 𝑞max ). (15)
⎢ ⎥
⎢0 1 . . . 0 −1⎥ 8) Test if the reference does not lie in the overmodulation
T𝝎 = ⎢ . . . (4)
⎢ ⎥
⎢ .. .. .. .. .. ⎥ region with the condition
⎣ . . . ⎥
⎦
0 0 . . . 1 −1 𝑞max − 𝑞min + 1 ≥ 𝑃. (16)

3) Decompose the reference space vector into the sum of 9) Select 𝑃 consecutive integer numbers {𝑞𝑚 } within the
its integer part 𝝎 𝑖 and its fractional part 𝝎 𝑓 : interval [𝑞max , 𝑞min ] according to any desired modula-
tion strategy.
𝝎 𝑖 = integ(𝝎 𝑟 ) (5) 10) Calculate the values of 𝑛𝑚 and 𝑗𝑚 that correspond to
𝝎𝑓 = 𝝎𝑟 − 𝝎𝑖 . (6) each selected index 𝑞𝑚 by means of
( )
4) From the fractional part, obtain the sequence of dis- 𝑞𝑚 − 𝑞𝑖
𝑛𝑚 = integ (17)
placed space vectors 𝝎 𝑑𝑗 = [𝜔𝑑 1 , 𝜔𝑑 2 , . . . , 𝜔𝑑 𝑃 −1 ]T 𝑃
and their dwell times 𝜏𝑗 by means of the two-level 𝑗𝑚 = 𝑞𝑚 − 𝑞𝑖 − 𝑛𝑚 𝑃 + 1. (18)
multiphase SVPWM in [11]. The displaced space vector
11) Obtain the vectors of the switching sequence {v𝑠𝑚 } and
sequence is extracted from the matrix
⎡ ⎤ their switching times {𝑡𝑚 } by means of
1 1 ... 1 v𝑠𝑚 = Tv (𝝎 𝑖 + 𝝎 𝑑𝑗 ) + 𝑛𝑚 [1, 1, . . . , 1]T (19)
⎢ 1
⎢ 𝜔𝑑 1 𝜔𝑑 12 . . . 𝜔𝑑 1𝑃 +1 ⎥
⎥
⎢ ⎥ 𝑡𝑚 = 𝜏𝑗𝑚 , (20)
⎢ 2 2 2
D = ⎢ 𝜔𝑑 1 𝜔𝑑 2 . . . 𝜔𝑑 𝑃 +1 ⎥ (7)
⎥
⎢ . respectively, where Tv is the following 𝑃 × (𝑃 − 1)
⎢ . .. .. .. ⎥
⎣ . . . . ⎦
⎥ transformation matrix:
⎡ ⎤
𝜔𝑑 𝑃
1 𝜔𝑑 𝑃
2 ... 𝜔𝑑 𝑃
𝑃 +1 1 0 ... 0
⎢0 1 ... 0⎥
⎢ ⎥
that is calculated as
⎢. .. .. ⎥
⎢ ⎥
Tv = ⎢ .. .. . (21)
D = PT D̂ (8) ⎢ . . .⎥⎥
⎣0 0 ... 1⎦
⎢ ⎥
where P is the permutation matrix that sorts the com-
ponents of 𝝎 𝑓 in descending order and D̂ is a upper 0 0 ... 0

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 TABLE I
Finally, the trigger signals of transistors are generated from P ERMUTATION MATRIX .
these switching vectors and switching times. The relationship
between them depends on the multilevel topology [14]. 𝐶𝑎𝑏 Ordered vector 𝝎
ˆ𝑓 Matrix P
⎡ ⎤
III. A PPLICATION TO T HREE -P HASE C ONVERTERS 𝑎 𝑏
1 0 0
𝜔
ˆ 𝑓 = 𝜔𝑓
0 ⎣0 0 1⎦
⎢ ⎥
The SVPWM algorithm for three-phase systems is obtained ˆ 𝑓 𝑏 = 𝜔𝑓 𝑎
𝜔
0 1 0
making 𝑃 = 3 in the multiphase algorithm. Therefore, in ⎡ ⎤
three-phase converters, the modulation problem is formulated 1 0 0
ˆ 𝑓 𝑎 = 𝜔𝑓 𝑎
𝜔
1 ⎣0 1 0⎦
⎢ ⎥
in a 3D space and the switching states are 3D integer vectors: ˆ 𝑓 𝑏 = 𝜔𝑓 𝑏
𝜔
0 0 1
v𝑠 = [𝑣𝑠 𝑎 , 𝑣𝑠 𝑏 , 𝑣𝑠 𝑐 ]T ∈ ℤ3 . (22)
The normalized voltage reference v𝑟 , calculated by means of TABLE II
D ISPLACED SPACE VECTOR SEQUENCE AND DWELL TIMES .
(2), is the 3D real vector:
V𝑟 𝐶𝑎𝑏 Displaced space vector sequence 𝝎 𝑠𝑗 Dwell times 𝜏𝑗
v𝑟 = = [𝑣𝑟 𝑎 , 𝑣𝑟 𝑏 , 𝑣𝑟 𝑐 ]T ∈ ℝ3 . (23)
𝑉dc 𝝎 𝑑1 = [0, 0]T 𝜏1 = 1 − 𝜔𝑓 𝑏
0 𝝎 𝑑2 = [0, 1]T 𝜏2 = 𝜔𝑓 𝑏 − 𝜔𝑓 𝑎
The reference space vector 𝝎 𝑟 = [𝜔𝑟 𝑎 , 𝜔𝑟 𝑏 ]T that corresponds
𝝎 𝑑3 = [1, 1]T 𝜏3 = 𝜔 𝑓 𝑎
to v𝑟 is a 2D vector that can be calculated from (3) as
𝝎 𝑑1 = [0, 0]T 𝜏1 = 1 − 𝜔𝑓 𝑎
𝝎 𝑟 = T𝝎 v𝑟 ∈ ℝ2 (24) 1 𝝎 𝑑2 = [1, 0]T 𝜏2 = 𝜔 𝑓 𝑎 − 𝜔 𝑓 𝑏
where the transformation matrix T𝝎 is 𝝎 𝑑3 = [1, 1]T 𝜏3 = 𝜔 𝑓 𝑏
[ ]
1 0 −1
T𝝎 = . (25)
0 1 −1 The dwell time corresponding to each displaced space vector
is calculated by means of (9) as
Hence, the components of the reference space vector can be
easily calculated from the reference vectors as ˆ𝑓 𝑎
𝜏1 = 1 − 𝜔
𝜔𝑟 𝑎 = 𝑣𝑟 𝑎 − 𝑣𝑟 𝑐 ˆ𝑓 𝑎 − 𝜔
𝜏2 = 𝜔 ˆ𝑓 𝑏 (32)
(26) 𝜏3 = 𝜔
ˆ𝑓 . 𝑏
𝜔𝑟 𝑏 = 𝑣𝑟 𝑏 − 𝑣𝑟 𝑐 .
In accordance with (5) and (6), the integer and fractional parts If the two-level modulation problem is solved in the two cases
of the reference space vector are in Table I then the results shown in Table II are obtained.
The value of 𝑞𝑖 is obtained from the integer part of the
𝝎 𝑖 = integ(𝝎 𝑟 ) = [𝜔𝑖 𝑎 , 𝜔𝑖 𝑏 ]T ∈ ℤ2 (27) reference space vector 𝝎 𝑖 by means of expression in (10) as
𝑎 𝑏 T 2
𝝎 𝑓 = 𝝎 𝑟 − 𝝎 𝑖 = [𝜔𝑓 , 𝜔𝑓 ] ∈ ℝ . (28)
𝑞𝑖 = 𝜔𝑖 𝑎 + 𝜔𝑖 𝑏 . (33)
The displaced space vectors 𝝎 𝑑1 = [𝜔𝑑 𝑎1 , 𝜔𝑑 𝑏1 ]T ,
𝝎 𝑑2 =
The intervals [𝑞min 𝑎 , 𝑞max 𝑎 ], [𝑞min 𝑏 , 𝑞max 𝑏 ] and [𝑞min 𝑐 , 𝑞max 𝑐 ]
[𝜔𝑑 𝑎2 , 𝜔𝑑 𝑏2 ]T and 𝝎 𝑑3 = [𝜔𝑑 𝑎3 , 𝜔𝑑 𝑏3 ]T that approximate the
that correspond to every phase are calculated by means of (11)
fractional part of the reference space vector 𝝎 𝑓 are obtained
and (12) as
by means of the two-level 2D SVPWM algorithm developed
in [11]. Its application requires calculating a permutation [𝑞min 𝑎 , 𝑞max 𝑎 ] = [Δ𝑞 𝑎 + 3𝑁min 𝑎 , Δ𝑞 𝑎 + 3𝑁max 𝑎 + 2]
matrix P that sorts the components of vector 𝝎 𝑓 . Such matrix [𝑞min 𝑏 , 𝑞max 𝑏 ] = [Δ𝑞 𝑏 + 3𝑁min 𝑏 , Δ𝑞 𝑏 + 3𝑁max 𝑏 + 2] (34)
can be determined by testing the following logical condition:
[𝑞min 𝑐 , 𝑞max 𝑐 ] = [Δ𝑞 𝑐 + 3𝑁min 𝑐 , Δ𝑞 𝑐 + 3𝑁max 𝑐 + 2]
𝑎 𝑏
𝐶𝑎𝑏 = [𝜔𝑓 ≥ 𝜔𝑓 ]. (29)
where the values of Δ𝑞 𝑘 are calculated from (13) taking into
Relationships between the result of this condition and the account the values of 𝝎 𝑑1 and 𝝎 𝑑3 in Table II:
permutation matrix P are shown in Table I. Next, by means Δ𝑞 𝑎 = 𝑞𝑖 − 3𝜔𝑖 𝑎 − 𝜔𝑑 𝑎2 − 1
of (8), the matrix D is calculated as
⎡ ⎤ Δ𝑞 𝑏 = 𝑞𝑖 − 3𝜔𝑖 𝑏 − 𝜔𝑑 𝑏2 − 1 (35)
1 1 1 Δ𝑞 𝑐 = 𝑞𝑖 .
D = PT ⎢
⎢ ⎥
⎣0 1 1⎦
⎥ (30)
The bounding indices 𝑞min and 𝑞max are determined by using
0 0 1 expressions in (14) and (15), respectively, as
and the sequence of displaced space vectors {𝝎 𝑑1 , 𝝎 𝑑2 , 𝝎 𝑑3 } 𝑞min = max(𝑞min 𝑎 , 𝑞min 𝑏 , 𝑞min 𝑐 ) (36)
is extracted from it taking into account that 𝑎 𝑏
𝑞max = min(𝑞max , 𝑞max , 𝑞max ). 𝑐
(37)
⎡ ⎤
1 1 1 By means of the condition given in (16) it can be tested if the
⎢ ⎥
D=⎢ 𝑎 𝑎 𝑎⎥
⎣𝜔𝑑 1 𝜔𝑑 2 𝜔𝑑 3 ⎦ . (31) reference does not lie in the overmodulation region
𝜔𝑑 𝑏1 𝜔𝑑 𝑏2 𝜔𝑑 𝑏3 𝑞max − 𝑞min ≥ 2. (38)

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The next step is to choose three consecutive integer numbers If a five-level cascaded full-bridge inverter is considered then
{𝑞1 , 𝑞2 , 𝑞3 } within the interval [𝑞min , 𝑞max ] according to any 𝑁min 𝑎 = 𝑁min 𝑏 = 𝑁min 𝑐 = −2 and 𝑁max 𝑎 = 𝑁max 𝑏 =
desired modulation strategy. The selection has influence on 𝑁max 𝑐 = 2. In this case, from (34), the intervals of indices
the capacitor balancing in diode-clamped and flying capacitor that corresponding to each phase are
converters or in the power sharing of dc sources in cascaded
[𝑞min 𝑎 , 𝑞max 𝑎 ] = [−9, 5]
full-bridge converters. The values of 𝑛1 , 𝑛2 and 𝑛3 that
correspond to selected indices are calculated from (17) as [𝑞min 𝑏 , 𝑞max 𝑏 ] = [−1, 13] (49)
𝑐 𝑐
(
𝑞1 − 𝑞𝑖
) [𝑞min , 𝑞max ] = [−11, 3].
𝑛1 = integ
3 Consequently, from (36) and (37), the range of the indices that
( )
𝑞2 − 𝑞𝑖 corresponding to all phases is
𝑛2 = integ (39)
3
( ) [𝑞min , 𝑞max ] = [−1, 3]. (50)
𝑞3 − 𝑞𝑖
𝑛3 = integ Testing the condition in (38), 𝑞max −𝑞min ≥ 2, it is verified that
3
the reference vector does not lie in the overmodulation region
and the values of 𝑗1 , 𝑗2 and 𝑗3 by means of (18) as
and it can be accurately synthesized. Among all available
𝑗1 = 𝑞1 − 𝑞𝑖 − 3𝑛1 + 1 possibilities, the following three first indices within the range
𝑗2 = 𝑞2 − 𝑞𝑖 − 3𝑛2 + 1 (40) have been selected:
𝑗3 = 𝑞3 − 𝑞𝑖 − 3𝑛3 + 1. {𝑞1 , 𝑞2 , 𝑞3 } = {−1, 0, 1}. (51)
Finally, the switching vector sequence is calculated from the
The values of 𝑛𝑚 and 𝑗𝑚 that correspond to these 𝑞𝑚 indices
expressions in (19) as
can be calculated by means of (39) and (40) as
v𝑠1 = [𝜔𝑖 𝑎 + 𝜔𝑑 𝑎𝑗1 + 𝑛1 , 𝜔𝑖 𝑏 + 𝜔𝑑 𝑏𝑗1 + 𝑛1 , 𝑛1 ]T
𝑛1 = 1, 𝑛2 = 1, 𝑛3 = 2,
v𝑠2 = [𝜔𝑖 𝑎 + 𝜔𝑑 𝑎𝑗2 + 𝑛2 , 𝜔𝑖 𝑏 + 𝜔𝑑 𝑏𝑗2 + 𝑛2 , 𝑛2 ]T (41) (52)
𝑗1 = 2, 𝑗2 = 3, 𝑗3 = 1.
v𝑠3 = [𝜔𝑖 𝑎 + 𝜔𝑑 𝑎𝑗3 + 𝑛3 , 𝜔𝑖 𝑏 + 𝜔𝑑 𝑏𝑗3 + 𝑛3 , 𝑛3 ]T
Finally, the following switching vector sequence
and the corresponding switching times by means of (20) as
v𝑠1 = v𝑠 (𝑛1 , 𝑗1 ) = [0, −2, 1]T
𝑡1 = 𝜏𝑗1
v𝑠2 = v𝑠 (𝑛2 , 𝑗2 ) = [1, −2, 1]T (53)
𝑡2 = 𝜏𝑗2 (42) T
v𝑠3 = v𝑠 (𝑛3 , 𝑗3 ) = [1, −2, 2] .
𝑡3 = 𝜏𝑗3 .
together with their corresponding switching times
The simplicity of the new 2D SVPWM algorithm is shown
by means of an example. Let us consider the normalized 𝑡1 = 𝜏2 = 0.55
reference vector v𝑟 = [0.59, −1.86, 1.27]T . In this case, the 𝑡2 = 𝜏3 = 0.32 (54)
reference space vector, calculated by means of (26), is the
𝑡3 = 𝜏1 = 0.13.
following 2D vector:
are obtained by means of (41) and (42), respectively. It is im-
𝝎 𝑟 = [𝑣𝑟 𝑎 − 𝑣𝑟 𝑐 , 𝑣𝑟 𝑏 − 𝑣𝑟 𝑐 ]T = [−0.68, −3.13]T . (43)
portant to remark that consecutive vectors of the sequence are
In accordance with (27) and (28), the integer and fractional adjacent. Therefore, the number of switchings is minimized.
parts of the reference space vector are
IV. C OMPARISON W ITH E XISTING 2D A LGORITHM
𝝎 𝑖 = integ(𝝎 𝑟 ) = [−1, −4]T (44)
The fast multilevel SVPWM algorithm for multilevel three-
𝝎 𝑓 = 𝝎 𝑟 − 𝝎 𝑖 = [0.32, 0.87]T . (45) phase converters presented in [8] is a 2D modulation technique
Since the condition in (29) is false that uses the following transformation to represent the refer-
ence and the switching vectors in the 𝑔ℎ space:
𝐶𝑎𝑏 = [𝜔𝑓 𝑎 ≥ 𝜔𝑓 𝑏 ] = 0 (46) ⎡ ⎤
[ ] [ ] 𝑣𝑎 − 𝑣𝑏
𝑔
then the displaced space vector sequence and the correspond- 𝑣 1 2 −1 −1 ⎢ ⎥
⎢𝑣𝑏 − 𝑣𝑐 ⎥ .
= (55)
ing dwell times provided by Table II are: 𝑣 ℎ 3 −1 2 −1 ⎣ ⎦
𝑐 𝑎
𝑣 −𝑣
𝝎 𝑑1 = [0, 0]T → 𝜏1 = 1 − 𝜔𝑓 𝑏 = 0.13
𝝎 𝑑2 = [0, 1]T → 𝜏2 = 𝜔𝑓 𝑏 − 𝜔𝑓 𝑎 = 0.55 (47) The above expression can be rewritten as
𝝎 𝑑3 = [1, 1]T 𝜏3 = 𝜔𝑓 𝑎 = 0.32.
⎡ ⎤
→ [ ] [ ] 𝑣𝑎
𝑔
𝑣 1 −1 0 ⎢ ⎥
The value of the index 𝑞𝑖 is calculated by means of (33) as = ⎢𝑣𝑏 ⎥ , (56)
ℎ
𝑣 0 1 −1 ⎣ ⎦
𝑎 𝑏
𝑞𝑖 = 𝜔𝑖 + 𝜔𝑖 = −5. (48) 𝑣𝑐

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which is very similar to the transformation in (24) used by
the new 2D SVPWM algorithm. Once in the 𝑔ℎ space, the
fast multilevel SVPWM algorithm searches the three space
Normalized reference voltage
vectors nearest to the reference vector. This is done by means 2
a
of a comparison operation following a similar procedure as

Voltage (p.u.)
1
in (29). Dwell times corresponding to the three nearest space b
vector are obtained from the fractional parts of the reference 0

space vector as in (32). Consequently, both algorithms have −1

a similar computational cost to calculate space vectors and c
−2
dwell times. 0 0.5 1
The application of the fast multilevel SVPWM algorithm to New 2D SVPWM algorithm
the reference vector v𝑟 = [0.59, −1.86, 1.27]T , considered in 4

Space vector sequence

the previous example provides the following results: 2
Vh

[𝑣𝑠 𝑔1 , 𝑣𝑠 ℎ1 ]T = [2, −3] T

→ 𝜏1 = 0.13 0

[𝑣𝑠 𝑔2 , 𝑣𝑠 ℎ2 ]T = [3, −4] T

→ 𝜏3 = 0.32 (57) −2
Vg
[𝑣𝑠 𝑔3 , 𝑣𝑠 ℎ3 ]T = [3, −3]T → 𝜏2 = 0.55. −4
0 0.5 1
If the vectors of the switching sequence in (53), which have
Fast multilevel 2D SVPWM algorithm
been obtained with the new 2D SVPWM algorithm, are 4

Space vector sequence

transformed by means of (55) then the following space vectors Vh
2
in the 𝑔ℎ frame are obtained
0
v𝑠1 : [𝑣𝑠 𝑔1 , 𝑣𝑠 ℎ1 ]T = [2, −3]T → 𝜏1 = 0.13
−2
v𝑠2 : [𝑣𝑠 𝑔2 , 𝑣𝑠 ℎ2 ]T = [3, −3]T → 𝜏2 = 0.55 (58) Vg

−4
v𝑠3 : [𝑣𝑠 𝑔3 , 𝑣𝑠 ℎ3 ]T = [3, −3]T → 𝜏3 = 0.32. 0 0.5 1

Above vectors are the same as the previous ones, except for Difference between both algoritms
1
the way in which they are sorted. Fig. 1 shows that if space Error g
vectors of the fast multilevel SVPWM in [8] algorithm are 0.5 Error h
Diff. (%)

properly sorted then the result obtained with both modulation 0

techniques in the 𝑔ℎ frame is the same.
−0.5
The fast multilevel SVPWM algorithm provides an unsorted
space vector sequence and it does not include an efficient −1
0 0.5 1
method to obtain the switching vector sequence from space Time (p.u.)
vectors. Consequently, the new 2D SVPWM algorithm can be
considered as an extension of the fast algorithm that includes Fig. 1. 2D algorithms comparison in the 𝑔ℎ space.
such features.
V. H ARDWARE IMPLEMENTATION
The new 2D SVPWM algorithm was described for a three-
level inverter by using very-high-speed integrated circuit hard-
ware description language (VHDL) and it was implemented
TABLE III
in a Digilent S3 board. This board hosts a XC3S200 FPGA R ESOURCES SUMMARY
from Xilinx, which has 4.320 logic cells, each one constituted
by two 16 × 1 lookup tables and two flip-flops. This FPGA Target Device : xc3s200
Number of Slice Flip Flops: 2,057 out of 3,840 53%
also has twelve 18 × 18 hardware multipliers and twelve Number of 4 input LUTs: 2,439 out of 3,840 63%
18 kb block random access memories (BRAMs). Table III Number of occupied Slices: 1,563 out of 1,920 81%
shows a summary of the resources used by the implementation. Total Number 4 input LUTs: 2,231 out of 3,840 58%
Number of bonded IOBs: 63 out of 173 36%
Neither BRAMs or the multipliers available in the FPGA were IOB Flip Flops: 39
used because the algorithm does not need data storage or Number of Block RAMs: 0 out of 12 0%
multiplication operations. Number of MULT18X18s: 0 out of 12 0%
Number of GCLKs: 8 out of 8 100%
Fig. 2 shows the FPGA output waveforms that correspond Number of Startups: 1 out of 1 100%
to the trigger signals in the case v𝑟 = [−0.16, 0.52, −0.77]T . Total equivalent gate count for design: 31,063
The new algorithm was tested with a three-level NPC in-
verter driving a star connected induction motor. A 220/380 V,
1.420 r/min, 1.35 kW rated motor was used. Fig. 3 shows the

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Phase a: 1 1 1 1 1 Optical
Phase b: 1 2 2 2 1
Phase c: 0 0 1 0 0
Fig. 2. Trigger signals.
experimental setup used in tests. It includes the converter, the
FPGA and a personal computer with a DSPACE DS1103 PPC
Controller Board. A reference voltage with 50 Hz fundamental
frequency and a 10 kHz output switching frequency were
considered. Fig. 4 shows the inverter output leg voltage, and
the low-order voltage harmonics, in the case of balanced
sinusoidal reference and the maximum modulation index
(𝑚 = 1.15). The SVPWM algorithm injects an homopolar
component in the leg voltage (channels one and two of the
oscilloscope) as Fig. 4a shows. This homopolar component is
the voltage of the neutral point of the load 𝑉𝑛 that is shown in
channel three. The hompolar component has no influence on
the phase-to-phase voltage shown in Fig. 4b. It is a sinusoidal
wave with negligible low order harmonics and a very low total
harmonic distortion (THD).
VI. C ONCLUSION
In this paper the recent SVPWM algorithm for multilevel
multiphase converters that takes into account the switching
state redundancy is particularized for three-phase systems.
The particularized algorithm is a 2D SVPWM algorithm that
provides a sorted switching vector sequence, which minimizes
the number of switchings. It can be used with the standard
multilevel topologies with any number of levels. It is suitable
for real-time implementation due to its low computational
complexity. The three-level version of this algorithm was
implemented in a low-cost FPGA and it was successfully
tested by using a NPC inverter.
The new 2D algorithm can be considered as an extension
of a previous fast 2D algorithm in which the problem of the
redundant switching state selection has been solved.
ACKNOWLEDGMENT
This work was supported by the Spanish Ministry of Educa-
tion and Science under the projects numbers ENE2006-02930
and DPI2009-07004.
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(b) Phase-to-phase voltage 𝑉𝑠 𝑏 − 𝑉𝑠 𝑎

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