AWNEEP DEV PANDEY

Phone: (+91)-9532853972 Email: awneep.pandey.ece13@iitbhu.ac.in

Career Objective:
To be at a challenging position to utilize my skills, training experience and creativity in the field of
VLSI design, which will bring growth to the organization and the society.

Work Experience:
Organization: ARM Embedded Technologies Private Limited.
Duration: August 2016 till date.
Designation: Memory Design Engineer.

Organization: INSEMI TECHNOLOGY SERVICES PVT. LTD., BANGALORE.

Duration: March – August 2016.
Designation: Trainee Engineer.

Project: Design and Analysis of 6T SRAM at 90nm Technology

 All the basic parameter of 6T SRAM bit cell has been designed and analyzed by using SPICE.
 The analysis has been functionally verified with schematic with cadence tool.
 The Layout also has been designed by using Cadence tool along with the verification of DRC & LVS.

Project: Design and Analysis of basic memory blocks

 In this project memory architecture has been analyzed which consist of control logic, row decoder, I/O
block and core array
 Row Decoder & Column Decoder has been designed. Different read/write driver has been analyzed. TO
increase the performance of the device minimization of area has been done.

Project: Design and Analysis of latches and flip-flops.

 Timing analysis of latch and Flip-Flop have been done, which consist of analysis of SETUP and HOLD
time.
 The Schematic & Layout has been designed by using Cadence tool along with the verification of DRC
& LVS for Layout.

Project: Study and Analysis of CMOS and its operation

 Study and Design of CMOS inverter has been done and its different operating region has been
analyzed.
 Design of different logic blocks using CMOS circuit.

Education:

Year Institute/Board Degree Grade

2015 IIT (BHU), Varanasi M.Tech (Electronics Engineering) 8.20
2013 BBDNITM, Lucknow B.Tech (Electronics and Communication) 77.84
2008 Uttar Pradesh Board Intermediate (12th) 77.80
2006 Uttar Pradesh Board High School (10 th) 62.50
Projects:
Project: A high speed and low power consumption bootstrapped full–swing CMOS inverter
 In this project a new high performance low power CMOS bootstrapped driver circuit is
presented. The output voltage levels may suffer from threshold voltage drop in several
circuit structures, such as pass transistors gates or enhancement-load inverters.
 Bootstrapping is a technique that is sometimes used to charge up a transistor gate to a
voltage higher than VDD when that transistor has to drive a line to the voltage level of
VDD.

Project: Design of Autonomous Line Follower Robot that detects and follows a line
 In this project the line follower is autonomous robots that detect and follow a line. The
path may be visible like a black line on a white surface or may be reverse of that.
 The robot must sense the line and have to stay on course while correcting the wrong
moves using feedback mechanism thus forming a simple but yet effective close loop
system.

Responsibilities apart from project:

 Parliament member and Student representative of M-Tech in IIT (BHU), Varanasi.
 Won the first prize in the event UTKARSH'11 For "The Aquabot Robotic Fish".

Skill/Knowledge:
 Skill: CADENCE, Perl, Scripting, Verilog, VHDL, C, HSpice, Embedded System, HFSS,
CST.
 Knowledge: Analog Circuit, Digital Electronics, CMOS Digital Integrated Circuit and
layout, ADC/DAC, Differential Amplifier, Electronics Devices, Microprocessor,
Communication, Electromagnetic, Antenna & Fabrication.

Research Paper:
 Published a paper in 10th International Conference on Microwaves, Antenna Propagation &
Remote Sensing 2014 titled "Slot Loaded Antipodal Vivaldi Antenna with Improved
Performance".

Hobbies:
 Listening music and Playing Football

Declaration:
I hereby declare that the above mentioned information in very true to the best of my knowledge.

Date- 22 August, 2016

Place- Bengaluru Awneep Dev Pandey