Us06-105 850 01 02 02 PDF

SONOLINE G20
US
Function-Description
System
System Functional Description
08647831
08647815
© Siemens AG 2004
The reproduction, transmission or use
of this document or its contents is not
permitted without express written
Siemens Medical
Ultrasound
ejt DivisionSolutions
authority. Offenders will be liable for
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created by patent grant or registration
of a utility model or design, are
reserved.
Print No.: US06-105.850.01.02.02 English

Replaces: US06-105.850.01.01.02 Doc. Gen. Date: 01.05
n.a.
Part No.: n.a.

sd
2 Revision / Disclaimer
1Revision / Disclaimer
Copyright
Copyright © 2004 by Siemens Corporation. All rights reserved. No part of this publication
may be reproduced, transmitted, transcribed, stored in retrieval systems, or translated into
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to this manual.Although Siemens Corporation has attempted to ensure accuracy through-
out this manual, Siemens Corporation assumes no liability for any errors or omissions, nor
for any damages resulting from the application or use of this information.
Trademarks
ACUSON, Sequoia, Cypress, AEGIS, Aspen, 128XP, XP, AcuNav, CV70, SONOLINE,
Adara, Antares, G20, G40, G50, G60S, Omnia and KinetDx are trademarks of Siemens
Corporation registered in the U.S. Patent and Trademark Office. CWS3000, DS3000,
WS3000, and WebPro are trademarks of Siemens Corporation.
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Other products and brand names are trademarks of their respective owners.
Disclaimer
The service of equipment described herein is to be performed by qualified personnel who
are employed by Siemens or one of its affiliates or who are otherwise authorized by Sie-
mens or one of its affiliates to provide such services.
Assemblers and other persons who are not employed by or otherwise directly affiliated
with or authorized by Siemens or one of its affiliates are directed to contact one of the
local offices of Siemens or one of its affiliates before attempting installation or service pro-
cedures.
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All computer programs copyright 1990-2004 by Siemens Corporation or its suppliers. Pro-
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Siemens or its suppliers retain(s) ownership of and title to any computer program supplied
with the equipment and to the trade secrets embodied in such computer programs. Sub-
ject to the Buyer’s acceptance and fulfillment of the obligations in this paragraph, Siemens
grants the Buyer a personal, non-transferable, perpetual, non-exclusive license to use any
computer program supplied with the Equipment that is necessary to operate the Equip-
ment solely on the medium in which such program is delivered for the purpose of operat-
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grams nor may Buyer make a copy of such program or apply any techniques to derive the
trade secrets embodied therein. In the event of a failure by Buyer to comply with the terms
SONOLINE G20 US06-105.850.01.02.02 Page 2 of 26 Siemens

01.05 sd Medical Solutions USA, Inc.
Revision / Disclaimer 3
of this license, the license granted by this paragraph shall terminate. Further, because
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rect, consequential, incidental or other damages arising out of the sublicense of the com-
puter programs supplied with the equipment.
Siemens US06-105.850.01.02.02 Page 3 of 26 SONOLINE G20

Medical Solutions USA, Inc. 01.05 sd
4 Table of Contents
1- 0Table of Contents
1 _______ Functional Description ___________________________________________ 5
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Front End Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
A30-1 PBIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
A30 TXRX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
A31 TRBF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
A32 CFMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
A37 MPXA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
A37-1 MPXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Back End Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
A33 ECPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
A33-2 SBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
A33-3 HD Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
A34 AVIF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
A35 MTHR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
A36 RGLT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
A03 SWRG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
A04 OUTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
A05 LNF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
A06 TRNS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
A07 LSPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Control Panel, Monitor, and CDRW Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
A10 CPNL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
A15 MON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
A27 CDRW (CD-R/RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Interconnect System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
System PCB Functional Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Front End PCBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Back End PCBs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Functional Description 5
2-
Overview
1Functional Description
The SONOLINE G20 system architecture has two configurations, the LC and the SLC,
comprised from the following sections:
• Front End Block
For the LC configuration: Consisting of the A30-1 PBIF, A30 TXRX, and A31 TRBF
printed circuit boards (PCB). These boards are the system interface for transducers,
control the transmit (Tx) and receive (Rx) functions, and control transducer
beamforming.
For the SLC configuration: Consisting of the A30-1 PBIF, A30 TXRX, A31 TRBF, A37
MPXA, and the A37-1 MPXT printed circuit boards (PCB). These boards are the system
interface for transducers, control the transmit (Tx) and receive (Rx) functions, and
control transducer beamforming. The A37-1 MPXT is an extension board connecting
the A37 MPXA to the A35 mother board. The A37 MPXA embodies a sector port,
switching circuit, and a pre-amplifier.
• Back End Block
For the LC configuration: Consisting of the A33 ECPR, A33-2 SBC, A33-3 HD Drive,
A34 AVIF2 , and the A35 MTHR2 components. These components control the echo
processing functions, system functions (by a single-board computer), partitioned
storage on the hard disk drive (HDD), audio video functions, and a mother board
interface.
For the SLC configuration: Consisting of the A32 CFMS, A33 ECPR, A33-2 SBC,
A33-3 HD Drive, A34 AVIF2 , and the A35 MTHR2 components. These components
control the echo processing functions, system functions (by a single-board computer),
partitioned storage on the hard disk drive (HDD), audio video functions, and a mother
board interface. The A32 CMFS controls the motor rotation, generates sector transmit
signals, and receives sector echo signals.
• Power Block
Consisting of the A36 RGLT, A03 SWRG2, A04 OUTL, A05 LNF, A06 TRNS, and A07
LSPS components. These components regulate B power to the transmit signal,
regulate power to the analog block, input voltage, OEM power, line filter, isolation
transformer, and low voltage power distribution.
• Control Panel, Monitor, and CD-RW Block
Consisting of the A10 CPNL, A15 MON, and A27 CDRW (CD-R/RW). These
components control the user interface including the control panel, monitor, and
CD-R/RW drive.

6 Functional Description
Front End Block 0
A30-1 PBIF 0
The A30-1 PBIF is the interface board for connecting array transducers to the system. The
transducers connect to either of two 156-pin ITT cannon connectors. The A30-1 PBIF uti-
lizes a walking aperture, a high voltage multiplexer (HV-MUX), and 64 mechanical relays.
The system has 48 transmit and receive channels (16-channel folded-over). The PBIF
board and the TXRX (echo transmit and receive) board are combined as one assembly.
A30 TXRX 0
The A30TXRX (echo transmit and receive) board consists of the following components:
• Tx driver blocks
• Walking aperture with 128:48 HV-MUX (high voltage multiplexer)
• Rx buffer amp
• CPS (cross point switch) for fold-over
• Variable gain control amp
The A30 TXRX board generates Tx pulses for B and M modes. Tx trigger signals are
received from the A31 TRBF board. A beamformer supports a maximum of 48 (16-chan-
nel folded-over) active transmit and receive channels from a maximum array of 128 ele-
ments. Each transmit channel utilizes high voltage power amplifiers to drive each acoustic
element in the transducer array. The pulse output level is software programmable. The
burst length ranges from 1 to 16 cycles. Voltage power amplifiers drive each acoustic ele-
ment in the transducer array. Software regulates the transducer acoustic power output.
The A30 TXRX receives 48 channel echo signals through 48 channel buffer amplifiers that
are folded-over by CPS ICs into 16 channel signals. (Control signals for CPS are gener-
ated in A31 TRBF.) The input to these buffer amplifiers is electrically protected from the
high voltage transmit pulses. The channel gain selection allows for aperture shading for a
given transducer, dynamic compensating for signal amplitude variation, and dynamic fil-
tering during beam steering.
A31 TRBF 0
The A31 TRBF (TX/RX beamformer) board performs the Rx and Tx beamforming for lin-
ear and convex array transducers. The A30 TXRX (echo transmit and receive) fold-over
signals are sent to the A31 TRBF board. The A31 TRBF board has the following compo-
nents:
• Two 8-channel ADCs (analog-to-digital converter)
• Four 4-channel Rx digital beamforming ASICs (application specific integrated circuit)
• 48-channel Tx pulse generator

• Controller for HV-MUX (high voltage multiplexer)

Tx Trigger signals are sent to Tx Driver block on the A30 TXRX board. The transmit aper-
ture size may be selected, through software, to be less than 48, depending on the focal
points and the acoustic vectors. Each of the transmit channels include digital delay gener-
ators to drive each acoustic element in the transducer array.
The pulse output level is software-programmable. The burst length ranges from 1 to 16
cycles. The A31 TRBF ADC utilizes a sample rate of 40MS/s at a resolution of 10-bits and
processes 8-channels at a time. Digitized echo data is output to Rx beamforming ASIC.
Echo signals are demultiplexed 20 MHz data and sent to the A33 ECPR (echo processor)
board.
A32 CFMS 0
The A32 CFMS PCB performs motor-rotation control of the mechanical sector transduc-
ers and controls the transmit (Tx) and receive (Rx) functions. To control the rotation motor
of the mechanical sector transducer, the A32 CFMS calculates and outputs rotation con-
trol signals. These calculated signals are based on the control encoder pulses from the
rotation motor on the mechanical sector transducer. This rotation control is performed by
U41 Motor Control FPGA (field programmable gate array IC).
The A33 ECPR PCB generates timing signals that transmit ultrasound in coherence with
the timing of the rotation encoder signals. The Tx echo pulse is generates in coherence to
this transmit timing.
The U25 Echo DATA IF CPLD generates a “Charp” transmission, which sends multiple
frequency pulses in one transmission. A 12-bit A/D converter converts the Rx echo sig-
nals from analog to digital, and sends the converted echo signals to the A33 ECPR. The
A33 ECPR then converts the image format.
The feed-forward method, which is a compromise between an encoder-master method
and a system-master method, is adopted for the Tx pulse generation timing. With the
feed-forward method, the encoder pulse time “T” is measured for the last M-period of
encoder pulses and controlled so that the next M-period can be transmitted at “N” times in
“T/N” period. TBGR (time base generator and digital RF processor) FPGA on the A33
ECPR PCB calculates this Tx timing.
A37 MPXA 0
The A37 MPXA PCB has a mechanical sector connector providing an interface for
mechanical sector transducers. This PCB houses a signal switching circuit that switches
Rx signals from a mechanical sector transducer and has a preamplifier that amplifies Rx
signals from a mechanical sector transducer. This switching circuit switches between the
signal line to the acoustic elements of 6 MHz (or lower) provided in a mechanical sector
transducer and the signal line to the acoustic elements of 7.5 MHz or higher.

A37-1 MPXT 0
The A37-1 MPXT PCB is the extension board that connects A35 MTHR2 and A37 MPXA.

Back End Block 0
A33 ECPR 0
The A33 ECPR (echo processor) board performs the following functions:
• Edge Enhance
• Dynamic filter
• LOG compression
The A33 ECPR board consists of following components:
• Time base controller
• RACS CPU
• TBGR FPGA
• BWPR ASIC
• BWPF FPGA
• PCI I/F FPGA
Echo data is demultiplexed in the EMUX (echo multiplexer) cPLD (complex programming
logic device) and sent to the BWPR (black and white processor) ASIC (application specific
integrated circuit) via the TBGR (time based generator and digital RF processor) FPGA
(field programmable gate array IC). PCIF (PCI interface) FPGA is a PCI (peripheral com-
ponent interconnect) bridge and utilizes FiFo (fast in- fast out memory) as buffer. The
decoder cPLD generates a system Information bus and TBGR FPGA generates a Control
Index bus that are controlled for the front end block.
Tx/Rx timing is generated by the time base generator and controlled by RACS (real time
acoustic control system) CPU (SH-3). The system controller is a PC-based board (A33-2
SBC: single board computer); the interface between the SBC boards is PCI I/F.
A33-2 SBC 0
The A33-2 SBC (single-board computer) board is the system controller board. The form
factor is PICMG (PCI Industrial Computers Manufactures Group) half-size. The following
is a list of the SBC board specifications:
• Celeron 1.2 GHz socket 370 based PC board (RadiSys)
• 256 MB SDRAM PC133 in one DIMM
• CD-R/RW Drive with IDE interface
• Installed Windows XP embedded
• 815E graphic chip set
• Display performance: 40 frames /s (Image), 60 frames/s (Overlay)
• LAN, RS-232-C, USB1.1

A33-3 HD Drive 0
The A33-3 HD (hard disk) drive is a 3.5 inch HDD with a minimum of 40 GB and IDE inter-
face.
A34 AVIF2 0
The A34 AVIF2 (audio video interface) board is video I/O board and I/O panel. The FPGA
(field programmable gate array IC) works as a down converter and an up converter. The
down converter converts VGA (video graphic array) format to NTSC (National Television
Standards Committee) and PAL (phase alteration by line) video format; the up converter
converts NTSC and PAL video to VGA format. The SDRAM (synchronous dynamic ran-
dom access memory) converts frame memory. These signals are used in the EMIFIL
(electro-magnetic interference filter) to apply the compliance for EMC.
NOTE The A34 AVIF2 is a redesign of the previous A34 AVIF.
A35 MTHR2 0
The A35 Mother board is the interface where the back end block PCBs connect.

Power Block 0
A36 RGLT 0
The A36 RGLT (regulator) board generates B power for Tx and supplies power to the ana-
log block.The DAC (digital-to-analog converter) voltage check is mounted on this board.
A03 SWRG2 0
The A03 SWRG2 (switching regulator) unit is a switching regulator with primary input volt-
age. The input voltage ranges from 90 VAC to 250 VAC.
NOTE The A03 SWRG2 is a redesign of the previous A03 SWRG to meet
the new CE regulations second edition requirements
A04 OUTL 0
The A04 OUTL (outlet) unit is located at the rear side of the system under the monitor.
The A04 OUTL has two outlets and two fuses, one is for 115 V and the other is 230V.
A05 LNF 0
The A05 LNF (line filter) unit consists of a low noise AC line filter.
A06 TRNS 0
The A06 TRNS (isolation transformer) unit is the transformer for service outlet.
A07 LSPS 0
The A07 LSPS (line selector and power supply) board selects the line detected by input
voltage range.

Control Panel, Monitor, and CDRW Block 0
A10 CPNL 0
The A10 CPNL (control panel) unit consists of a controller, DGC slide pots, panel software
and trackball. The A10 CPNL controls the interface to system through USB ports, freeze,
reset, and power on signals.
A15 MON 0
The A15 MON (monitor) unit is a VGA (video graphic array) monitor. The A15 MON has
the following specifications:
• Brightness and contrast are user-selectable
• Display size is 640 dots and 480 lines
• Pixel rate is 25.175 MHz
• Power is 12V DC
• Display format is VGA
A27 CDRW (CD-R/RW) 0
The CD-R/RW interface is IDE (integrated drive electronics).

System Architecture 0
The System Architecture section consists of the following diagrams:

• Interconnect System Block Diagram
• System PCB Functional Diagrams
• Front End PCB Diagrams
• Back End PCB Diagrams
See the Component Configuration section for detailed descriptions of the components
listed in the diagrams.

Interconnect System Block Diagram 0

Fig. 1: G20 SLC Block Diagram

System PCB Functional Diagrams 0
See the Component Configuration section for detailed descriptions of the system architec-
ture.
Front End PCBs 0

A30 TXRX PCB Functional Diagram
Fig. 2:
A30-1 PBIF PCB Functional Diagram
Fig. 3:
A31 TRBF PCB Functional Diagram
Fig. 4:
Fig. 5: A37 MPXA Diagram
Fig. 6: A37-1 MPXT Diagram
Back End PCBs 0

A32 CFMS Diagram
Fig. 7:
A33 ECPR PCB Functional Diagram
Fig. 8:
A33-2 SBC PCB Functional Diagram
Fig. 9:
Fig. 10: A34 AVIF 2 PCB Functional Diagram
Fig. 11: A36 RGLT PCB Functional Diagram

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SONOLINE G20

Print No.: US06-105.850.01.02.02 English

Part No.: n.a.

SONOLINE G20 US06-105.850.01.02.02 Page 2 of 26 Siemens

Siemens US06-105.850.01.02.02 Page 3 of 26 SONOLINE G20

1 _______ Functional Description ___________________________________________ 5

SONOLINE G20 US06-105.850.01.02.02 Page 4 of 26 Siemens

Siemens US06-105.850.01.02.02 Page 5 of 26 SONOLINE G20

Front End Block 0

SONOLINE G20 US06-105.850.01.02.02 Page 6 of 26 Siemens

• Controller for HV-MUX (high voltage multiplexer)

Siemens US06-105.850.01.02.02 Page 7 of 26 SONOLINE G20

SONOLINE G20 US06-105.850.01.02.02 Page 8 of 26 Siemens

Back End Block 0

Siemens US06-105.850.01.02.02 Page 9 of 26 SONOLINE G20

NOTE The A34 AVIF2 is a redesign of the previous A34 AVIF.

SONOLINE G20 US06-105.850.01.02.02 Page 10 of 26 Siemens

Siemens US06-105.850.01.02.02 Page 11 of 26 SONOLINE G20

Control Panel, Monitor, and CDRW Block 0

A27 CDRW (CD-R/RW) 0

The CD-R/RW interface is IDE (integrated drive electronics).

SONOLINE G20 US06-105.850.01.02.02 Page 12 of 26 Siemens

The System Architecture section consists of the following diagrams:

Siemens US06-105.850.01.02.02 Page 13 of 26 SONOLINE G20

Interconnect System Block Diagram 0

SONOLINE G20 US06-105.850.01.02.02 Page 14 of 26 Siemens

SONOLINE G20 US06-105.850.01.02.02 Page 16 of 26 Siemens

System PCB Functional Diagrams 0

Front End PCBs 0

Siemens US06-105.850.01.02.02 Page 17 of 26 SONOLINE G20

Fig. 5: A37 MPXA Diagram

Fig. 6: A37-1 MPXT Diagram

Back End PCBs 0

Siemens US06-105.850.01.02.02 Page 21 of 26 SONOLINE G20

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1 _ Functional Description _____________________________________ 5