E I A T I A - b L 2 93 = 3234600 0552Lô7 9 7 2 =

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ANSI/ TIA/ EIA-6 12 1993
APPROVED: November 2, 1993

TIAJEIA
STANDARD

Electrical Characteristics for an

Interface at Data Signaling Rates
up to 52 Mbit/s

TIAIEIA-612

DECEMBER 1993

TELECOMMUNICATIONS INDUSTRY ASSOCIATION

 E I A TIA-b12 9 3 W 3234600 0552188 809

NOTICE

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through eliminating misunderstandings between manufacturers and purchasers, facilitating
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Recommended Standards and Publications are adopted by TINEIA in accordance with the
American National Standards Institute (ANSI)patent policy. By such action, W E I A does not
assume any liability to any patent owner, nor does it assume any obligation whatever to parties
adopting the Recommended Standard or Publication.

This Standard does not purport to address all safety problems associated with its use or ail
applicable regulatory requirements. It is the responsibility of the user of this Standard to
establish appropriate safety and health practices and to determine the applicability of regulatory
limitations before its use.

Published by

%LECOMMUNICATIONS INDUSTRY ASSOCIATION 1993

Standards and Technology Department
2001 Pennsylvania Ave. N. W.,
Washington, D.C. 20006

PRICE: Please refer to current

Catalog of EL4 & JEDEC STANDARDS & ENGINEERING PUBLICATIONS
or call Global Engineering Documents, USA and Canada (1-800-854-7179)
International (303-397-7956)

All rights reserved

Printed in U.S.A.
 E I A TIA-bL2 93 = 3 2 3 4 6 0 0 0552390 4b7

ELECTRICAL CHARACTERISTICS FOR AN

INTERFACE AT DATA SIGNALING
RATES UP TO 52 Mbiüs
(From Standards Proposai Nos. 2795. 2795-1 and 2795.2.
formulated under the cognizance of TIA TR30.2 Subcommittee
on Data Transmission Interfaces)

Contents Page

1 SCOPE ..................................................................................................................1

2 APPLICABILITY................................................................................................... 2

3 ELECTRICAL CHARACTERISTICS................................................................. 3
3.1 Generator Characteristics............................................................................3
3.1.1 Open Circuit Measurement ................................................................... 4
3.1.2 Test Termination Measurements........................................................... 5
3.1.3 Short Circuit Measurement .................................................................... 5
3.1.4 Output Signal Waveform ........................................................................ 6

3.2 Load Characteristics..................................................................................... 7

3.2.1 Input Current-Voltage Measurements .................................................
O 3.2.2
3.2.3
Input Sensitivity Measurements............................................................
Cable Termination ...................................................................................
7
7
9
3.2.4 Failsafe Operation................................................................................... 9
3.3 Interconnecting Cable Electrical Characteristics................................. 10
4 ENVIRONMENTAL CONSTRAINTS............................................................. 10
5 CIRCUIT PROTECTION.................................................................................... 11

Annex A (informative)................................................................................................... 12
A .1 Interconnecting Cable ................................................................................ 12
A.l.l Length ...................................................................................................... 12
A.1.2 Cable Physical Characteristics ..........................................................12
A.1.3 Cable Termination ................................................................................. 12
A.2 ECL Generators and Receivers................................................................13
A.2.1 ECL - Emitter Coupled Logic Technology ........................................13
A.2.2 Failsafe Biasing of Receivers ............................................................. 13

Annex B (informative) ................................................................................................... 14

a References.................................................................................................... 14

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FOREWORD

(This foreword is not part of this Standard)

This Standard was formulated under the cognizance of TIA Subcommittee

TR-30.2 on Data Transmission Interfaces. It is intended to be used with
ANSIKIAEIA-613-1993, High Speed Serial Interface for Data Terminal
Equipment and Data Circuit-Terminating Equipment.
This Standard specifies generators and receivers capable of operating at data
signaling rates up to 52 Mbitís. This Standard was developed in response to a
demand from the data communications community for a high speed general
purpose DTE-DCE interface.

Annex A of this Standard is informative and provides guidelines for application.

Annex B of this Standard is also informative and provides references to this
Standard. Neither Annex is considered part of this Standard. I

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ANSI/TIA/EIA-612-1993

1 SCOPE

This Standard sDecifies the electrical characteristics of the balanced diaital

interface circuit,' normally implemented in integrated circuit technology, ?hat
may be employed when specified for the interchange of serial binary signals
between Data Terminal Equipment (DTE) and Data Circuit-Terminating
Equipment (DCE) or in any point-to-point interconnection of serial binary
signals between data equipments.

The interface circuit includes a generator connected by a balanced

interconnecting cable to a load consisting of a receiver and a termination. The
electrical characteristics of the circuit are specified in terms of required
voltage, and current values obtained from direct measurements of the
generator and receiver components at the interface points. The logic function
of the generator and the receiver is not defined by this Standard, as it is
ap pl¡catio n -dependent. Minimum electrical requirements for the
interconnecting cable are f urnished.

It is intended that this Standard will be referenced by ANSI/TIA/EIA-613-1993,

High Speed Serial Interface for Data Terminal Equipment and Data Circuit-
Terminating Equipment, that specifies the other necessary components of an
interface (e.g., connector, pin assignments, function) for applications where the
electrical characteristics of a high speed balanced digital circuit are required.

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ANSI/TIA/EIA-612-1993

2 APPLICABILITY

The provisions of this Standard may be applied to the circuits employed at the
interface between equipments where information being conveyed is in the form
of binary signals.
Typical points of applicability for this Standard are depicted in figure 1.

D D
T C
E E
Id L

Legend:

DTE = Data Terminal Equipment

DCE = Data Circuit-Terminating Equipmc

E = Interface Generator

@ = Interface Receiver

-
- = Balanced Interface Circuit

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Figure 1 Applications of balanced digital interface circuit

The balanced digital interface circuit will normally be utilized on data and
timing, or control circuits where the data signaling rate is up to a maximum limit
of 52 Mbiîís.

In this Standard, the term:

data signaling rate, expressed in the units bit/s (bits per second), is the
significant parameter. It may be different from the equipment's data transfer
rate, which employs the same units. Data signaling rate is defined as 1/T
where T is the minimum interval between two significant instants. In a binary
system for which this Standard is designed, the data signaling rate in bitk and
the modulation rate in bauds are numerically equal when the unit interval used
in each determination is the minimum interval.

star (*) represents the opposite input condition for a parameter. For example,
the symbol Q represents the receiver output state for one input condition, while
Q' represents the output state for the opposite input state.

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ANSITTINEIA-612-1993

3 ELECTRICAL CHARACTERISTICS

The balanced digital interface circuit is shown in figure 2. The circuit consists
of three parts: the generator (G), the balanced interconnecting cable, and the
load. The load is composed of a receiver (R) and a cable termination/faiIsafe
network. The electrical Characteristics of the generator and receiver are
specified in terms of direct electrical measurements while the interconnecting
cable is described in terms of its electrical characteristics.

+ GENERATOR )+BALANCED I N T E R F A C L LOAD b

CABLE Cable

1
Rt =
110 R
B
755- B'
Q
Rrp =
1.5 k(l
Vee

I I

Legend:

G = Generator A,B = Generator Interface Points

Rgp = Generator Pull Down Resistor A,B' = Receiver Interface Points
R = Receiver C = Generator Circuit Common
Rt = Termination Resistor C' = Receiver Circuit Common
Rrp = Receiver Bias Resistor (Optional, Receiver Dependent)
Vcpd = Common Potential Difference
Vee = Negative Voltage Power Supply
NOTE: All resistors f 2%

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Figure 2 Balanced digital interface circuit

3.1 Generator Characteristics

The generator 'electrical characteristics are specified in accordance with the
measurements illustrated in figures 3 to 6 and described in 3.1.1 through 3.1.4.
The generator circuit meeting these requirements results in a low impedance

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ANSITTINEIA-612-1993

balanced source that will produce a differential voltage applied to the

interconnecting cable in the range of 590 mV to 1500 mV.

The signaling sense of the voltages appearing across the interconnecting

cable are defined as follows:

a. The A terminal of the generator shall be negative with respect to the

B terminal for a binary O (SPACE or OFF) state.

b. The A terminal of the generator shall be positive with respect to the B

terminal for a binary 1 (MARK or ON) state.

NOTE -, The sense of data binary O (SPACE) and data binary 1 (MARK)
are inverted from that specified in ElMIA-422-A.

The logic function of the generator and the receiver is beyond the scope of this
Standard, and therefore is not defined.

3.1.1 Open Circuit Measurement (Figure 3)

For either binary state, the magnitude of the differential voltage (VOCor VOC')
measured between the two generator output terminals shall not exceed 1.5 V.

Vee OPEN CIRCUIT MEASUREMENT

T-

I VOC I 5 1 . 5 v, I VOC' I 5 1.5 V

0 = Measured Parameter

I
Vee

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Figure 3 Open circuit measurement

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 ANSITTINEIA-612-1993

3.1.2 Test Termination Measurements (Figure 4)

With a test load of the resistors shown in figure 4, the magnitude of the
differential output voltage (Vt), shall be 590 mV or greater. For the opposite
binary state, the polarity of Vt shall be reversed (Vt*). The magnitude of the
difference between Vt and Vt' shall be less than 100 mV. The magnitude of the
generator offset voltage (Vos), measured between the center point of the test
load and the generator circuit common shall be -1.6 V or more positive for
either binary state. The magnitude of the difference of Vos for one binary state
and Vos' for the opposite binary state shall be 1O0 mV or less.

Vee TEST TERMINATION MEASUREMENTS

I Vt I 2 590 mV, I Vt' I 2 590 mV
I I Vt I - I Vt' I I I 100 mV
O V 2 VOS 2 -1.6 V, O V 2 VOS' 2 -1.6
-
I Vos Vos' I I100 mV
= Measured Parameter
I
Vee

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Figure 4 Test termination measurements

3.1.3 Short-Circuit Measurement (Figure 5)

With the generator output terminals short-circuited to each other, the magnitude
of the current (los) following between each output terminal shall not exceed
50 mA in magnitude, for either binary state.

SHORT CIRCUIT MEASUREMENT

I los I s 50 mA, I los' I I 5 0 mA
= Measured Parameter

Vee

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Figure 5 Short-circuit measurement

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ANSI/TIA/EIA-612-1993

3.1.4 Output Signal Waveform (Figure 6)

During transitions of the generator output between alternating binary states

(one-zero-one-zero, etc.), the differential voltage measured across the 11O Q
test load connected between the generator output terminals shall be such that
the voltage monotonically changes between 0.2 and 0.8 of Vss within 0.5 ns to
2.3 ns. Thereafter, the signal voltage shall not vary more than 10% of Vss from
the steady state value, until the next binary transition occurs, and at no time
shall the instantaneous magnitude of Vt or Vt* exceed 1500 mV nor be less
than 590 mV. Vss is defined as the voltage difference between the two steady
state values of the generator output.

Legend: Vee
t b = Time duration of the unit interval
at the applicable data signaling rate.
0.5 ns 5 tr or tf 22.3 ns
Vss = Difference in the steady
state voltages
vss = 1 Vt - Vt* I

Vee

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Figure 6 Output signal waveform

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ANSITTINEIA-612-1993

3.2 Load Characterfstics

The load is composed of a receivers (R) and a termination/failsafe network as
shown in figure 2. The electrical characteristics of a receiver without
termination or failsafe provision are specified in terms of measurements
illustrated in figures 7 to 9 and described in 3.2.1 and 3.2.2. A circuit meeting
these requirements results in a differential receiver having a high input
impedance, and a small input threshold between f 150 mV.

3.2.1 Input Current-Voltage Measurements (Figure 7 )

With the voltage Via (or Vib) ranging from -0.5 V to -2.0 V while Vib (or Via) is
held at -1.32 V, the resultant input current lia (or lib) shall be no greater than
350 PA. These measurements apply with the receiver's power supply(s) in
both power-on and power-off conditions (as defined by the Integrated Circuit
manufacturer). Note that these measurements are made with any termination
resistor or failsafe provision disconnected.

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Figure 7 Receiver input current-voltage measurements

3.2.2 Input Sensitivity Measurements (Figure 8)

Over an entire input voltage range of -0.5 V to -2.0 V (referenced to receiver
circuit common), the receiver shall not require a differential input voltage of
more than 150 mV to correctly assume the intended binary state. Reversing the
polarity of Vi shall cause the receiver to assume the opposite binary state. The
receiver is required to maintain correct operation for differential input voltages
ranging between 150 mV and 1.5 V in magnitude. Note that these
measurements are made with any termination resistor or failsafe provision
disconnected.

Figure 9 illustrates the minimum and maximum operating voltages of the

receiver. Note that the logic function of the receiver is not defined by this
Standard.

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 EIA TIA-612 93 3234600 0552203 072
ANSITTINEIA-612-1993

....

Vcm = -0.575 V to -1.925 - Y

............................................................... h . 5V
Vi (V) measured from B' to A'

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Figure 8 Input sensitivity measurements

A'
I
d
to
= Measured Parameter

= Applied Voltage

B'
Note:
C' Vcrn = (Via + Vib)M,
Vid = IVia - Vibl

Applied Voltages
Resulting
Input
Voltage
Resulting
Common
Mode Voltage
I
Via I Vib Vid Vcrn
-0.50 V -0.65 V +150 mV -0.57 V
-0.65 V -0.50 V -150 mV -0.57 V

-0.50V -2.00 V +1.50 V -1.25 V

-2.00 V -0.50 V -1.50 V -1.25 V

I -1.85 V
-2.00 V
-2.00 V
-1.85 V
+150 mV
-150 mV
-1.92 V
-1.92 V

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Figure 9 Receiver input sensitivity table

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ANSI/TIA/EIA-612-1993

3.2.3 Cable Termination

For all applications, the use of a cable termination is required. The

recommended value is 110 R f 2%. The termination resistor is connected
across the cable at the load end of the cable, as close to the receiver input
pins as possible.
3.2.4 Failsafe Operation

Other standards and specifications using this electrical characteristics of the

balanced digital interface circuit may require that specific interchange circuits
be made failsafe to certain fault conditions. Such fault conditions.may include
one or more of the following:
1) open-circuited interconnecting cable

2) generator in power-off condition

When detection of one or more of the above fault conditions is required by

specific applications, additional provisions are required in the load and the
following items must be determined and specified.

1) which interchange circuits require fault detection

2) what faults must be detected

3)what action must be taken when a fault is detected

The method of detection of fault conditions is application-dependent and is
therefore not further specified. (see Annex A.2.2)

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ANSITTINEIA-612-1993

3.3 Interconnecting Cable Electrical Characteristics

The cable shall consist of 25 twisted pairs of conductors of 28 AWG. The cable
has an overall foil/braid shield which serves the purpose of a signal shield.

The two wires of each pair shall be connected to the same signal, one to the
NA' and the other to the B/B' signal pins.
Maximum DC Resistance
(DCR) at 20 OC 3.5 n
Differential Impedance at 50 MHz 110 alt 11R
Maximum Signal Attenuation
at 50 MHz 4.5 dB
Mutual Capacitance within pair
at 1 kHz 47.6 56.5 pF/m (14.5 i 2.0 pF/ft)

Propagation Delay
maximum: 79 ns
skew (pair to pair) 2.0 ns

See Annex A.l for further guidance on the interconnecting cable.

4 ENVIRONMENTAL CONSTRAINTS

A balanced digital interface circuit conforming to this Standard will perform

satisfactorily at data signaling rates up to 52 MbiVs providing that the following
operational constraints are simultaneously satisfied:

a. The interconnecting cable meets the recommended cable

characteristics and the cable is appropriately terminated.

b. The input voltage at the receiver is between -0.5 V and -2.0 V with
respect to receiver circuit common.

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ANSI/TIA/EIA-612-1993

5 CIRCUIT PROTECTION

Balanced digital interface generator and receiver devices, under either the
power-on or power-off condition, complying to this Standard shall not be
damaged under the following conditions:

a. Generator open circuit.

b. Short-circuit across the balanced interconnecting cable.
c. Short-circuit to circuit common.

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ANSI/TIA/EIA-612-1993 A

ANNEX A (Informative)
a
GUIDELINES FOR APPLICATION
A.l Interconnecting Cable
The following section provides further information to Section 3.3 and is
additional guidance concerning operational constraints imposed by the cable
parameters of length and termination.

A.1.1 Length
The nominal length of cable separating the generator and the load is 15 meters
(50 ft).

A.1.2 Cable Physical Characteristics

The following physical characteristics apply to the cable:

Conductor 28 AWG, 7 strands of 36 AWG, tinned annealed copper,

nominal diameter 0.38 mm (0.015 in.)
Insulation polyethylene or polypropylene; 0.24 mm (0.0095 in.)
nominal wall thickness; 0.86 mm +_ 0.025 mm ( 0.034 in +_
0.001 in.) outside diameter

Foil Shield 0.051 mm (0.002 in.) nominal

aluminum/polyester laminated tape spiral wrapped around
the cable core

Braid Shield braided 36 AWG, tinned plated copper in accordance

with 80% minimum coverage, in electrical contact with the
aluminum of the foil shield

Outside Diameter I 10.6 mm (I

0.417 in.)

A.1.3 Cable Termination

The characteristic impedance of twisted pair cable is a function of frequency,

wire size and type as well as the kind of insulating materials employed. For
example, the characteristic impedance of average 28 AWG, copper conductor,
plastic insulated twisted pair cable, to a 50 MHz sine wave will be on the order
of 110 a.

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ANSI/TIA/EIA-612-1993

A.2 ECL Generators and Receivers

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A.2.1 ECL Emitter Coupled Logic Technology

Emitter Coupled Logic (ECL) families such as l O K , 10H, and 100K have been
developed that meet the requirements of this Standard by a number of
Integrated Circuit manufacturers. The 1OOK family is compensated for both
Power Supply Voltage and Operating Temperature variations, offering constant
thresholds and output levels over both ranges. Some other families are only
Power-Supply-Voltage-compensated. The 1OOK family also accepts a wide
range of power supply voltages (Vee) from -4.2 V to -5.7 V.

A.2.2 Failsafe Biasing of Receivers (Figure A.l)

In the event that the interface cable is not present, the receiver must default to a
known state. The method of failsafe biasing is application and component
specific, and therefore is beyond the scope of this Standard.

External resistors can be used to bias the receiver's input into a known state
(2150 mV differential) for the case of the disconnected cable. For example, a
1.5 kn pull up and pull down resistor will bias the receiver to 177 mV,defaulting
the receiver to a OFF state.

Vee
I
1.5 k@
A' .L

o
B'

Figure A.1 - Receiver failsafe biasing

It should be noted that it is not necessary to use external resistors on ail families
of receivers. Some receiver integrated circuits have this feature incorporated
internal to the integrated circuit.

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ANSITTINEIA-612-1993

ANNEX B (informative)
e
REFERENCES
ANSIíTIA/EIA-613-1993, High Speed Serial Intedace for Data Terminai
Equipment and Data Circuit-Terminating Equipment

E IA-422-A, Electrical Characteristics of Balanced Voltage Digital Interface

Circuits

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