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ARPAN DESAI
Contents
Lithography/Patterning
Etching
Oxide Growth/Oxide Deposition
Ion Implantation
Device Isolation Techniques
Fabrication of nMOS Transistor
Fabrication of CMOS
Lithography/Patterning
Etching is a common
process to pattern
material on the surface.
Ion implantation is
used to add doping
materials to change the
electrical
characteristics of
silicon locally.
The dopant ions
penetrate the surface,
with a penetration
depth that is
proportional to their
kinetic energy.
Fabrication of nMOS
Fabrication of nMOS
Fabrication of nMOS
Functions of Various Layers
Drawbacks:
large oxide steps at the boundaries between active areas and field
regions.
cracking of polysilicon/metal and subsequent deposited layers
Process flow
1) Grow a thin pad oxide (SiO2) on the silicon surface.
Thin pad oxide - protect the silicon surface from
stress caused by nitride
2) Define active area : deposition and patterning a
silicon nitride (Si3N4) layer
Device Isolation Techniques
Local Oxidation of Silicon (LOCOS)
3) Channel stop implant: p-type regions that surround the
transistors
To prevent the formation of any unwanted channels
between two neighboring N+ diffusion regions.
5) Etch the nitride layer and the thin oxide pad layer
CMOS Fabrication Process:
1. Layer Representations
– Substrates and/or Wells
– Diffusion Regions (Active areas)
• Select regions: For contacts to substrate or well
– Polysilicon Layers
– Metal Interconnects
• Contact: Metal to active
• Via: Metal to metal
2. Intralayer Constraints
3. Interlayer Constraints
MOSIS (MOS Implementation System) Layout Design
Rules
MOSIS (MOS Implementation System) Layout Design
Rules
Polysilicon Rules
R3 Minimum poly width 2λ
R4 Minimum poly spacing 2λ
R5 Minimum gate extension of 2λ
poly over active
R6 Minimum poly active edge 1λ
spacing (poly outside active
area)
R7 Minimum poly active edge 3λ
spacing (poly inside active
area)
MOSIS (MOS Implementation System) Layout Design Rules
VDD
A Y
GND