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10nS delay
10nS glitch
Race condition
4
caused by B signal
1 Digital Design
Static 1-hazard
a network output momentarily go to the 0 when it should remain a
constant 1
Static 0-hazard
a network output momentarily go to the 1 when it should remain a
constant 0
Dynamic hazard
if an output changes three or more times, when the output is supposed to
change from 0 to 1 (1 to 0)
Glitches during signal transitions
2 Digital Design
1
Hazards in Combinational Circuits
AB AB
00 01 11 10 00 01 11 10
C C
0 1 0 1
1 1 1 1 1 1 1 1
To avoid hazards:
every pair of adjacent 1s should be covered by a 1-group
3 Digital Design
Combinational networks
don’t care – the network will function correctly
Change here
4 Digital Design
2
System Component Levels
Levels of abstraction
gate
Combinatorial networks
flipflops
LD(R1) ld ld LD(R2)
RD(R1) R1 R2
rd rd RD(R2)
shift registers
16
16
LD(L1) ld
L1
CL(L1) cl
16
+
BR0
16
16
LD(BR) ld rd RD(BR) A B
DEC(BR) dec BR S0
ALU S1
C16 16
Systems
C0
F
F15..0 16
LD(A) ld rd RD(A)
A
cl CL(A)
5 Digital Design
Flip-Flops/ Latches
Latches and Flip-Flops are devices that can have two internal
states (0,1)
levels
edges
6 Digital Design
3
Basic RS Flip-Flop (NAND)
1
0 S (set) S R Q Q’
1 Q
1 0 0 1
1 1 0 1 (after S = 1, R = 0)
1 0 1 1 0
1 1 1 0 (after S = 0, R = 1)
0 R (reset) 2 Q’
’ 0 0 1 1
(a) Logic diagram (b) Truth table
7 Digital Design
illegal states
8 Digital Design
4
D Latch (transparent latch)
9 Digital Design
Clocked flip-flops
Devices synchronised to clock edges
edge triggered
10 Digital Design
5
A Clock Waveform
voltage
time
Pw
rising edge falling edge
τ - period (in seconds)
Pw - pulse width (in seconds)
f - frequency pulse width (in Hertz)
f = 1/τ
11 Digital Design
D-type Flip-Flop
D
D-type Q
FF
clock Q
12 Digital Design
6
Clocked JK Flip-Flop
do nothing
reset
set
toggle
negative edge
triggered next state
14 Digital Design
7
Synchronous vs Asynchronous Inputs
Synchronous input
Output will change after active clock edge
Asynchronous input
Input changes independent of clock
15 Digital Design
state machines
systems where the present state is based on
the present state of the system STATE = stable condition
the inputs of the system
clock
Present state = next state
present
state combinatorial
network next
state
logic
inputs
The clock signal updates the present state with the next state values
State information stored in a flip-flop based register
16 Digital Design
8
Sequential System Concepts
feedback
clock
register
Combinatorial
Logic Excitation
(next state logic) variables Combinatorial
Logic
(output logic)
outputs
inputs Optional
(Mealy)
17 Digital Design
Moore machine
feedback
Outputs are only dependent on
clock the state variables
register
Combinatorial
logic Excitation
variables Combinatorial
State logic
storage outputs
inputs
Mealy machine
feedback
Combinatorial
logic Excitation
Combinatorial
variables
logic
outputs
inputs
18 Digital Design
9
Real World Examples 1
19 Digital Design
d b
10 01 [error = state(b) & ready]
ready
State code
ready
Moore output
c [running]
11
done
20 Digital Design
10