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VN/VP13 Series

Application Note

High Voltage Pulser Circuits

Introduction Circuit Description/Design Considerations

The high voltage pulser circuit shown in Figure 1 utilizes Supertex The high voltage pulser in Figure 1 consists of 3 basic stages: (A)
complementary N- and P-channel DMOS transistors to achieve input signal interface, (B) high current buffer and level translation,
excellent performance and efficiency with minimal components. and (C) high voltage and current output drivers. Each stage has
The output voltage swings are -100V to +100V. Rise and fall its own specific requirements for device parameters, which will
times are less than 10 nsec while sourcing and sinking over 0.75 be discussed in the following section.
and 1.0 amps respectively. The output is conveniently controlled
by TTL or CMOS input signals. The VDD supply voltage, however,
needs to be at the same value as the input logic high value. Stage 1:
High voltage, high speed, and high current pulses at low duty Stage 1, consisting of VN1306N3 and VP1306N3, is an input
cycles are required in several applications. Ultrasound cleaning stage to interface directly with TTL or CMOS logic signals.
equipment, flaw detection, medical imaging, and test instruments Low input capacitance and fast switching speed are the most
are but a few examples. Complementary N- and P-channel important considerations in this stage. The VN1306N3 and
DMOS transistors, VN1306N3, VP1306N3, TN0104N3, VP1306N3 are chosen for their low in-put capacitance, 35pF
TP0102N3, TP0620N3, and TN0620N3 are used for their low maximum, and their 2ns typical/5ns maximum td(on), tr,
threshold voltages, low input capacitances and high output td(off) and tf switching speed. This will minimize loading and
current capabilities. These are essential features to generate distortion on the input drive signals. Often the input signals
high voltage pulses with high speeds and currents. Another are from fairly resistive sources, which may be in the order
aspect considered was their cost-effective TO-92 package, of 100’s of ohms, creating large RC constants. Low CISS and
which saves board space. CRSS will allow the gate voltage to charge past the transistors’
threshold voltage rapidly, to accomplish high speed switching.

VPP = +100V The low threshold ratings will accommodate TTL and CMOS
VDD = 10V
compatibility. Max threshold ratings, VGS(th), for VN1306N3
R and VP1306N3 are 2.4V and -3.5V respectively. For the
1K +
15V ‘worst case’ design consideration, VN1306N3 will turn on
VP1306N3 TP0102N3
- when the input signal voltage reaches 2.4V. For a given input
signal voltage rise and fall time of 50ns for 0 to 10V, the time
A TP0620N3 required for the input to reach 2.4V is 12ns. For VP1306N3,
C 0.01µF GP time required to turn on is about 35ns. Once the devices are
VN1306N3 TN0104N3 turned on, the output voltage rising and falling edges will
have a waveform similar to that of an RC circuit where R is
the on-resistance of the transistor and C is the total equivalent
VDD = 10V
VOUT capacitance the transistor is driving.
RL In addition to performing the interface to TTL and CMOS
100Ω signals and improving rise and fall times, Stage 1 is also a
VP1306N3 TP0102N3
high current low impedance buffer. Output currents of more
GN than 250mA source and 500mA sink (based on ID(ON)
B TN0620N3 specifications of these devices) are available to adequately
C 0.01µF
drive the inputs of the 2nd stage.
VN1306N3 TN0104N3
R 15V
1K -

VNN = -100V

Figure 1. High Voltage Pulser


Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products,
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VN/VP13 Series Applications

Stage 2: During power up and power down conditions, it is possible for

transient voltages greater than 20V to appear across the gate-
Stage 2 provides high output peak currents, improves rise to-source on the output transistors. Maximum gate-to-source
and fall times, and performs high voltage level translation. voltage, VGS, is rated at ±20V. 15V zener diodes are connected
This stage consists of device types TN0104N3 & TP0102N3. across the gate and source of the output transistors to protect
The Supertex low threshold DMOS transistors TN0104N3 against such transient voltages. These diodes will not be zenering
and TP0102N3 provide typical output peak currents of 2.8 during normal operation.
amps sink and 1.7A source. Such high currents are required
to adequately drive the input capacitances, including Miller The zener protection diodes can be omitted if VPP and VNN can
effect of the output transistors, to accomplish fast switching be ramped slowly to their rail voltages during power up.
speeds. The low threshold guaranteed maximum limits of Input signals and corresponding voltages are shown in Figure 2.
1.6V and -2.4V for TN0104N3 and TP0102N3 respectively Actual output waveforms with a 100Ω load for a 60 nsec and a
will further improve rise and fall time transitions. Resistor R 100 nsec positive and negative pulse are shown on Figures 3A
and Capacitor C provide the DC level shifting. Value of C to 3D. VPP and VNN voltages can be varied without additional
should be much larger than CIN of the output stage where CIN changes within the circuitry. For example, VNN can be -10V and
is equal to CISS plus Miller effect: CIN = CISS + CRSS (GFS* RL). VPP +190V for -10V to +190V pulses. Higher voltages and
Resistor value R is selected such that time constant RC is currents can be accomplished with minimal changes.
much greater than the output high voltage pulse width
With the source at +100V, gate voltage driving the P-channel of
the output stage are +100V and +90V to provide gate-to-source 10V
drives of 0V and -10V. Similarly for the N-channel, with the A
source at -100V, gate voltages are -100V and -90V to provide 0V
0V and +10V gate-to-source drives.
Stage 3: 0V

Stage 3 is the output stage and consists of Supertex low 100V

threshold DMOS discrete transistors TP0620N3 and
TN0620N3. These devices have a breakdown voltage rating
of 200V minimum. Output voltage swings can switch from -
100V to +100V. Input capacitance is increased due to Miller
effect, CIN = CISS + CRSS (GFS* RL). Low CRSS & CISS -100V
capacitance, high output current, low on-resistance and
200V breakdown voltage are required parameters for the 100V
output transistors. The Supertex TP0620N3 and TN0620N3 VOUT 0V
are ideally suited. Their guaranteed parameters are listed in -100V
Table 1:

Table 1

DEVICE min typ max min typ max typ max

TN0620N3 200 4.0 6.0 1.0 110 150 10 35
TP0620N3 -200 9.0 12.0 -0.75 85 150 10 35

VN/VP13 Series Applications

Figure 3A. 60 nsec Output Pulse Figure 3B. 100 nsec Output Pulse

Figure 3C. Positive Going Pulse Figure 3D. Negative Going Pulse

Optional Variations Conclusion

The high voltage pulser in Figure 1 can be easily modified to suit Supertex DMOS transistors are ideal for high speed, high
various high voltage pulser needs. Figures 4A to 4D show some voltage, high current pulsing applications. Bipolar transistors
examples. require base currents and time to recover from the saturation
region. MOSFETs do not require any DC gate current thus
Figure 4A is a positive high voltage pulser with one end pulling
enabling them to be easily driven with a simple AC coupling
to ground. Basically, components R and C are not needed to
scheme. Because of Miller effect on the high voltage outputs,
drive the N-Channel.
large peak currents are essential for the second stage to drive
Figures 4B and 4C are high and low side open drain pulsers. the outputs hard for fast switching speeds. The Supertex line of
Supertex VP2450N3 and VN2450N3 are used to satisfy DMOS transistors has low input capacitance ratings making
applications with 500V pulse requirements. them ideal candidates for high speed, high voltage pulsing
Figure 4D utilizes Supertex VN0550N3 and VP0550N3 for high applications.
voltage +250V push-pull 100mA requirements. Max input
capacitances of VN0550N3 and VP0550N3 are only 55pF and
60pF respectively. These can be driven directly from Stage 1
with minimal loss in switching speed.

VN/VP13 Series Applications


VPP = +500V
  VDD = 10V
    1K 15V
 µ VP1306N3 TP0102N3
 Input VP2450N3
VN1306N3 TN0104N3

Figure 4B. High Side Open Drain High Voltage Pulser



Figure 4A. Push-Pull Positive High Voltage Pulser 




Figure 4C. Low Side Open Drain High Voltage Pulser Figure 4D. Push-Pull ±250V High Voltage Pulser


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