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Fig. 3. Threshold-voltage shift ΔVth with dependence on the gate bias Vg under the HCI stress in the (a) SOTB and (b) bulk NMOSFETs.
Fig. 4. Stress bias Vstress dependence of the HCI degradation in the SOTB
device. Fig. 5. Comparison of the HCI lifetime between the SOTB and bulk
NMOSFETs for Vd = Vg .
Fig. 4 shows the dependence of the stress bias Vstress of the channel and the drain. This is supposed to be the reason why
HCI degradation at Vg = Vd . The power-law slopes are also the dependence on Vstress is different between the SOTB and
around 0.5 and independent of Vstress . Hence, the interface- bulk devices. The advantage of having no halo implant was also
trap-generation mechanism is thought to be the same even in experimentally confirmed in the SOTB device [19].
the case of Vstress over 2 V, in which the parasitic bipolar effect
occurs. The HCI lifetimes, defined as the 10% degradation of
C. Effect of Back Biasing in the Case of the HCI
Ion , under the CHE condition are shown in Fig. 5. The SOTB
lifetime dependence on Vstress produces a longer lifetime at A technique for applying the substrate bias Vb adaptively
the operating voltage of 1.2 V than that of the bulk device. according to the state of operation has been applied in late
To clarify the reason for this longer lifetime, the electric-field years [20]. However, with regard to the present scaled bulk
strengths in the devices with and without a halo implant were CMOSFETs, it is becoming difficult to apply Vb because of
simulated by using a 2-D device simulator. The lateral electric- the increase in the p-n junction leakage current between the
field strength Ex of the silicon surface along the channel S/D and the substrate. In SOTB devices, the wide-range back
(x-direction) at Vstress = 1.2 and 2.4 V are shown in Fig. 6(a). biasing including a forward bias higher than 0.6 V, which can
The profiles of net doping in the SOTB structure with and never be applied in a bulk device, is possible without any
without a halo implant are also shown in Fig. 6(b). Ex at the leakage due to the BOX layer. It significantly changes not only
drain edge of the devices with and without a halo implant are the drive currents but also the strength of the vertical electric-
almost the same at Vstress = 2.4 V due to the high drain voltage. field strength Ey .
Meanwhile, that of the device without a halo implant becomes Fig. 7 shows the dependences of the HCI characteristics on
about 10% lower than that of the devices with a halo implant Vb at Vstress = 2.4 V. The slope of the power law changes
at 1.2 V, which is due to the abrupt p-n junction between the from 0.4 at forward Vb to over 1.0 at reverse Vb . A slope of
1200 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 4, APRIL 2011
Fig. 6. (a) Simulated lateral electric-field strengths Ex along the channel surface in SOTB structures with or without a halo implant at (dashed) Vstress = 2.4
and (solid) 1.2 V. (b) Net doping profiles along the channel surface in the SOTB structures with and without a halo implant.
the other hand, the worst condition is the forward back biasing
because a large number of hot electrons was generated by the
large drain current (37% larger than that at Vb = 0 V), although
Ey decreases under the forward back biasing. In Fig. 7, the
large drain current is a main factor for the amount of the
HCI degradation. Meanwhile, Ey is considered to influence a
mechanism of the degradation. To evaluate the lifetime of this
forward-bias state, condition Vb = Vstress was used. Even under
this forward back-biasing condition, the lifetime is sufficiently
longer than ten years, as shown in Fig. 9.
Fig. 8. Simulated vertical electric-field strength Ey along the channel surface at forward, reverse, and no back biasing under the HCI stress.
Fig. 9. HCI lifetime of the SOTB NMOSFET under the forward back biasing
(i.e., worst case degradation). Fig. 11. Comparison between NBTI characteristics of the SOTB and bulk
PMOSFETs.
ACKNOWLEDGMENT
The authors would like to thank the staff at Renesas Elec-
tronics Corporation (Renesas) and Hitachi Central Research
Laboratory (HCRL) for fabricating the devices. The authors
would also like to thank T. Iwamatsu, H. Oda, and Y. Inoue
of Renesas for their assistance with the device fabrication, and
Fig. 13. Dependence of NBTI characteristics on the back bias Vb . K. Torii of HCRL and M. Odaka and K. Kasai of the Hitachi
Research and Development Group for their encouragement.
the gate bias (not by the back biasing). It is clear that the hole
concentration at the silicon surface is slightly influenced by the R EFERENCES
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and F.-L. Yang, “Novel 20nm hybrid SOI/Bulk CMOS technology with Jun. 2004, pp. 88–89.
0.183 μm2 6T-SRAM cell by immersion lithography,” in VLSI Symp.
Tech. Dig., Jun. 2005, pp. 16–17.
[10] S. Monfray, M. P. Samson, D. Dutartre, T. Ernst, E. Rouchouze,
D. Renaud, B. Guillaumot, D. Chanemougame, G. Rabille, S. Borel,
J. P. Colonna, C. Arvet, N. Loubet, Y. Campidelli, J. M. Hartmann,
L. Vandroux, D. Bensahel, A. Toffoli, F. Allain, A. Margin, L. Clement,
A. Quiroga, S. Deleonibus, and T. Skotnicki, “Localized SOI technology:
An innovative low cost self-aligned process for Ultra Thin Si-film on
thin BOX integration for Low Power applications,” in IEDM Tech. Dig.,
Takashi Ishigaki (M’01) received the B.E. and M.E.
Dec. 2007, pp. 693–696.
[11] F. Andrieu, O. Weber, J. Mazurier, O. Thomas, J.-P. Noel, degrees in electrical and electronic engineering from
Kobe University, Kobe, Japan, in 1999 and 2001,
C. Fenouillet-Béranger, J.-P. Mazellier, P. Perreau, T. Poiroux,
respectively.
Y. Morand, T. Morel, S. Allegret, V. Loup, S. Barnola, F. Martin,
In 2001, he joined the Compound Semiconductor
J.-F. Damlencourt, I. Servin, M. Cassé, X. Garros, O. Rozeau,
M.-A. Jaud, G. Cibrario, J. Cluzel, A. Toffoli, F. Allain, R. Kies, Division, Nippon Electric Company Corporation,
Otsu, Japan, where he was involved in the research
D. Lafond, V. Delaye, C. Tabone, L. Tosti, L. Brévard, P. Gaud,
and development of GaAs heterojunction field-
V. Paruchuri, K. K. Bourdelle, W. Schwarzenbach, O. Bonnin,
effect transistors (FETs) and heterojunction bipolar
B.-Y. Nguyen, B. Doris, F. Boeuf, T. Skotnicki, and O. Faynot,
“Low leakage and low variability ultra-thin body and buried oxide transistors for microwave applications. Since 2004,
he has been with the Central Research Labora-
(UT2B) SOI technology for 20nm low power CMOS and beyond,” in
tory, Hitachi Ltd., Tokyo, Japan, working on the research and develop-
VLSI Symp. Tech. Dig., Jun. 2010, pp. 57–58.
ment of high-capacity Flash memories, silicon-on-insulator complementary
[12] M. Khater, J. Cai, R. H. Dennard, J. Yau, C. Wang, L. Shi, M. Guillorn,
J. Ott, Q. Ouyang, and W. Haensch, “FDSOI CMOS with dielectrically- metal–oxide–semiconductor FETs, spin-transferred magnetic memories, and
III–V power devices.
isolated back gates and 30nm LG high-k/metal gate,” in VLSI Symp. Tech.
Mr. Ishigaki is a member of the IEEE Electron Devices Society.
Dig., Jun. 2010, pp. 43–44.
[13] T. Ishigaki, R. Tsuchiya, Y. Morita, N. Sugii, S. Kimura, T. Iwamatsu,
T. Ipposhi, Y. Inoue, and T. Hiramoto, “Wide-range threshold volt-
age controllable silicon on thin buried oxide integrated with bulk com-
plementary metal oxide semiconductor featuring fully silicided NiSi
gate electrode,” Jpn. J. Appl. Phys., vol. 47, no. 4, pp. 2585–2588,
Apr. 2008.
[14] M. Yoshimi, M. Takahashi, T. Wada, K. Kato, S. Kambayashi,
M. Kemmochi, and K. Natori, “Analysis of the drain breakdown mech-
anism in ultra-thin-film SOI MOSFET’s,” IEEE Trans. Electron Devices, Ryuta Tsuchiya received the B.S., M.S., and Ph.D.
vol. 37, no. 9, pp. 2015–2021, Sep. 1990. degrees in material science from the Tokyo Institute
[15] H. Yoshimoto, N. Sugii, D. Hisamoto, S. Saito, R. Tsuchiya, and of Technology, Tokyo, Japan, in 1993, 1995, and
S. Kimura, “Extension of universal mobility curve to multi-gate 1998, respectively.
MOSFETs,” in IEDM Tech. Dig., Dec. 2007, pp. 703–706. Since 1998, he has been with the Central Re-
[16] J. Chen, F. Assaderaghi, H.-J. Wann, P. Ko, C. Hu, P. Cheng, and search Laboratory, Hitachi Ltd., Tokyo, where he
T.-Y. Chan, “An accurate model of thin film SOI MOSFET breakdown has been engaged in research on the fabrication and
voltage,” in IEDM Tech. Dig., Dec. 1991, pp. 671–674. characterization of high-performance and low-power
[17] P. Heremans, R. Bellens, G. Groeseneken, and H. E. Maes, “Consis- metal–oxide–semiconductor field-effect transistors,
tent model for the hot-carrier degradation in n-channel and p-channel including thin-film silicon-on-insulator and buried
MOSFETs,” IEEE Trans. Electron Devices, vol. 35, no. 12, pp. 2194– oxide transistors.
2209, Dec. 1988. Dr. Tsuchiya is a member of the Japan Society of Applied Physics.
[18] N. Koike and K. Tatsuuma, “A drain avalanche hot carrier lifetime model
for n- and p-channel MOSFETs,” IEEE Trans. Device Mater. Rel., vol. 4,
no. 3, pp. 457–466, Sep. 2004.
[19] T. Ishigaki, R. Tsuchiya, Y. Morita, H. Yoshimoto, N. Sugii, and
S. Kimura, “HCI and NBTI including the effect of back-biasing in thin-
BOX FD-SOI CMOSFETs,” in Proc. Int. Rel. Phys. Symp., May 2010,
pp. 1049–1052.
[20] M. Nakai, S. Akui, K. Seno, T. Meguro, T. Seki, T. Kondo,
A. Hashiguchi, H. Kawahara, K. Kumano, and M. Shimura, “Dynamic Yusuke Morita received the B.S. and M.S. degrees
voltage and frequency management for a low-power embedded micro- in material engineering from Shonan Institute of
processor,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 28–35, Technology, Fujisawa, Japan, in 1999 and 2001,
Jan. 2005. respectively, and the Ph.D. degree from Tokyo Insti-
[21] S. Mahapatra, P. B. Kumar, and M. A. Alam, “Investigation and modeling tute of Technology, Tokyo, Japan, in 2004.
of interface and bulk trap generation during negative bias temperature Since 2005, he has been with the Central Research
instability of p-MOSFETs,” IEEE Trans. Electron Devices, vol. 51, no. 9, Laboratory, Hitachi Ltd., Tokyo, where he has been
pp. 1371–1379, Sep. 2004. working on the research and development of comple-
[22] N. Kimizuka, K. Yamaguchi, K. Imai, T. Iizuka, C. T. Liu, R. C. Keller, mentary metal–oxide–semiconductor devices includ-
and T. Horiuchi, “NBTI enhancement by nitrogen incorporation into ul- ing silicon-on-insulator metal-oxide-semiconductor
trathin gate oxide for 0.10-μm gate CMOS generation,” in VLSI Symp. field-effect transistors.
Tech. Dig., Jun. 2000, pp. 92–93. Dr. Morita is a member of the Japan Society of Applied Physics.
1204 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 4, APRIL 2011
Nobuyuki Sugii (M’08) received the B.S., M.S., and Shin’ichiro Kimura (M’87–SM’07) was born in
Ph.D. degrees in applied chemistry from the Uni- Miyagi, Japan, in 1955. He received the B.S. and
versity of Tokyo, Tokyo, Japan, in 1986, 1988, and M.S. degrees in materials science from Tohoku Uni-
1995, respectively. versity, Sendai, Japan, in 1978 and 1980, respec-
In 1988, he joined the Central Research Labo- tively, and the Ph.D. degree from the University of
ratory, Hitachi Ltd., Tokyo, where he was engaged Tokyo, Tokyo, Japan, in 1989. The subject of his
in the research and development of oxide super- Ph.D. dissertation was low-temperature oxidation of
conducting materials and devices until 1996 and silicon by microwave oxygen plasma.
has been working on the research and develop- Since 1980, he has been with the Central Research
ment of SiGe materials and complementary metal– Laboratory, Hitachi Ltd., Tokyo, where he was first
oxide–semiconductor devices, including silicon-on- involved in the research of high-dielectric-constant
insulator and strained-silicon metal–oxide–semiconductor field-effect transis- insulators. He then worked on the plasma oxidation of silicon. From 1986
tors, since 1996. From 1991 to 1994, he was a Research Scientist with to 1988, he worked on the process design and device characterization for
the Superconductivity Research Laboratory, International Superconductivity metal–oxide–semiconductor (MOS) dynamic memory for 16 Mb. From 1988
Technology Center. Since 2004, he has been also a Visiting Professor with the to 1989, he was a Visiting Research Associate with the University of Warwick,
Tokyo Institute of Technology, Tokyo. Coventry, U.K. He is currently a Chief Senior Researcher with Central Research
Dr. Sugii is a member of the Japan Society of Applied Physics and the IEEE Laboratory. His current research interests include new submicrometer MOS
Electron Devices Society. He was a member of the program subcommittees of field-effect transistor devices and processes.
the Solid State Devices and Materials Conference from 2002 to 2004. Dr. Kimura is a member of the Japan Society of Applied Physics and the
IEEE Electron Devices Society (EDS). He has served as a member of the
Solid State Devices and Materials Conference from 1995 to 1998. He was as a
member of the steering committee in 2003, the Program Chair in 2005, and the
Conference Chair in 2007 of the Symposium on Very Large Scale Integration
Technology Symposia. From March 2002 to 2007, he was one of the Editors
of IEEE TRANSACTIONS ON ELECTRON DEVICES. He has also served as the
Vice Chair of the IEEE EDS Japan Chapter. Since 2010, he has been the Chair
of IEEE EDS Tokyo Chapter.