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Chapter 1: Digital Background
Chapter 2: Semiconductor backgro
Index
Chapter 3: CMOS Processing
Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Chapter 4: CMOS Basics
STA & SI
Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics Chapter 5: CMOS Layout Design

Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6

Extraction & Featured Post
DFM Introductio Parasitic Interconnect Corner (RC Manufacturing Effects and Their Dielectric Process Other
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Implant P+ Impurities: CMOS P
5)
Tuesday, September 13, 2016
Implant P+ Impurities: CMOS Process
Chapter1 Chapter2 Chapter3 Chapter
Timing Arc
STA & SI:: Chapter 1: Introduction
1.1a 1.1b 1.1c 1.2a 1.2b
INTRODUC Timing Unate: Unateness of Complex Circuit: LIB File syntax for Logic Gates: LIB File syntax for Complex Circuit:
TION Arc Timing Arc Timing Arc Timing Sense Timing Sense

Before Understanding the Timing Arc, you have to consider the design from the "END USER" point of view. "END USER" doesn't mean only
person who are using the End Product (Like mobile Phone or Laptop etc), "END USER" can be anyone. It can be a user of any CHIP , or may be Vlsi expert
user of a particular IP/Macro or may be a user of a Standard Cell Library.
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Lets take an example of Standard Cell (assume NAND GATE). Ask yourself ... What all information you require, If you want to use NAND gate in
your design ? Be the first of your friends to like th

You may be interested to know -

How much time (may be in the form of Delay) it will take to respond for a particular Input ?
For a Particular Input (Rising or falling), What type of Output (output is rising or falling or no change) you will get ?

These questions are about the Normal Standard Cell (NAND Gate). But what about more complex circuit/CELL like Flip-Flop ( There will be more
Blog A
questions because it has more input and outputs in comparison to Normal NAND GATE.)
► 20
E.g For D Flip-Flop : There are ► 20
2 Input Pin (D and CLK) and ▼ 20
2 output Pin (Q and Q') and ►
2 asynchronous Pin (RESET and SET). ▼
VLSI EXPERT (vlsi EG)
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It means the number of Timing/Delay information are large in this case. Because there are so many input and output pins and their corresponding
►
combinations are also large in number. Apart of this there are so many dependency of output of one pin on other pin that it's not consider as Bridging Gap Between
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simple as NAND gate. In general, we are not interested what's going on inside the FlipFlop (Like how many NAND gates are there and how they ►
are connected), we are only interested to know ►
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How and when we will get the Output after applying a certain input. ►
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Is there any constraint and if yes, then what are those and on what pin. ►

► 20
So basically, in every case (normal combinational gate or a complex sequential circuit) "END USER" has only concern about the relationship
Total Pageviews ► 20
between different Pins/Port of a Product (like GATE, FLIP-FLOP, IP).
Note: They may have other concern also, but right now we are talking about Concerns only related to Timing. :) ► 20
5,787,869 ► 20
To answer these questions, we do a lot of experiment (Technical Terminology : Characterization or say Simulation) and come up with a
► 20
relationship between different Pins in terms of Timing numbers (which is more commonly known as Timing arcs).
► 20
Timing Arc represent the timing relationship between 2 Pins of any element or Block or any boundaries. Basically it represent the timing ► 20
characteristic of the element or block or Boundaries.
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EDN:
Timing arc has a Start-point and an Endpoint.
Posts
The start-point can be an Input, output or inout. Fo
ve
The End is always an output pin or an inout pin (with few exception). Comments
two
Most of the Time arc Endpoint is always an output pin. But there are few cases where it can be input pin. So
ve
These are constraint timing arc. Like Setup, Hold, Recovery or Removal constraint. These are between input to input pins Popular Posts
Im
ma
"Timing Paths" : Static
On the basis of above understanding, I can say that Timing Arc can be Timing Analysis (STA) es
basic (Part 1) As
Delay Arc po
Constraint Arc Basic of Timing SA
Analysis in Physical mi
Design ap
 Re
Lets consider the Below System, where there are 4 input X1- X4 and 1 output Y1. You can see that there are 4 Arcs between Input pins and "Setup and Hold Time" fixe
: Static Timing Analysis be
output pin. For better understanding we named these as "Input to output Timing Arcs".
(STA) basic (Part 3a) sig

"Examples Of Setup
and Hold time" : Static
Timing Analysis (STA)
basic (Part 3c)

"Setup and Hold Time

Violation" : Static
Timing Analysis (STA)
basic (Part 3b)

Delay - "Wire Load

Model" : Static Timing
Analysis (STA) basic
(Part 4c)

Now this is just a small block and End user don't want to know anything about this (what's inside this), if we provide the information about these Delay - "Interconnect
Delay Models" : Static
Input-to-output Timing Arcs. But if we will see what's inside, then it may have Nets and Gates or Cells.
Timing Analysis (STA)
basic (Part 4b)

"Time Borrowing" :
Static Timing Analysis
(STA) basic (Part 2)

10 Ways to fix SETUP

and HOLD violation:
Static Timing Analysis
(STA) Basic (Part-8)

5 Steps to Crack VLSI

Interview

From above figure, you can easily realized that Timing arc can be for NETS also. Now, I can say very easily that Timing arcs can be divided into Recent Visitors

Net Arc
Followers
Cell Arc
Followers (480) Next
Combinational Cells
Sequential Cells

Note: Macro / Custom Blocks also designed using the cells and Nets. So these custom Blocks are again similar to the system/blocks
as shown in above figures. Only difference will be that it’s small in size.

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In the Next Article, we will discuss how Timing Arc will help you to Answer your questions. We will also discuss more about the Cell Arc and Net
Arc. We will also try to capture, how these information is captured in Timing Library.

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Unateness of Proper Assessment Antenna Effects

Complex Circuit: With detailed
Timing Arc Feedback is
missing for ...

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Posted by VLSI EXPERT at 12:58 PM

Reactions: Excellent (19) Good (1) Interesting (0) Need More (1)

9 comments:
Mallikarjuna Reddy Ankinapalli September 14, 2016 at 8:25 PM
Very much appreciated. Simple yet thoughtful explanation
Reply

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