design

Edited by Bill Travis and Anne Watson Swager

ideas
Equal-element filter improves
passband performance
Richard M Kurzrok, RMK Consultants, Queens Village, NY
esigners originally conceived

D equal-element filters as all-

pole microwave bandpass
filters that provide minimum center-fre-
Figure 1
L1=1 L2=1 L3=1 L4=1

quency insertion losses for specific values

of resonator-unloaded Q (Reference 1). C1=1 C2=1 C3=1 C4=1 C5=1
All resonators of the equal-element
bandpass filter operate at the same loaded
Q. For LC filters, the equal-element filter
has another advantage. In the lowpass (a)

prototype, all inductors have the same L1=1 L2=1 L3=1 L4=1
value, and all capacitors have the same
value. This minimum number of circuit
elements provides design simplicity and C1=0.5 C2=1 C3=1 C4=1 C5=0.5
reduces filter cost.
However, the equal-element filter’s re-
sponse shape has one severe shortcom-
ing. Passband amplitude ripples, due to (b)

reflection, are unacceptable for some ap-

plications. In minimum-phase-shift filter The equal-element lowpass filter can feature unacceptable passband ripple for some applications
circuits, group-delay ripples that pre- (a). A modified filter realizes substantial improvement in passband performance with some reduc-
clude equalization accompany the am- tion in stopband selectivity (b).
plitude ripples. At microwave frequen-
cies, modifying the central resonator of a five-pole bandpass filter leads to im- filter and a nine-pole, modified, equal-el-
proved performance (Reference 2). ement, lowpass filter with inductor-un-
Figure 1a shows the schematic of a loaded Qs of 100.
Equal-element filter improves
nine-pole, equal-element, lowpass-filter The reference frequency, at normalized
passband performance..............................123
prototype. Figure 1b shows a compara- frequency x51.0, is not the 3-dB cutoff
Test batteries without a ble schematic of a modified lowpass-fil- frequency for the filters in Figure 1. The
voltmeter, part 2 ..........................................126 ter prototype. By altering the filter input 3-dB cutoff frequency occurs close to
SCR phase control yields and output capacitors, the modified fil- x51.9. This feature differs from Butter-
solid-state switch..........................................128 ter realizes substantial improvement in worth and Chebyshev filters, for which x
passband performance with some reduc- can equal 1.0 at 3-dB cutoff frequencies.
Circuit facilitates video fading ..................130 tion in stopband selectivity. In the mod- You use this normalization for equal-el-
Time-delay relay uses ified equal-element design, all filter in- ement and modified equal-element de-
proximity control ..........................................132 ductors are still equal in value, and you signs to calculate the values of the circuit
Circuit forms shaping amp
need only two capacitor values in a con- elements.
and amplitude detector..............................134
venient 2-to-1 ratio. Table 1 shows com- A nine-pole, modified, equal-element
parative theoretical amplitude responses lowpass filter was designed at a reference
for the nine-pole, equal-element lowpass frequency FR of 4.681 MHz, for which

www.ednmag.com March 15, 2001 | edn 123

design
ideas

TABLE 1—THEORETICAL AMPLITUDE RESPONSES FOR NINE-POLE, TABLE 2—MEASURED AMPLITUDE

EQUAL-ELEMENT AND MODIFIED, EQUAL-ELEMENT, LOWPASS FILTER RESPONSE FOR NINE-POLE,
MODIFIED, EQUAL-ELEMENT,
Insertion loss Insertion loss of LOWPASS FILTER
Normalized Frequency of equal-element modified equal-element
Frequency (MHz) Insertion loss (dB)
frequency (MHz) lowpass filter (dB) lowpass filter (dB)
2 0.1
0 0 0.172 0.172
4 0.15
0.1 0.468 0.185 0.172
5 0.2
0.2 0.936 0.202 0.174
5.5 0.25
0.3 1.404 0.201 0.176
6 0.3
0.4 1.872 0.212 0.178
6.5 0.4
0.5 2.341 0.315 0.182
7 0.6
0.6 2.809 0.532 0.184
7.25 0.85
0.7 3.277 0.739 0.186
7.5 1.15
0.8 3.745 0.74 0.192
7.75 1.4
0.9 4.213 0.475 0.215
8 1.5
1 4.681 0.259 0.27
8.1 1.1
1.1 5.149 0.707 0.345
8.2 0.8
1.2 5.617 1.777 0.386
8.3 1.5
1.3 6.085 2.546 0.337
8.4 1.1
1.4 6.553 2.167 0.258
8.5 0.8
1.5 7.022 0.664 0.462
8.6 1.25
1.6 7.49 1.849 1.191
8.7 0.75
1.7 7.958 5.52 1.84
8.8 1.25
1.8 8.426 5.91 1.124
8.9 2.4
1.9 8.894 3.574 2.887
9 4
2 9.362 19.255 12.533
9.25 9.2
2.1 9.83 28.937 20.678
9.5 13.7
2.2 10.298 36.285 27.288
10 21.9
2.3 10.766 42.426 32.953
11 34.6
2.4 11.234 47.794 37.977
12 to 30 Greater than 45
2.5 11.703 52.612 42.53
2.6 12.171 57.011 46.715
2.7 12.639 61.075 50.604 You can transform the modified,
Note: Data is for inductor-unloaded Qs of 100. equal-element, lowpass prototype into
useful highpass and bandpass filters with
x51. For 50V input and output imped- 0.53C05340 pF. In the actual filter, the similar design features.
ances Z0, you calculate the normalizing input and output capacitors are standard
inductance, L0, and normalizing capaci- 330-pF values. The nine-pole, modified, References
tance, C0, as follows: equal-element, lowpass filter was con- 1. Taub, JJ, “Design of Minimum Loss
structed in a die-cast aluminum box with Band-Pass Filters,” Microwave Journal,
Z0
L0 = = 1.7 µH; BNCs. The filter circuit was fabricated us- Volume 6, pg 67, November 1963.
2 π • FR ing vector board. All capacitors were 5%- 2. Bawer, R, and G Kefalas,“A Modified
tolerance polypropylene units. All induc- Equal-Element Band-Pass Filter,” IRE
1 × 1016 tors used 18 turns of number 26 magnet Trans MTT, Volume MTT-5, pg 175, July
C0 = = 680 pF. wire on Micro Metals’ T37-2 toroids. 1957.
2 π • FR Z 0
Table 2 shows the measured amplitude-
You then use these values of L0 and C0 response data. The measured data pro-
to denormalize the filter to actual circuit- vides reasonable correlation between the-
element values. Filter inductors L1, L2, L3, ory and experiment and shows sub-
and L4 are equal to L051.7 mH. Interior stantial improvement in amplitude re-
filter capacitors C2, C3, and C4 are equal sponse over most of the filter passband Is this the best Design Idea in this
to C05680 pF. The filter input and out- with some degradation in stopband per- issue? Vote at www.ednmag.com/edn
put capacitors, C1 and C5, are equal to formance. mag/vote.asp.

124 edn | March 15, 2001 www.ednmag.com

design
ideas
Test batteries without a voltmeter, part 2
Harry Gibbens Jr, PowerStream Technology, Orem, UT

rom a high-volume- 1, using the rearranged formula. An ex-

F production
point of view
Figure 1
of the Design Idea “Test bat-
BATTERY
R0
VCC

4 _
VCC

3
2
1k
VCC
ample follows:
 1.55V 
R FORM1 = 182 kΩ
 6V 

teries without a voltmeter” IC
HOLDER 5 + 1A
1.55V
(EDN, Nov 9, 2000, pg 167), +
12 = 182 kΩ(0.2583)
it is a time-consuming and R1 6 _ 1k
= 47.01 kΩ.
1
laborious task to tweak the 1 IC
7 + 1B
1.50V
large number of poten- Next, calculate the first resistance val-
tiometers on each of the R2
8 _
ue, R0, by using the formula
1k
comparator input refer- IC
9 + 1C
14
ences. An alternative to this 1.45V
 V 
onerous adjustment chore is R3 R X = R TOT1R TOT  X  = R TOT1R FORMX
10 _ 1k  V TOT 
to replace all potentiometers 13
11 IC 1D
with 1%-tolerance fixed re- 1.40V +  1.55V 
R 0 = 182 kΩ 1182 kΩ  
sistors (Figure 1). Before cal-  6V 
R4 4 _
culating each voltage-refer- 2
1k
= 182 kΩ 1182 kΩ (0.2583)
5 IC 2A
ence resistance value, you 1.35V +
= 182 kΩ147.01 kΩ
should use a reasonable se- = 134.99 kΩ.
R5 6 _
lected total resistance value, 1
1k
RTOT, ranging from 100 kV 7 IC+
2B
1.30V
to 1 MV. You can usually ob- Calculate the rest of the resistor values,
R6
tain each of the resistance- 8 _ 1k R1 through R7, by using the formula
IC 14
divider values from off-the- 1.25V
9 + 2C
shelf fixed resistors. After  V  V 
calculating all the resistance- R7
VCC
R X +1 = R TOT  X 1R TOT  X +1  =
10 _ 3 1k  VTOT   VTOT 
divider values (with RTOT5 11 IC 1A
13
1.20V +
12 R FORMX1R FORMX +1.
100 kV), if the closest rea- NOTES:
R8 VCC=6V.
sonable stock values are un- IC1, IC2=LM339.
available, just increase the R0 TO R8: SEE TABLE 1. For example, for R1:
value of RTOT. For the exam-
ple in Figure 1, you calculate Fixed, 1%-tolerance resistors eliminate the need to trim poten-
 1.55 V   1.5V 
the values using a spread- tiometers in this battery-testing circuit. R1 = 100 kΩ 1100 kΩ 
 6V   6V 
sheet to obtain quick results.
This example uses RTOT5182 kV. All the manually selected value. The first step is = 1.51 kΩ.
calculations use Kirchoff ’s law: to calculate the “Formulated R” in Table Finally, use the rearranged formula to

 RX  TABLE 1—CALCULATED VALUES FOR BATTERY TESTER

VX = VTOT  .
 R1 + R 2  Reference Voltage Formulated R Calculated R Fixed R
voltage (V) V
kV RX V
kV V
kV
VTOT 6 RTOT 182
Rearranging the terms in the formula,
VREF1 1.55 0.26 47.01 R0 134.99 134.5
you determine the resistance value, RX:
VREF2 1.5 0.25 45.5 R1 1.51 1.5
VREF3 1.45 0.24 43.99 R2 1.51 1.5
 V 
R X = R TOT  X  , VREF4 1.4 0.23 42.46 R3 1.53 1.54
 VTOT  VREF5 1.35 0.23 40.95 R4 1.51 1.5
VREF6 1.3 0.22 39.44 R5 1.51 1.5
VREF7 1.25 0.21 37.91 R6 1.53 1.54
where VX is each comparator’s reference
VREF8 1.2 0.2 36.4 R7 1.51 1.5
voltage, VREFX; VTOT5VCC; and RTOT is the
R8 36.4 36.4

126 edn | March 15, 2001 www.ednmag.com

design
ideas
find the last resistance value, R8. calculated resistance value (Calculated R) mag.com. Click on “Search Databases”
to the nearest available fixed-resistor val- and then enter the Software Center to
 1.2V  ue (Fixed R) as shown in the last two download the .gif file for Design Idea
R 8 = 182 kΩ  = R FORM 8
 6V  columns. Note that R0 consists of two se- #2654.
= 36.4 kΩ. ries-connected resistors. You can down- Is this the best Design Idea in this
load the table of 1%-tolerance resistor issue? Vote at www.ednmag.com/edn
In Table 1, you match the rounded-off values from EDN’s Web site, www.edn mag/vote.asp.

SCR phase control yields solid-state switch

James Keith, York, PA
CRs (silicon-controlled

S rectifiers), or thyris-
tors, have higher
current and voltage ratings, low-
F i g u r e

115V
1
LOAD

150
0.5W
12V 1k 1N4002
er conduction losses, and more AC 22 1 mF
robustness than triacs. For these 0.1 mF
600V
reasons, SCRs are better suited 2N6027
to high-power applications. For SNUBBER
example, you can use two SCRs 1k
PHOTOMOD
to configure a 100 or 200A, 460V 1k VOLTAGE
100k ADJUST
control circuit. Table 1 lists some 0.5W 100k
SCR DOUBLER
of the advantages of SCRs over 0.5W
triacs. The main challenge is
driving the SCRs: You now have
two gates, rather than one, to 22 2N6027

drive. Furthermore, the gates are 1mF

1k 1N4002
referenced to opposite polarities 12V
with a significant voltage differ-
ence. The circuit in Figure 1
solves the problem with two This SCR phase-control circuit uses one potentiometer and no pulse transformers.
PUTs (programmable unijunc-
tion transistors), one connected to each can obtain 230V operation by using 1.5- a 100-kV, 25W potentiometer. Using the
SCR. Performance is good because the to 2-mF timing capacitors. You can circuit as a solid-state switch is practical;
circuit does not “fold back” as inexpen- achieve 460V-ac operation by using simply replace the voltage-adjust block in
sive triac phase controls (dimmers) do. 1200V SCRs; 3-mF timing capacitors; and the broken lines in Figure 1 with a pho-
The PUT fires when the tim- tomod. A photomod is a
ing-capacitor voltage exceeds TABLE 1—SCR-VERSUS-TRIAC COMPARISON unique type of photocoupler
the PUT reference voltage by Device SCR Triac
that has an LED or incan-
one diode drop and dumps Current rating >>50A <40A
descent-light source and a
the capacitor’s charge into Conduction voltage drop ~1V ~1.5V
cadmium-sulphide photo-
the SCR gate. Junction temperature 12588C 11588C
cell. Unique properties of
You adjust the phase delay Thermal resistance Low Medium
these photocells are their
by varying the charge rate of Maxium voltage 1400V 600V
high dark resistance and
the capacitor via the poten- Surge current High Limited
high voltage ratings.
tiometer. You can enhance Robustness High Low
the balance by matching Is this the best Design Idea
1
Package Doubler or "hockey puck" /4-in. stud in this issue? Vote at www.
both the zener-diode volt- Isolation Isolated Nonisolated
ages and the values of the ednmag.com/ednmag/vote.
Number required Two One asp.
charging capacitance. You
128 edn | March 15, 2001 www.ednmag.com
 design
ideas
Circuit facilitates video fading
JM Terrade, Clermont-Ferrand, France
hen you’re copying videotapes, tiometer. In the second path, the syn- amplifier, which provides the video out-

W it’s sometimes desirable to sup- chronization pulse, separated from the put.
press some passages. Using the input signal, connects to the other end of When you adjust P1’s wiper from one
pause control of the recorder does not the potentiometer. The wiper of the po- end to the other, the video image disap-
yield satisfactory results. Another tentiometer connects to the second video pears and fades to a black screen. Because
method produces better results P1 and P2 are ganged, the sound
(Figure 1). The video source con- follows the image brightness.
nects to the video-in plug, and the AMPLIFIER
32
The circuit could have used
recorder connects to the video-out triple integrated video ampli-
FULL IMAGE
plug. Turning potentiometer P1 ad- fiers, such as an AD813, and a
justs the image brightness from VIDEO IN
P1 AMPLIFIER
VIDEO OUT video sync separator, such as an
normal video to a black image. K1 32
K2 LM1881. However, these ICs are
With the P2 potentiometer ganged expensive (approximately $25)
to P1, the sound also varies accord- BLACK IMAGE compared with the six standard
SYNC
ingly. The objectives in building SEPARATOR transistors shown in Figure 2.
this circuit are to use inexpensive, R1 sets the input impedance at
readily available components and 75V. Q1, Q2, and associated
SOUND IN
to obtain batteryless operation. K1
components form a video am-
SOUND OUT
The video signal follows P2 plifier with an approximate gain
two paths (Figure 2). In the Figure 1 K2
of two. R2, R3, and D1 set the dc
first path, the signal undergoes am- voltage, and C1 blocks any dc
plification by a factor of two and A simple circuit provides for effective video and audio fading voltage from the source. The
connects to one end of a poten- when you’re recording source material. amplified video signal connects
R7
10 R8
5V 10
2N2907A 5V
Q2 + C7 Q6
1k +
Figure 2 R3 1 mF
330 2N2907A C8
470 1 mF
1N4148 1N4148
4.7 mF Q5
+

D1 Q1 2N2369A
+ 2N2369A R4
R2 C1 180 +
330 3.3k
390 4.7 mF 12 pF 330 10 pF

R7 75
150 MAXIMUM
560 5V
P1 100
C2 2
+

470 pF 10k VIDEO OUT

P4
1 4.7 mF 1k
1k
Q3 MINIMUM
VIDEO GROUND C6 2N2907A R6
0V
K1 K2
VIDEO 1.5k P3 VIDEO
21 R5 100 nF 21
20 IN 2 GROUND 20
19 470 19
18 1k 18
17 R1 470k 17
16 Q4 1 16
15 75 1k 2N2369A 15
14 14
13 13 12
12
11 11 10
10
9 SWITCHING LEVEL SWICHING LEVEL 9
8 8
7 7
6 6
5 5
4 4
3 SOUND IN LEFT 3
+

2 2
1 P2 SOUND OUT 1
C2 2
1 mF 10k
VIDEO IN VIDEO OUT
SOUND GROUND 1 SOUND GROUND
5V
9 TO 12V 1k
IN OUT
IC1
+ C4 78M05 C5 +
D2
C3 C6
100 nF 100 nF
1 mF GND 1 mF LED

A handful of transistors and associated components yields a professional-quality video fader.

130 edn | March 15, 2001 www.ednmag.com

 design
ideas
to P1 through R4 and the C1 dc-blocking
capacitor. R5, Q3, Q4, and associated com-
ponents form a sync separator. The sync
pulse connects to the bottom of P1
through R6 and P3, an adjustable voltage
divider. The wiper of P1 connects to the
second video amplifier comprising Q5,
Q6, and associated components. You can
adjust the amplification with P4. R7 sets
the output impedance at 75V.
P2, ganged to P1, is a simple voltage di-
vider, using C2 to block dc voltages. The
sound input uses the left channel, and the
output goes to both the left and right
channels. With a video source connect-
ed to video in, a dc voltage of 9 to 12V ap-
pears at Pin 8 of the video plug. IC1 and
the C2 through C6 capacitors derive pow-
er from this pin and provide a stable 5V
for the circuit. D2 is a high-brightness
LED that indicates that a video source is
present. R7, C7, R8, and C8 provide de-
coupled supplies for the amplifiers.Video
cables are often of poor quality. For that
reason, the circuit in Figure 2 provides
for amplification of the video signal. Also,
compensation of the first amplifier pro-
vides amplification of color burst with a
concomitant improvement of video
quality. To adjust the circuit, first turn P1
fully clockwise and then adjust P4 for a
good video image. Then, turn P1 fully
counterclockwise and adjust P3 to obtain
a stable black image.
Is this the best Design Idea in this
issue? Vote at www.ednmag.com/edn
mag/vote.asp.

Time-delay relay uses proximity control

Dennis Eichenberg, Parma Heights, OH
ou can build a circuit that allows to 1•1(R31R4)(C3). The period is ad- tive when IC2 drives relay K1 on. Lamp

Y a passerby to briefly operate model

trains in a display window (Figure
1). The design uses a proximity detector
rather than a pushbutton switch to elim-
inate the need to mount and wire any
equipment outdoors. The circuit worked
well in this application and other appli-
cations. The heart of the circuit is the
quad CMOS NAND gate, IC1. A human
hand near the sensor induces 60-Hz pow-
er-line noise into IC1A, and this IC trig-
gers IC2. IC2 is configured as a mono-
stable multivibrator, with a period equal
justable from approximately 0.5 to 50 sec.
The sensitivity of the circuit depends on
the size of the sensor. A 10-in.-sq piece
of screen mounted inside the display
window works well for this application,
because it permits complete visibility
through the sensor. The circuit triggers
several inches away from the window in
this application.
You can manually or automatically op-
erate the circuit through the single-pole,
double-throw, center-off switch, S1. In
automatic operation, receptacle J1 is ac-
LP1 indicates when the load is active.
Lamp LP2 indicates when the circuit is in
automatic mode. J1 is active whenever S1
is in the on position, as LP1 indicates. VCC
for the circuit comes from transformer
T1, rectifier D1, and filter capacitors C1
and C2. The load rating for the circuit de-
pends on the selection of fuse F1, switch
S1, relay K1, and receptacle J1.
Is this the best Design Idea in this
issue? Vote at www.ednmag.com/edn
mag/vote.asp.

Figure 1 F1
S1
K1
AUTO
2A 12V DC D1
T1 50PIV, 1A
OFF
120-TO-12
P1
120V AC ON 1 + VCC
LP1 LP2
120V 120V + C1 C2
100 mF 0.01 mF
LOAD J1
120V AC ON AUTO

10-IN.-SQ VCC
SCREEN OR R3
PLATE 100k

V 5
IC1B 4
R1 R4 8 6 4011
VCC 3
2.2M 1 1M 5 OUT
IC1A 3 CONT 8
2 4011 6 IC2 7 IC1C 10
THRE NE555 DIS 9 4011
2 D1
R2 TRIG
4 1 1N4001 12
6M RESET GND IC1D 11
+ C3 C4 13 4011
5O mF 0.05 mF

A proximity sensor turns a load on when a human hand comes near the sensor screen.
132 edn | March 15, 2001 www.ednmag.com
 design
ideas

Circuit forms shaping amp and amplitude detector

Elio Rossi, ITESRE-CNR, Bologna, Italy
he use of solid-state detectors

T connected to charge ampli-

fiers requires appropriate
conditioning of the output signals, be-
Figure 2

cause of the signals’ long decay time.

Moreover, you must “stretch” the peaks of
the shaped pulses for a period sufficient
for A/D conversion. For a single detec-
tor, you can use a relatively expensive
module. For a large detector array, you
need to develop an ASIC. For a moder-
ate number of detectors, you can use an
inexpensive circuit that handles an array
of 19 drift diodes connected to a scintil-
lating crystal of cesium-iodide (Figure
1). The two ICs, an OP37 and an AD823,
provide the correct gain and the semi-
gaussian conditioning of the input puls-
es. The conditioning involves a differen-
tiating input with pole-zero adjust in the At the AD823 output in Figure 1, the signal peaks in 6 msec. A peak detector then “stretches” the
gain-of-35 first stage, a lowpass Sallen- signal.

100k 1M
Figure 1 VTHRESH 10k

GAIN 10k 12
11 PKD01
ADJUSTMENT 2
56k 15k CMP
+
VCC 10
100 pF VCC 10k STRETCHED
5k 5
1k 2 SIGNAL
AD823 A + 3
+/2 IN 2.2 nF 5.1k C
2 7 22k 22k 8 + 10k +
+ 2 7 6 2
6 + 1 5.1k 1/2
3 OP37 3 21/2 2 9
2 4 +/2SELECT 2
22k 4 SHAPED B
OUT +
8 VCC1VCC GND
10k
PZ 2VCC 1 14 4 2 7 13 10k
ADJUSTMENT 2VCC 22 pF
15k
220 pF
4.7k CH 470
pF

330
pF
VTHRESH
212VCC 2VCC
12VCC VCC 5V
+
10 mF 78L05 IN IN GND OUT 5V
+ 5k
RESET RTP LOG TRIG LOG
GND

A few linear ICs form the basis of a shaping amplifier and peak-amplitude detector.

134 edn | March 15, 2001 www.ednmag.com

design
ideas
Key filter in the unity-gain second stage,
and a gain-adjustable third stage.
Figure 3
Figure 2 shows a peaking time of
6 msec with a gain of 50 to 100V/V. The
circuit can use either a positive or a neg-
ative input signal.
The third IC, a PKD01, acts as a
“stretcher” circuit with a built-in trigger
discriminator. To measure the perform-
ance of the circuit, the design uses four
external one-shot multivibrators, a pre-
cision pulse generator, and a multichan-
nel analyzer in sample mode. The dis-
criminator output triggers the sequence
of the one-shots, which in turn open the
in reset and close the in rise-time-pro-
tection, gated amplifiers, A and B (fig-
ures 1 and 3). This action allows the hold
capacitor to reach the peak of the inte- In the second waveform down, the peak detector provides a sample/hold function and preserves
grated (via the 10-kV, 330-pF network) the peak value of the signal.
input pulse, so that an A/D converter can
begin its conversion. The circuit must command and the peak of the input ing time of the input signal to obtain a
maintain the stretched signal via the re- pulses to maintain the linearity of the stretched signal output greater than 5V.
set pulse until the end of conversion. In- low-level signal. Also, the approximately Is this the best Design Idea in this
put integration is necessary to generate 0.7V/msec slew rate of the stretched out- issue? Vote at www.ednmag.com/edn
a delay between the aperture of the reset put requires at least 8 msec in the peak- mag/vote.asp.

136 edn | March 15, 2001 www.ednmag.com