CYCLE 2 EXPERIMENT ( EXPT 5 TO 8) P A G E | 1 OF 18

EXPERIMENT 5:- DESIGN OF TWO STAGE RC COUPLED AMPLIFIER

Aim :- To design a two stage RC coupled BJT amplifier and to determine frequency response.

Components & Equipments required :- Bread board, resistors ( 9nos as per design), capacitors
(5nos as per design),NPN Transistor (2 nos SL 100 or eqt) Regulated DCsupply ( 0-30V dc,1no.), Signal
generator(10Hz to 1 MHz), Decade Resistor Box, CRO, multimeter, wires, probes.

Theory: -In a capacitor coupled two stage amplifier circuit,, each stage is similar to the single stage circuit.
Stage-1 is connected to stage-2 via the coupling capacitor. The signal is applied at stage-1 and the load is
coupled to the output of stage-2. The signal is amplified by stage-1, and the output of stage-1 is amplified
again by stage-2, so that overall voltage gain is much greater than the gain of a single stage. The other
advantage of two stage amplifier is no phase shift in the output voltage. As the signal voltage is phase
shifted by through 180 degree by stage-1 and through a further 180 degree by stage-2, the overall phase
shift from input to output is 360 degree or zero degree.
Design of all the components except emitter bypass capacitors is similar to the single stage amplifier .
Negative feedback is introduced by the unbypassed first stage emitter bypass capacitor to reduce the gain of
the first stage.

Procedure:- To find, maximum undistorted gain, frequency response, refer the procedure given in single
stage amplifier.)

1. Draw and study the circuit,

2. Place the components on bread board and connect them as per given fig a. Use the wires for
connection as required.
Note: Measure the DC values of VCE, VBE, I C for both stages and ensure that they are close to the
designed values, before connecting the function generator, coupling capacitors and bypass
capacitor.

3. To find gain – frequency response: Find the max undistorted voltage gain for both stage separately.
Then find the overall gain with combined two stage. Find the overall frequency response.
1. No Load Gain for stage 1(Av1):- Measure the max undistorted voltage gain for stage 1
without load and ( For this remove the connection between CC2 and base of Q2.)
2. No Load Gain for stage 2(Av2):- Measure the max undistorted voltage gain for stage 2 ( For
this remove the connection between CC2 and collector of Q1 and connect the input signal to
disconnected CC2 end.
3. Gain for two stage (Avt):- Connect the CC2 connection and measure the max undistorted
voltage gain for complete circuit. ( For this, connect signal generator at CC1 and measure Vo
at CC3.) Note:- Also note down the output of stage 1 with two stage connected.
4. Overall frequency response:- Find the overall frequency response of the system. And find the
bandwidth.

Staff :- KRS , 3rd Sem Telecommunication Department, Session :- Aug10-Dec10,

 CYCLE 2 EXPERIMENT ( EXPT 5 TO 8) P A G E | 2 OF 18

Result:- The performance of two the RC Coupled Amplifier was designed and verified that the output
waveform is in phase with input signal.
Also find the gain of individual stages and verified that overall gain is the sum of dBAv1 and dBAv2.

Sl.No Vi in mV Vo in V Gain Avm =Vo/Vi Gain in dB =

20 log (Vo / Vin)
1 Stage 1 only

2 Stage 1 with second

stage connected
3 Stage 2 only

4 Stage 2 with second

stage connected
5 Overall Two stage

Staff :- KRS , 3rd Sem Telecommunication Department, Session :- Aug10-Dec10,

 CYCLE 2 EXPERIMENT ( EXPT 5 TO 8) P A G E | 3 OF 18

Work sheet :

Circuit diagram:-

Design:-

Bias circuit design:

Given: VCC = 10V, VCE = 5V, IC = 2m  = 100 (assumed)

Assume VBE = 0.7V for silicon diodes
VE = 10% of Vcc = 1V
Assume IE ~ IC
RE = VE /IE = 1V/ 2mA = 500Ω (use R8 = 470 Ω, R4= 100 Ω R9 = 330 Ω)
Rc =(Vcc- VCE -VE) / IC=( 10-5-1 ) / 2mA =2 k.(Use 2.2kΩ for R3 &R7)
V 2 =V B = VE + VBE = 1+0.7 = 1.7V
βR E ≥ 10 R 2
R 2 = (βR E)/10 = 5kΩ (use R2 & R6 as 4.7k Ω)
V1 = Vcc – V2 = 10-1.7= 8.3V
V1/ V2 = R1 / R2
R1 = (V1/ V2) * R2 = 22.9kΩ (use 22 kΩ R1 and R5)
Cc = 1-10 F, CE = 22 or 47F
Observation :-

I. Biasing Values :-

Staff :- KRS , 3rd Sem Telecommunication Department, Session :- Aug10-Dec10,

 CYCLE 2 EXPERIMENT ( EXPT 5 TO 8) P A G E | 4 OF 18

For stage1 Biasing values VCE1= VBE1= VRC1= So Ic1 = VRC1 / Rc1 =

For stage2 Biasing values VCE2= VBE2 = VRC2= So Ic2 = VRC2 / Rc2=

II Voltage Gain :
For stage 1 only Vin = Undistorted Max Vout = Avm = Vout/Vin =

For stage 2 only Vin = Undistorted Max Vout = Avm = Vout/Vin =

Combined two stage Vin = Vo1 = Undistorted Max Vout , Vo2 =

Av1 with combined stage = Vo1/Vin = Av2 with combined stage = Vo2/Vo1

Over all Gain = Vo2/Vin

Sl.No Vi in mV Vo in V Gain Avm =Vo/Vi Gain in dB =

20 log (Vo / Vin)
1 Stage 1 only

2 Stage 1 with second

stage connected
3 Stage 2 only

4 Stage 2 with second

stage connected
5 Overall Two stage

Staff :- KRS , 3rd Sem Telecommunication Department, Session :- Aug10-Dec10,

 CYCLE 2 EXPERIMENT ( EXPT 5 TO 8) P A G E | 5 OF 18

III Frequency Response:- Table 1 – Frequency response measurement

Vin = ------- Volts ( Peak to Peak)

Input freq Vo (p-p) Av=(Vo/Vin Avdb=20log(Av) Input freq Vo (p-p) Av=(Vo/Vin) Avdb=20log(Av)

10 Hz 7 kHz
20 Hz 8 kHz
30Hz 9 kHz
40Hz 10 kHz
60 Hz 20kHz
70Hz 30kHz
80Hz 40kHz
90Hz 50kHz
100 Hz 60kHz
200Hz 70kHz
300Hz 80kHz
400 Hz 90kHz
500Hz 100kHz
600Hz 200kHz
700Hz 300kHz
800Hz 400kHz
900Hz 500kHz
1 kHz 600kHz
2 kHz 700kHz
3 kHz 800kHz
4 kHz 900kHz
5 kHz 1MHz
6 kHz 2MHz

Name & USN of student:-

Staff sign with date:-

Marks:-
Staff :- KRS , 3rd Sem Telecommunication Department, Session :- Aug10-Dec10,
 CYCLE 2 EXPERIMENT ( EXPT 5 TO 8) P A G E | 6 OF 18

EXPERIMENT6:- VOLTAGE SERIES NEGATIVE FEED BACK AMPLIFIER

Aim :- Design of a BJT voltage series feed back amplifier and determine frequency response, input and output
impedance and compare the results with open loop values.

Components & Equipments required:- Bread board, resistors ( 10nos as per design), capacitors
(5nos),NPN Transistor (2 nos SL 100 or eqt) Regulated DC supply ( 0-30V dc,1no.), Signal generator(1 no, 10Hz to
1 MHz), CRO, multimeter, wires, probes.
Theory :- In a Negative feedback amplifier, a small portion of the output is fed back to the input. The feedback
quantity is applied in opposition to the signal so that the effective input is reduced. The proper use of negative
feedback is the significant improvement in the frequency response and in the linearity of operation of the feedback
amplifier compared with that of the amplifier without feedback. The other advantage of negative feedback is it
increases the input resistance and decreases the output resistance of the amplifier.

Input (Vs) Vi Vo
Av

Voltage
sampling
Vf β

Series addition at
input Fig b :- A typical Voltage series feedback amplifier.

The gain without feedback AV = V0/Vi.

The gain with feedback AVf = V0/VS
Feedback factor β = V0/Vf = RF2/Rf1
We have: Vi = VS – Vf
Since V0 = AVi = A (VS – Vf) = AVS - AVf = AVS - AβV0
Then V0(1+Aβ) = AVS
Therefore AVf = A/(1+Aβ)= (RF1+RF2)/RF2 ≈ RF1/RF2
Gain with feedback reduces by a factor of (1+Aβ). Also the output impedance reduces by a factor 1+Aβ while the input
impedance increases by the same factor.
In two stage series amplifier, two feedback resistors RF1 & RF2 are connected as in fig a. The output voltage is
divided across RF2 and RF1 to produce a feedback voltage in series with the signal at the base of Q1.
AVf = A/(1+Aβ)
Procedure:- (Note :- To find, maximum undistorted gain, frequency response, Input & output impedance refer the
procedures given in single stage amplifier.

3. Draw and study the circuit,

4. Place the components on bread board and connect them as per given fig a. Use wires for connection
as required.
5. Check DC conditions for both stages.

Staff :- KRS , 3rd Sem Telecommunication Department, Session :- Aug10-Dec10,

 CYCLE 2 EXPERIMENT ( EXPT 5 TO 8) P A G E | 7 OF 18

6. With feedback resistor RF1 disconnected, Vi from signal generator is fed to first stage with amplitude of
say 20 mV and frequency say 2 KHz. Vo is measured on CRO. Vi is increased till Vo is undistorted. At
this instant Vo and Vi amplitudes are measured. Calculate the open loop gain . Theoretical gain =
Av1*Av2 = (-R3*Zi2/R4) *R7/re ≈ 300 or higher.
7. Wth the feedback circuit, find voltage gain as per step 4. and ensure that it is less than open loop gain
by (1/AB) ≈ 100 to 200
8. Now the frequency is varied in steps from 10 Hz to 1 MHz The output is measured at each step and is
recorded in the tabular column. Plot the graphs of frequency versus Gain in dB.
9. Find the input impedance and output impedance as per given procedure.
10. Compare the closed loop voltage gain, frequency response, input and output impedance with the open
loop values

To find input impedance:

1. Adjust the input sinusoidal peak to peak in such a way that the output sine wave is not clipped.
2. Note down this value of the input Vin. (Let the frequency of the input be around 2kHZ)
3. Note down the peak to peak amplitude of the corresponding output Vo . Let Vo=Va
4. Connect a DRB ( with 0 resistance)in series with the Function generator.
5. Increase the DRB and observe the magnitude of the output Vo simultaneously on the Oscilloscope.
6. When the magnitude of the output Vo is reduced to half of its original value, stop varying the DRB
further and remove the DRB from the circuit. Vo=Va/2
7. Measure the value of the DRB and this measured value will be the input impedance ( Ri) of the
circuit.
8. Repeat this with RF1 disconnected
DRB/POT
Series voltage feedback
RC coupled amplifier Vo
Vin circuit.

Fig b
5. To find output impedance:

Series voltage feedback

RC coupled amplifier DRB Vo
Vin circuit.

Fig c
1. Adjust the input sinusoidal peak to peak in such a way that the output sine wave is not clipped.
2. Note down this value of the input Vin. (Let the frequency of the input be around 2kHZ)
3. Note down the peak to peak amplitude of the corresponding output Vo . Let Vo=Va
4. Connect a DRB ( with max resistance) in parallel with the load as shown in fig c.
5. Decrease the DRB and observe the magnitude of the output Vo simultaneously on the Oscilloscope.
6. When the magnitude of the output Vo is reduced to half of its original value, stop varying the
potentiometer further and remove the DRB from the circuit. Vo=Va/2

Staff :- KRS , 3rd Sem Telecommunication Department, Session :- Aug10-Dec10,

 CYCLE 2 EXPERIMENT ( EXPT 5 TO 8) P A G E | 8 OF 18

7. Measure the value of the DRB and this measured value will be the output impedance ( Ro) of the
circuit.
8. Repeat this with RF1 disconnected.

Result:- The performance of series voltage feedback amplifier is verified. And the readings are listed below

Parameters With out feedback With feedback circuit

Gain

Band width (f2-f1)

Input resistance Zi

Output resistance Zo

Staff :- KRS , 3rd Sem Telecommunication Department, Session :- Aug10-Dec10,

 CYCLE 2 EXPERIMENT ( EXPT 5 TO 8) P A G E | 9 OF 18

Worksheet:-
Circuit diagram:-

Design:-
Bias circuit design: Given: VCC = 10V, VCE = 5V, IC = 2m  = 100 (assumed)
Assume VBE = 0.7V for silicon diodes
VE = 10% of Vcc = 1V
Assume IE ~ IC
RE = VE /IE = 1V/ 2mA = 500Ω (use RF1 = 330Ω, R4= 180 RE8= 470 Ω)
Rc =(Vcc- VCE -VE) / IC=( 10-5-1 ) / 2mA =2 k.(Use 2.2kΩ for Rc1 &Rc2)
V 2 =V B = VE + VBE = 1+0.7 = 1.7V
βR E ≥ 10 R 2
R 2 = (βR E)/10 = 5kΩ (use 4.7 kΩ for R 2 and R6)
V1 = Vcc – V2 = 10-1.7= 8.3V
V1/ V2 = R1 / R2
R1 = (V1/ V2) * R2 = 22.9kΩ (use 22 kΩ R1 and R3)
Cc = 10F, CE = 22F

Designing the feedback circuit:-

Take β as 0.7% =0.007
As per design consideration, RF1 should be high and RF2 should be as low as possible.
β = RF2 / (RF1+RF2)
Take RF2 as 330 Ω and RF1 = (RF2- β RF2)/ β = 46.8K take 47k

Staff :- KRS , 3rd Sem Telecommunication Department, Session :- Aug10-Dec10,

 CYCLE 2 EXPERIMENT ( EXPT 5 TO 8) P A G E | 10 OF 18

Biasing Values :-

For stage1 Biasing values VCE1= VBE1= VRC1= So Ic1 = VRC1 / Rc1 =

For stage2 Biasing values VCE2= VBE2 = VRC2= So Ic2 = VRC2 / Rc2=

Voltage Gain :
Without feed back Vin = Undistorted Max Vout = Avm = Vout/Vin =

With feedback connected Vin = Undistorted Max Vout = Avm = Vout/Vin =

Measurement of Input impedance:-

With out feed back

Vo when resistance of DRB is zero , Va1 = Va1/2 = Resistance of DRB when Vo is equal to Va1/2 =

With feedback

Vo when resistance of DRB is zero , Va2 = Va2/2 = Resistance of DRB when Vo is equal to Va2/2 =

Measurement of output impedance:-

With out feed back

Vo when resistance of DRB is max , Vb1 = Vb1/2 = Resistance of DRB when Vo is equal to Vb1/2 =

With feedback

Vo when resistance of DRB is max , Vb2 = Vb2/2 = Resistance of DRB when Vo is equal to Vb2/2 =

Parameters With out feedback With feedback circuit

Gain

Band width (f2-f1)

Input resistance Zi

Output resistance Zo

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Marks:-

Staff :- KRS , 3rd Sem Telecommunication Department, Session :- Aug10-Dec10,

 CYCLE 2 EXPERIMENT ( EXPT 5 TO 8) P A G E | 11 OF 18

Frequency Response:- Table 1 – Frequency response measurement without feedback

Vin = ------- Volts ( Peak to Peak)

Input freq Vo (p-p) Av=(Vo/Vin Avdb=20log(Av) Input freq Vo (p-p) Av=(Vo/Vin) Avdb=20log(Av)

10 Hz 7 kHz
20 Hz 8 kHz
30Hz 9 kHz
40Hz 10 kHz
60 Hz 20kHz
70Hz 30kHz
80Hz 40kHz
90Hz 50kHz
100 Hz 60kHz
200Hz 70kHz
300Hz 80kHz
400 Hz 90kHz
500Hz 100kHz
600Hz 200kHz
700Hz 300kHz
800Hz 400kHz
900Hz 500kHz
1 kHz 600kHz
2 kHz 700kHz
3 kHz 800kHz
4 kHz 900kHz
5 kHz 1MHz
6 kHz 2MHz

From the graph, f1 = f2 =

Bandwidth (BW) = f2 - f1 = Gain bandwidth(GBW) = Avm * BW =

Staff :- KRS , 3rd Sem Telecommunication Department, Session :- Aug10-Dec10,

 CYCLE 2 EXPERIMENT ( EXPT 5 TO 8) P A G E | 12 OF 18

Table 2 – Frequency response measurement with feedback

Vin = ------- Volts ( Peak to Peak)

Input freq Vo (p-p) Av=(Vo/Vin Avdb=20log(Av) Input freq Vo (p-p) Av=(Vo/Vin) Avdb=20log(Av)

10 Hz 7 kHz
20 Hz 8 kHz
30Hz 9 kHz
40Hz 10 kHz
60 Hz 20kHz
70Hz 30kHz
80Hz 40kHz
90Hz 50kHz
100 Hz 60kHz
200Hz 70kHz
300Hz 80kHz
400 Hz 90kHz
500Hz 100kHz
600Hz 200kHz
700Hz 300kHz
800Hz 400kHz
900Hz 500kHz
1 kHz 600kHz
2 kHz 700kHz
3 kHz 800kHz
4 kHz 900kHz
5 kHz 1MHz
6 kHz 2MHz

From the graph, f1 = f2 =

Bandwidth (BW) = f2 - f1 = Gain bandwidth(GBW) = Avm * BW =

Name & USN of student:-

Staff :- KRS , 3rd Sem Telecommunication Department, Session :- Aug10-Dec10,
Staff sign with date:-

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 CYCLE 2 EXPERIMENT ( EXPT 5 TO 8) P A G E | 13 OF 18

EXPERIMENT 7:- FET CHARACTERISTIC

Aim: To plot the characteristic of FET and to find i)Drain dynamic resistance ii) Mutual conductance
iii)Amplification factor.

Components & Equipments required: Bread Board, FET (1 no- BFW10 /equt), Multimeter, DC Milliammeter
-1no Regulated DC power supply (2no- 0 to 30V dc), Probes, Wires (As required).
Theory: FET, the field Effect transistor is a 3 terminal, voltage controlled device with three terminals drain,
source and gate. The current flows between drain and source and this current is controlled by the voltage
between gate & source. Mainly there are two types of FET , they are i)JFET (Junction Field Effect
Transistor) ii)MOSFET (Metal Oxide Semiconductor Field Effect Transistor)..

The FET has several advantages over conventional Bipolar junction transistor.
1. In a conventional transistor, the operation depends upon the flow of majority and minority carriers.
That is why it is called bipolar transistor. In FET the operation depends upon the flow of majority
carriers only. It is called unipolar device.
2. The input to conventional transistor amplifier involves a forward biased PN junction with its
inherently low dynamic impedance. The input to FET involves a reverse biased PN junction hence
the high input impedance of the order of M-ohm.
3. It is less noisy than a bipolar transistor.
4. It exhibits no offset voltage at zero drain current.
5. It has thermal stability.
6. It is relatively immune to radiation.
The main disadvantage is its relatively small gain bandwidth product in comparison with conventional
transistor.
In FET the current is flowing through either P or N semiconductor and called as N channel or P channel .
JFET. Ohmic contacts are then added on each side of the channel to bring the external connection. Thus if
a voltage is applied across the bar, the current flows through the channel.
The terminal from where the majority carriers (electrons) enter the channel is called source designated by S.
The terminal through which majority carriers leaves the channel is called drain and designated by D. For an
N-channel device, electrons are the majority carriers. Hence the circuit behaves like a dc voltage V DS applied
across a resistance RDS. The resulting current is the drain current ID. If VDS increases, ID increases
proportionally.
Now on both sides of the n-type bar heavily doped regions of p-type impurity have been formed by any
method for creating pn junction. These impurity regions are called gates (gate1 and gate2) as shown in the
fig below.

Staff :- KRS , 3rd Sem Telecommunication Department, Session :- Aug10-Dec10,

 CYCLE 2 EXPERIMENT ( EXPT 5 TO 8) P A G E | 14 OF 18

Both the gates are internally connected and they are grounded yielding zero gate source voltage (VGS =0).
The word gate is used because the potential applied between gate and source controls the channel width
and hence the current.

As with all PN junctions, a depletion region is formed on the two sides of the reverse biased PN junction.
The current carriers have diffused across the junction, leaving only uncovered positive ions on the n side
and negative ions on the p side. The depletion region width increases with the magnitude of reverse bias.
The conductivity of this channel is normally zero because of the unavailability of current carriers.

The potential at any point along the channel depends on the distance of that point from the drain, points
close to the drain are at a higher positive potential, relative to ground, then points close to the source. Both
depletion regions are therefore subject to greater reverse voltage near the drain. Therefore the depletion
region width increases as we move towards drain. The flow of electrons from source to drain is now
restricted to the narrow channel between the no conducting depletion regions. The width of this channel
determines the resistance between drain and source.

Procedure:
1. Study the circuit and expected outputs.
2. Place the components on bread board and connect them as per given test set up. Use wires
for connection as required.
3. Output characteristic: - Set VGS to 0V and vary VDS and measure the corresponding ID . Upto
pinch off voltage Vds in steps of 0.5 and then after in steps of 1V. Repeat this experiment when
Vgs =-2V .
4. Transfer characteristic: - Set VDS to 10V i.e well above the pinch off voltage. And vary the VGS
from 0V till ID becomes 0 in steps of -1V and note down the output current ID . Repeat this
experiment for VDS =20V
5. Plot the graph of
a. VDS Vs ID for various VGS
b. VGS vs Δ ID.

6. From the output characteristic, note down the pinching voltage Vp, max drain current I DSS and
output resistance, rd (Δ VDS / Δ ID ).
7. From the transfer characteristic measure the mutual conductance or transconductance gm
(Δ ID/ Δ VDS) at a given Q point.

Result:-

Staff :- KRS , 3rd Sem Telecommunication Department, Session :- Aug10-Dec10,

 CYCLE 2 EXPERIMENT ( EXPT 5 TO 8) P A G E | 15 OF 18

Worksheet:-
Test Set up:-
Calculations:- From the output characteristic graph, at Q
point ----------

Δ ID = ΔVDS = So rd =

From the transfer characteristic graph, at Q point ----------

Δ ID = ΔVGS = So gm =

Amplification factor Av = gm*rd

Output Characteristic Table Transfer Characteristic Table

VGS =0V VGS = -2V VDS =10V VDS =20V

VDS (V) ID (mA) VDS (V) ID (mA) VGS (V) ID (mA) VGS (V) ID (mA)

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Staff :- KRS , 3rd Sem Telecommunication Department, Session :- Aug10-Dec10,

 CYCLE 2 EXPERIMENT ( EXPT 5 TO 8) P A G E | 16 OF 18

Aim : To design voltage divider biasing circuit of JFET and verify the DC conditions .

Components & Equipments required: Bread board, resistors ( 4nos as per design), FET (3 no- BFW10 or eqt)
, Regulated DC supply ( 0-30V dc ,1no) multimeter (at least 2nos), wires, probes.
Theory: For the field-effect transistor, the relationship between input and output quantities is nonlinear due to the
squared term in Shockley’s equation. Linear relationships result in straight lines when plotted on a graph of one
variable versus the other, while nonlinear functions result in curves as obtained for the transfer characteristics of
a JFET. Due to the nonlinear relationship between ID and VGS dc analysis can be done using c the
mathematical approach or simplified graphical approach which limit solutions to tenths-place accuracy.
Another distinct difference between the analysis of BJT and FET transistors is that the input controlling variable
for a BJT transistor is a current level, while for the FET a voltage is the controlling variable. In both cases,
however, the controlled variable on the output side is a current level that also defines the important voltage levels
of the output circuit. The general relationships that can be applied to the dc analysis of all FET amplifiers
Are IG 0 A and ID = IS Shockley’s equation is applied to relate the input and output quantities:

Three types of FET biasing generally used are :- a) fixed bias, which needs a separate dc source b) Self bias ,
by grounding gate through a resistor c) Voltage divider bias .
When IDQ is given, the corresponding input parameter VGS can be get using transfer characteristic curve or using
the Scholkey ‘s equation . Values IDSS and VP are taken from the data sheet. The graph below explains the dc
load line analysis voltage divider bias circuit for a FET.

Q point equations:-

Q point Equations Load line equations

VDD R2 VG
VG  ID  atVGS  0
R1  R2 ) RS
VGS  VG  I D RS

V VGS  VG atID  0mA

I D  I DSS (1  GS ) 2
VP

VDSQ  VDD  I D ( RD  RS )

Staff :- KRS , 3rd Sem Telecommunication Department, Session :- Aug10-Dec10,

 CYCLE 2 EXPERIMENT ( EXPT 5 TO 8) P A G E | 17 OF 18

Procedure:
1. Study the circuit, Get IDSS & VP (VGS off ) from the data sheet of BFW 10. Design the biasing
resistors.
2. Take 3 FETS and measure the IDSS and VP for the same.
3. Place the components on bread board and connect them as given in circuit diagram. Use the
wires for connection as required.
4. Set VDD to 12V DC. And Measure DC voltage
i) between Drain and Source (VDS) ii) between Gate and Source (VGS) iii) Across the resistor
RD (VRD ) iii) Across the resistor R2 (VG or VR2) iv) Across the resistor RS (VS) v)Across the resistor
R1 (VR1)
5. Calculate the value of ,Is / Id ;
ID= VRD / RD, Is= VS / Rs,
6. Compare the measured ID , IS , VGS and VD S with the design value.
7. Repeat this experiment by changing the FET
8. Draw load line and locate Q point for all FET.

Result: It is observed that for variation of IDSS from ------------ value --------------, variation in VDSQ & IDQ changes from ---
------------ ---- to ------------------------------

Staff :- KRS , 3rd Sem Telecommunication Department, Session :- Aug10-Dec10,

 CYCLE 2 EXPERIMENT ( EXPT 5 TO 8) P A G E | 18 OF 18

Work Sheet:
Circuit Diagram:-

Fig a:- FET Amplifier Fig b: DC analysis circuit

Design:- From the data sheet of BFW 10, VGSoff = 8V So VP = 8V IDSS = 8 to 20mA, We will take IDSS =( 8+20)/2 =
14mA
Given VDD = 12V IDmaxQ = IDSS/4 = 3.5mA VDSmin = 3V Then VGSQ = VP/2 = - 4V
(Note :- If IDQ is other than IDSS/4, find VGSQ using Shockley’s equation or from the transfer characteristic curve )
Take VG=1V Then Vs= VG- (VGS) = 1- (-4V) = 5V Rs = 5V/3.5mA = 1.42k Take Rs =1.5 k
RD = (VDD-VDS-Vs ) / ID = 12 - 3 - 5 / 3.5 mA = 1.14k Take RD = 1.2k

To get VG=1 V use suitable potential divider say R2 =100K and R1 =1.1 M take R1 =1 M
Design fig as per
Parameters FET 1 FET2 FET3 data sheet
IDSS
VP
VG
IDQ
ISQ
VDSQ
VGSQ

Result:
It is observed that for variation of IDSS from ------------ value --------------, variation in VDSQ & IDQ changes from ---------------
---- to ------------------------------
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Marks:-

Staff :- KRS , 3rd Sem Telecommunication Department, Session :- Aug10-Dec10,