8086 : Overview

8086 Pin Description

Pin description – 8086 minimum

_ (34) BHE/S7 : Bus High Enable. Enables the most significant data bus bits
(D 15 -D 8
) during a read or write operation
_ S7 , S6 : 1, 0 for 8086
_ AD15-AD0
Multiplexed address(ALE=1)/data bus(ALE=0). , A19/S6-A16/S3
(multiplexed)
_ IO/M is replaced with M/IO

MINIMUM-MODE AND MAXIMUM-MODE

SYSTEMS

Minimum and Maximum Modes of Operation

Difference : Min and Max mode
MINIMUM MODE INTERFACE SIGNALS

1 Address/data bus
AD0-AD7 (address/data bus pins) –
• these pins output both address and data information and input
data at different times of the bus cycle.
•As address bus; carry address infor to memory / IO port
•As databus , r/w data for memory, i/o data for IO device and
interrupt codes fr interrupt controller
•Usually an external latch stores the address information form
these pins before the pins are switched to carry data.
A8-A15 (address bus pins)
used solely for specifying the address of a memory location or IO
port. (for 8088)
8086 has 16 bit data bus , AD0-AD15

2 Status signals
Status signals: A16 – A19 multiplexed with status signals
S3 – S6 respectively
-A16/S3-A19/S6 (address bus or status pins) - these either carry memory
addressing information or status information.
S6 is always at logic 0.
S5 describes the state of the interrupt flag in the FLAGS register.
S4 and S3 describe the segment register being used to generate the physical
address that was output on the address during the current bus cycle.

SYSTEM CLOCK
Clock (CLK) : input signal which synchronize the
internal and external operations of the
microprocessor.

BUS CYCLE AND TIME STATES

A bus cycle defines the basic operation that a microprocessor performs to

communicate with external devices.
•Examples of bus cycle are memory read, memory write, input/output read and
input/output write.
•A bus cycle corresponds to a sequence of events that starts with an address
being output on the system bus followed by a read or write data transfer.
•During these operations, a series of control signal are also produced by the
MPU to control the direction and timing of the bus.
•Each bus cycle consists of at least four clock periods, T1, T2, T3 and T4.
•These clock period are also called T-state.
• These 4 clock states gives a bus cycle duration of ( 125 ns * 4 ) = 500 ns in a 8-
Mhz 8088
• Idle State: no bus activity ; one clock period
• Wait state : controlled by READY signal ; inserted between T3 and T4 when
READY = 0 . Bus cycle will complete when READY = 1

Timer States

• T1
– Address placed on bus
– ALE active
• T2
– Change direction of Data bus for READ instructions
• T3-4
– Data transfer occurs

Bus Cycle and Time States

T1 - start of bus cycle. Actions include setting control signals to give the
required values for ALE, DTR, IO/M putting a valid address onto the
address bus.
T2 - the RD or WR control signals are issued, DEN is asserted and in the
case of a write, data is put onto the data bus. The DEN turns on the
data bus buffers to connect the CPU to the external data bus. The
READY input to the CPU is sampled at the end of T2 and if READY is
low, a wait state TW (one or more) is inserted before T3 begins.
T3 - this clock period is provided to allow memory to access the data. If
the bus cycle is a read cycle, the data bus is sampled at the end of T3.
T4 - all bus signals are deactivated in preparation for the next
clock cycle. The 8088 also finishes sampling the data (in a read
cycle) in this period. For the write cycle, the trailing edge of the
WR signal transfers data to the memory or I/O, which activates
and write when WR returns to logic 1 level.

System Timing Diagrams

Wait and Idle States

• Idle State
– No bus activity required
– Each is 1 clock period long
– Occurs when instruction queue is full or the MPU does
not need to read/write to memory
• Wait State
– Triggered by events external to MPU
– Buffer full will trigger a wait state
– Triggered by READY pin
– Inserted between T3 and T4