2014 5th International Conference on Computer and Communication Technology
CORDIC based BPSK Modulator
Parichay Kalra andAnand Kukde
Department of ECE
NIT, Trichy, India
parichaykalra@yahoo.com,anand.kukde@gmail.com
Abstract—This paper presents a novel approach for
implementing Binary Phase Shift keying (BPSK) modulator and
demodulator using Coordinate Rotation Digital Computer
(CORDIC). The CORDIC is used in rotation mode for modulator
and in vector mode for the demodulator. For the sake of
comparison, the modulator and demodulator have been
implemented using three different architectures. From the
results, it is inferred that, pipelined multiplexer based CORDIC
modulator-demodulator is more speed efficient and unpipelined
multiplexer based CORDIC modulator-demodulator is more
hardware efficient.
Keywords—Universal Modulator, CORDIC, FPGA, BPSK,
QPSK
I. INTRODUCTION
Digital modulation schemes are preferred over analog
modulation schemes due to advantages such as reliability,
robustness, cost, flexibility and development of advanced
signal processing algorithms. The Binary phase Shift keying
(BPSK) and Quaternary Phase Shift keying (QPSK)
modulation techniques are more robust in terms of better
security and channel utilization than amplitude modulation
and frequency modulation. The BPSK is applicable in low
cost passive transmitters and used in RFID standards such as
ISO/IEC 14443 adopted in biometric applications. On the
other hand, QPSK has been widely applicable in wireless
techniques such as LTE & LTE ADVANCE, IEEE 802.11b-
1999, IEEE 802.11g-2003, IEEE 802.15.4 standards.
Coordinate Rotation Digital Computer (CORDIC) is one of
the algorithms used for the implementation of both analog and
digital modulators and demodulators. CORDIC algorithm
uses add-shift operations for evaluation of trigonometrical
functions and is proposed by Jack E. Volder [1] and further
improved by Walter [2]. The FPGA implementation of
systems is advantageous due to the flexibility, modularity,
scalability, performance, relative cost and computational
capability and re-programmability of the design. Field
Programmable Gate Array (FPGA) implementation of
CORDIC is reported in a number of works in the literature. In
[3], the universal modulator based on CORDIC is used to
implement BPSK using Xilinx Virtex 5 (FPGA) board.
In [4], multiplexer is proposed in the first three stages of
iteration of CORDIC algorithm implementated on ASIC. It is
978-1-4799-6758-2/14/$31.00 ©2014 IEEE
B Venkataramani
Department of ECE
NIT, Trichy, India
bvenki@nitt.edu
more hardware efficient and has practically same delay. In [5],
this architecture is used for the FPGA implementation of
frequency modulator.
The BPSK modulated wave obtained in [6] proposes a BPSK
modulator based Direct Digital Frequency Synthesis simulated
in MATLAB/Simulink. A BPSK demodulator is also proposed
in [7] which employs multiplier, accumulator and decision
making device. A CORDIC demodulator approach has been
proposed in [8] for FSK modulator which employs phase
adjustment algorithm before the CORDIC module.
In this paper, a novel approach is proposed for implementing
BPSK modulator and demodulator based on CORDIC and
compare their performance with those reported in the
literature.
This paper is organized as follows: Section II and section III
give an overview of BPSK and CORDIC algorithm. Section
IV and V elucidate the details of the CORDIC as modulator
and demodulator. Section VI gives the details on different
types of CORDIC architecture followed by results in Section
VII. Section VIII presents the conclusion.
II. BINARY PHASE SHIFT KEYING
Binary Phase Shift Keying (BPSK) involves two phases or
phase reversal. The BPSK is most robust among all Phase
Shift Keying (PSK) schemes as it is capable of tolerating
maximum noise and distortion. The BPSK modulates 1 bit/
symbol. The general form of BPSK is given as:
cos 2 1 , 0,1 (1)
cos 2 0 (2)
cos 2 , 1 (3)
The block diagrams of BPSK modulator and demodulator
are shown in Fig. 12 and Fig. 2 respectively. The BPSK
demodulator comprises of multiplier, integrator and a decision
making device. The BPSK signal is multiplied by carrier
signal from different periods. The multiplied output is then fed
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into a decision making device which results in negative or
positive output depending on the input signal. Mi + 1 = Mi cos φ − Ni sin φ (10)

Ni + 1 = Ni cos φ + Mi sin φ (11)

Mi + 1
= Mi − Ni tan φ (12)
cos φ

Ni + 1
= Ni + Mi tan φ (13)
cos φ

The above equations are simplified and rewritten as:

Fig. 1: BPSK Modulator Mi + 1 = Mi − Ni tan φ (14)

Ni + 1 = Ni + Mi tan φ (15)

M N
(M , N ) = (
N N
, ) (16)
∏ ∏ cos φ
fn fn
cos φ

The division by cosφ for all the N iterations is evaluated by

i

dividing the value of (MN,NN) by ∏ cos φ i . The value of φ i

for i =1, 2,..where N is chosen such that tan φi is 2 This -i.

results in reducing multiplication operation by tan φ i to a shift

Fig. 2: BPSK Demodulator
III. CORDIC ALGORITHM
A. Introduction
The CORDIC algorithm provides an iterative method
of performing vector rotations by arbitrary angles using shifts
and adds [1]. In the rotation mode, CORDIC is used for
converting one vector in rectangular form to another vector in
rectangular form. In the vector mode, it converts a vector in
operation. With increase in iteration count φi reduces to
smaller values. The iteration is terminated difference when
-1 -i
between tan (2 ) become very small. The angle by which the
vector needs to be rotated after the completion of ith iteration
is indicated by the parameter zi + 1 defined by equation
zi + 1 = zi − φ i (17)
φ is taken as positive when the rotation is anticlockwise
i

rectangular form to polar form. and negative otherwise. A sign (sgn) of zi indicates whether in
The CORDIC algorithm is a versatile iterative algorithm the next iteration, the rotation has to be anticlockwise or
using shifters and adders instead of multipliers, dividers. The −i
clockwise. Since, tan φ is (+2 ) when θI is positive and
CORDIC algorithm has been used in evaluation of
−i
trigonometrical values, square roots, logarithms etc. [3] (−2 ) otherwise, the iterative equations may be rewitten as
B. Rotation Mode of CORDIC
The CORDIC algorithm in rotation mode is derived ∂i = sgn( zi ) (18)
−i
from the following equations: Mi + 1 = Mi − ∂i 2 Ni (19)
−i
Mfn = Min cos φ − Nin sin φ (8) Ni + 1 = Ni + ∂i 2 Mi (20)
−1 −i
zi + 1 = zi − ∂i tan 2 (21)
Nfn = Nin cos φ + Min sin φ (9)

The vector M and N is rotated in Cartesian Plane by an angle
φ . The rotation is achieved by undertaking smaller successive
pseudo rotations φ 1, φ 2.........φ n such that φ = ∑φ i
Rotation of the vector by an angle φ can be rewritten as
i
C. Vector Mode of CORDIC
In this mode of operation, the input vector is (X,Y) is rotated
using the CORDIC algorithm until the y component becomes
zero. The three outputs obtained from the CORDIC algorithm

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 y with the carrier signal of same frequency with the 90
are x 2 + y 2 , 0 and tan −1 ( ) . This mode coverts the degrees phase offset.
x
Cartesian coordinates into polar coordinates i.e. is (X,Y) is CORDIC module: The in-phase and quadrature signals are
y given to x and y inputs of the CORDIC which is operated
converted to ( x 2 + y 2 , tan −1 ( ) ).
x
in the vector mode which yields x 2 + y 2 and
IV. CORDIC AS UNIVERSAL MODULATOR y
tan −1 ( ) i.e. magnitude and phase of the input.
The block diagram of the universal modulator is shown in x
Fig. 3. The Modulating signal for frequency modulation is fed Accumulator and Threshold Device: The phase output of
to ∆r as the input of the phase accumulator. The phase the CORDIC module is accumulated and summed together
accumulator is followed by an adder. The amplitude to get the output.
modulation signal is fed as one of the inputs to this adder. This
adder is succeeded by CORDIC whose inputs M, N and θ Threshold device: The threshold device is the decision
form the other set of inputs to the design. These design inputs making device which works depending on the input given.
are used to control various characteristics of the wave which This device gives ‘1’ as the output if the input as positive
and ‘-1’ as the output when input is negative.
are described below:
Counter: The counter module is used to provide the
Min, Nin : Amplitude Modulation necessary synchronization for accumulator to obtain the
∆r : Frequency Modulation correct modulating signal as the output.
φ(t): Phase Modulation
∆r, φ(t) are variable and Min, Nin is constant: BPSK
∆r, φ(t) are constant and Min, Nin is variable: QPSK

Fig.3: Universal Demodulator

Fig.3: Universal Modulator

Fig.4: CORDICDemodulator

V. CORDIC AS DEMODULATOR
If the carrier frequency, amplitude and phase of the received
The block diagram for CORDIC based demodulator is signal are fi , 2b(t) and θ(t) respectively, then received signal
shown in Fig.3. The CORDIC based demodulator consists of r(t), is given by
following blocks: 2 sin 2 t+ θ (t))
• In phase generation One of the approaches for demodulating the above signal is
the generation of the in phase signal I(t) and quadrature signal
• Quadrature generation Q(t) given by
• CORDIC module in vector mode
sin 2 0
• Accumulator and Threshold device
In-phase Generation: The in-phase or I phase is generated cos 2 0
by multiplying the BPSK modulated signal with the carrier
signal of same frequency.
VI. CORDIC ARCHITECTURES
Quadrature Generation: The quadrature phase or Q phase
is generated by multiplying the BPSK modulated signal The architectures used in the implementation of the
universal modulator for obtaining BPSK signal are as follows:

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 • Unrolled CORDIC • ∂1 is +ve and ∂2 is -ve
• Multiplexer Based unpipelined CORDIC q2 p 3 p 7 p
p3 = p2 + = + = (28)
• Multiplexer based pipelined CORDIC 4 2 8 8

Unrolled CORDIC: This type of architecture uses simple p 2 3 p p 11 p

q3 = q2 − = − =
shifter and adder/ subtractor for the each iteration. The 4 2 8 8
uppermost adder/ subtractor is used for evaluation of angle for
the next iteration. The output of these adder/ subtractor also
determines the direction of rotation of the vector whether it • ∂1 is -ve and ∂2 is -ve
should be clockwise or anticlockwise. The lowermost and the q 2 3 p p 13 p
middle adder/ subtractor is used for evaluation Min and Nin. p3 = p 2 + = + = (29)
This type of architecture is hardware extensive architecture 4 2 8 8
which is costly in terms of hardware as well as delay [3]. p2 p 3 p p
q3 = q2 − = − =
Multiplexer based unpipelined CORDIC: This architecture 4 2 8 8
involves replacement of initial three stages of shifter and
adder/ subtractor with the multiplexer. This is done taking
into consideration the following calculations: VII. RESULTS
CORDIC based modulator and demodulator have been
p1 = p = (1/R)(22)
implemented in Xilinx Virtex 5 to obtain the details no. of
q 1 = p (23) slices, LUTs, delay. These results have been taken from design
summary window in Xilinx ISE 14.1. The implementation
The output of second stage can be given as: results of modulation techniques on Xilinx Virtex 5
• ∂1is positive (XC5V1X110T-1FF1136) are given in tables I, II.

p1 p
p 2 = p1 − = (24)
2 2 TABLE I: Implementation Results for Binary Phase Shift Keying Modulator
p1 3 p
q2 = p1 + = Binary Phase Shift Keying - Modulator
2 2 Parameter [6] Multiplexer based Multiplexer based
Unpipelined CORDIC Pipelined CORDIC
111 1349 1879
• ∂1is negative Slice/LUTs
Critical Path 107 3.376 3.075
p1 3 p Delay (ns)
p 2 = p1 + = (25)
2 2
TABLE II: Implementation Results for Binary Phase Shift Keying
p1 p Demodulator
q 2 = p1 − =
2 2
Therefore, stage 2 can be replaced with the two multiplexers Binary Phase Shift Keying - Demodulator
with the crosswise interchanged values. The output of stage 3 Parameter Unrolled Multiplexer based Multiplexer based
can be gives as: CORDIC Unpipelined CORDIC Pipelined
CORDIC
Slice/LUTs 2654 1860 2708
Critical Path 101.247 5.375 4.714
• ∂1 is +ve and ∂2 is +ve Delay (ns)
p2 p 3 p p
p3 = p2 − = − = (26)
4 2 8 8 The BPSK waveform obtained from the universal
p 2 3 p p 13 p modulator is shown in fig 5:
q3 = q2 + = + =
4 2 8 8

• ∂1 is -ve and ∂2 is +ve

q 2 3 p p 11 p
p3 = p2 − = − = (27)
4 2 8 8
p2 p 3 p 7 p
q3 = q 2 + = + =
4 2 8 8
Fig.5: BPSK Waveform

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 The output of the demodulator along with the modulating
signal is shown below in fig.6 and fig. 7
From the implementation results, it is inferred that the
multiplexer based unpipelined CORDIC modulator-
demodulator is more hardware efficient and multiplexer based
pipelined CORDIC modulator-demodulator is more speed
efficient

Fig.6: Modulating Signal

REFERENCES
[1] J.E. Volder, “The CORDIC Trigonometric Computing Technique”,IRE
Transactions on Electronic computer, vol. EC-8, pp. 330-334,1959.
[2] J. Walther, “a unified algorithm for elementary functions,” proc.
Spring joint comp. con & vol.38, pp.379-385, 1971.
Fig.7: Demodulated Output
[3] Meher, P.K.; Valls, J.; Tso-Bing Juang; Sridharan, K.; Maharatna, K.,
"50 Years of CORDIC: Algorithms, Architectures, and Applications,"
IEEE Transactions on Circuits and Systems I: Regular Papers,, vol.56,
The hardware setup is also shown below in Fig. 8 where it
no.9, pp.1893,1907, Sept. 2009
co-simulation has been done.
[4] Peter Nilsson, “Complexity reduction in unrolled CORDIC architectures
“ Electronics, circuits, and systems,2009.ICECS 2009, pp.868-871.
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Jan. 2013
[6] Popescu, S. O.; Gontean, A.-S.; Budura, G., "Simulation and
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Informatics (SACI) 2011, vol., no., pp.459,463, 19-21 May 2011
[7] Popescu, S. O.; Gontean, A.-S.; Budura, G., "BPSK system on Spartan
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[8] Xiaoxin Cui; Dunshan Yu; Xing Zhang, "A 2-Level FSK Demodulator
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VIII. CONCLUSION Dec. 2007

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