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MICROPROCESSOR
REFERENCE
MANUAL
~(JTOMATIC ELECTRONIC SYSTEMS INC., 5455 PARE sr, MONTREAL 309 CANADA, TEL. (514) 735- 6581
~ES DATA INC., P.O. BOX 143 ST ALBANS, VERMONT 05478, TEL. (802) 524-3660
: I : :
MICROPROCESSOR
REFERENCE MANUAL
TEL. : ( 514 ) 7 3 5 - 6 5 8 1
AES MICROPROCESSOR
TABLE OF CONTENTS
Page
I . System Design Features 1
3 .~ serial I/O 23
3.~.1 I/O Bus Structure 23
3.~.2 Modular System Unit Bus Interface 24
3.~.3 Typical I/O Board 24
3.~.4 Serial I/O Interrupt 25
3.1 Interrupt Structure 26
3.2 Parallel I/O 26
3.3 Multiprocessor Configuration 27
3.4 I/O Instructions 27
3~4.l U-Register Instructions 28
3.4.2 I/O Register Select Instructions 28
3.4.3 I/O Channel Select Instruction 28
3.4.4 Serial I/O Clock, Load and R/W 29
Instructions
3.4.5 Relinquish Bus Control Instructions 29
3.4.6 Serial I/O Timing Instructions 29
3.4 . 7 Interrupt Instructions 3~
3.4.8 Other I/O Instructions 31
IV. Timing 35
4. JJ Function and Literal Timing 35
4.1 Branch Instruction Timing 35
4.2 Subroutine Timing 35
4.3 I/O Timing 35
V. Program Development and Control Console 41
VI. Software Development 45
VII. Appendices
A.I Table of Binary to Octal to ASCII Conversion A.l
A.2 Operation Code List B.l
Illustrations
·1.1 Microprocessor Block Diagram 8
1.2 Master Clock Timing 9
2.1 Functional Programming Block Diagram 22
3.1 Typical I/O System Configuration 32
3.2 MSU Bus Interface 33
3.3 Typical I/O Interface Card 34
4.1 Function Timing Diagram 36
4.2 Branch Instruction Timing Diagram 37
4.3 Subroutine Timing Diagram 38
4.4 Reading a Character 39
4.5 writing a Character 4~
5.1 Program Development and Control Console Panel 44
1. SYSTEM DESIGN FEATURES
1) Timing Generator
2) Control Logic A
3) Control Logic B
4) 1.'J24 x 8 Data Memory (RAM)
5) 2~48 x12 Instruction Memory (ROM)
1.
Most configurations leave a slot reserved for a maintenance
and control interface card that interfaces the microprocessor to a
program development and control console, thus enabling the operator to
monitor and/or c6ntrol the microprocessor during maintenance, test
or programming.
2.
* National Semiconductor Corp. TM.
upon the particular instruction decoded, literal data can be out-
putted directly from RO.r.1.
3.
1.5. Arithmetic Logic Unit (ALU)
1.6. Registers
4.
1.6.3. L.A.-Register: The 8-bi t LA (ALU Conunand) register is
similar to the L-register in that an 8 bit literal from ROM is
loaded into it during an ALU literal instruction. The output of
the LA-register selects the operating mode of the ALU.
e) cleared.
5.
1.8. Push Down Stack
struction or data memory has an access time longer than 16~ n sec,
a memory ready flag from the memory device being accessed maybe
used to lengthen or delay the master clock in increments of 8~ nano-
sec. This feature of having a variable cycle time is normally not
used. It does, however, provide the flexibility of intermixing
both slow and fast memory types within the same microprocessor with-
out completely slowing down the master clock to accommodate the
slowest memory module. It should be noted that only the leading
and trailing edges of the master clock pulse are used for strobing
or setting the various logic functions throughout the control ,logic
of the microprocessor. No other sub-clocks delay lines or one-shots
are used for timing purposes. When the P register is incremented
or loaded, the new instruction address is available. After the
memory access time has been reached, data is available for instruction
decoding. Both the leading and trailing edges of the next clock
pulse are used for executing the instruction just read. The detailed
timing diagrams for the various instructions are provided in section
IV.
6.
line. This I/O bus is used to transfer 8 bit serial characters
into or out of the microprocessor at rates up to one character every
9 .12 micro-seconds.
7.
DECISION a
INTERRUPT FLAGS
J ( CONTROL
FUNCTIONS
LOAD
LITERAL
INSTRUCTION DECODER
a
CONTROL
LA-
ROM
REGISTER
ENABLE LOAD NCREMENT-..
INST RU CT I ON
D=B FLAG CARRY
OUT
FLAG
R/W OUTPUT LITERAL LOAD RET.
ADDRESS
- .. MEMORY
AD JUMP-..
8 BIT ADDRESS '-----r---P"""""USH DOWN
RAM
A- STACK OVER
DATA FLOW FLAG
REGISTER
MEMORY
F PUSH
PLUS
PUSH UP-.w DOWN
- - - SHIFT 2 LOAD
R/W-... STACK ADDRESS
1~ 1
FIG. I- I SERIAL
MICRO PROCESSOR ~
U
(!)
<I:
o UJ
<I:-J
I-
(')Ol-~IJJ
<I:
11 f
a: I- ~c:t>(!)
......... I-oe
ENABLE
OUTPUT
CLEAR
U
SHIFT
CLOCK 10 TIMING
a (!)
-I
.
<I:
l-
-I
La..
IJJ CD 0 IJJ ......... <I: Q. (I)
0::: c:t ~ -J - 0 kI
o:::Cc:t-J
QUJL&..
ENABLE ~ Sg:
CONT RO L La.. kI
In
BLOCK DIAGRAM z
- - I-
Z
Z
LLI
LLI
(I)
a:: 0:::
z :5
I-e:)
zI- ~~~r-
(.) ~ kI
c:t
l-
C
Q
e
'--~
I-
°11-
c:t 0
.........
" v
/ _LL: _<t a.. kI
(I)
a:
0 9 ......... (I)
PARALLEL CLOCKS
I/O BUS " SERIAL
v
I/O BUS
/
8
12,5 MHZ CLOCK OSC.
ROM ADDRESS IN
~-
MASTER CLOCK I J
I I i I I I I I I I I I I I I I I I , I I ,
2.~.~. Function
11 l~ 9 8765432 1 ~
2.~.1. Decision
11 l~ 9 8765432 1
10.
When bits 8-11 of the micro-instruction are ~, the first
seven bits form a selection address to interrogate one of 27
possible decision flags. If the flag is equal to the value of bit
7, the next micro-instruction will be treated as a branch address.
11 l~ 9 876 5 4 321
LITERAL
I ,
11 10 9 8 7 6 5 4 3 2 1 fI
11.
2.~.5. ALU Literal
~ ~ 1 1 ALU COMMAND
11 If1 9 8 7 6 5 4 3 2 1 ~
12.
For example:
The modified ASCII representation of the following function
.[~,~,~, 1 1 ~ ~ Y1 ~ 1 1 1
11 1 fa' 9 8 7 6 5 4 3 2 1 fa'
is FG.
# Logical OR operation.
13.
2.3. Load Literal Buffer Instruction
14.
Logic Instructi~.
Mnemonic
- -
ASCII Description
Arithmetic Instructions
15.
Mnemonic ASCII Description
Mnemonic ASCII
F=D#B+D LM
F=D#B'+D LN
F=D#B+D+l L- F=D#B'+D+l L.
F=D.B+D LH F=D.B'+D LD
F=D.B+D+l L( F=D.B'+D+l L$
F=D.B-l LK F=D.B'-l LG
F=D#B+D.B' LE F=D#B'+D.B LJ
F=D#B+D.B'+l L% F=D#B'+D.B+l L*
16.
2.5. Load Accumulator Instructions
Bits 8, 9, 1,
8 least significant bits of the
A-register. and
11 of the A-register are left un-
changed.
17.
~, 1, 2 & 3 of the data bus
. respectively.
JIS,DB~ JIC,DB~ BH @H
JIS,DBI JIC,DBI BI @I
JIS,DB2 JIC,DB2 BJ @J Jump if bit n of the
JIS,DB3 JIC,DB3 BK @K data bus is set/clear
JIS,DB4 JIC,DB4 BL @L where n = .~ to 7
JIS,DBS JIC,DBS BM @M
JIS,DB6 JIC,DB6 BN @N
JIS,DB7 JIC,DB7 BO @O
18.
Mnemonic Mnemonic ASCII ASCII Description
for for
Comprement comprement
e) The CLK, LD, R/W and RBC functions are all cleared.
These functions will be explained in the section on
Input/Output.
21.
SERIAL 1/0 8US PARALL EL lI0 8 US
/~ ________________________________________________________ ~A~ _________________________________________________________, /~----------------------~A~----------------------~,
~l;Q
ENABLE FLAG INT INT ACK
~~ ~
-~
~~~ ~~~~~ ~ ~ ){){ A I? Il){"
, I 2 3 4 5 6 7 v V ,
.,. SELECT
& 1
~ '"
3/
(CHL=XX
(-Ci.-K~
( CLK=' )
I
LA IN ENABLEH F=X ) ( PG = I ROM
INSTRUCTION ( PG =0 )
LA- REG I STE R EIN }-t DECODER 8 8/ 2"-2 7
~
P LS.
~ ~ ~---~ 11---1
to
~~
II 2; - 22 27
DECISION a INSTRUCTION
( L=XXX
I
LIN
.
It' INTERRUPT CONTROL ENABLE
/V;
~
3 FL AG
7J B
8 elN M S3 S2 SI S"
jJ
D
D:B
~
REGISTER
LOUT
}
4-BIT UP DOUT
DOUT
1 __ _
DIN
16-WORD PUSH
8-BIT ALU
I/O
READY
I/O
CLOCK
PT t:'
CARRY OUT
~
DOWN COUNTER
DOWN UP
W :
ADD DOWN STACK
R/W
'\ 8 A =Aft )
1/0 B = BR R ) (
EBR
~ J \..
~
J
£
SIO )
I. (-6
>----+.--t---+---V-:6---o-, .L.
8' ,( M=O
... ,. ) ( AL=O)
~----~
~--_--I----
8
CLOCK UOUT
----
... SER. IN
SER.OUT D=U 0= B )
U=U#D
SET U- REGISTER
ENABLE ( D=M
( U=0 CLEAR UIN
,..
A t '" ,. ~ ~
0 8,.. BIT
.. ..
-.I.R - --.S.IA.LE ~ROCES S0 BUS
"\
~
~
~~~~~~~~ ~~~?
FIG. 2.1 FUNCTIONAL PROGRAMMING BL 0 C K DIAGRAM FO R MICROPROCESSOR
22
III. Input/Output
23 .
Type 1: For simple systems (maximum of 2 I/O channels,
proximity of less than 5 ft.), all unidirectional bus lines use
standard TTL gates as both drivers and receivers and bi-directional
lines use TRI-state'* TTL logic gates as drivers and standard TTL
gates as receivers. For this system configuration no serial Input/
Output control card is necessary.
24.
2) outputting drives (sinks) to 8 external points
The output lines are also isolated from the logic and
are protected against electrical transients. An important feature
for the outputs is the capability of providing either a source
of power for the 8 external points or of sinking current from
these same 8 sources. This source/sink capability is an option
on the card.
25.
3.1 Interrupt Structure
26.
It may be seen in Fig. 2.2, there are 3 control and 2
flag lines on the parallel I/O bus that are not used for accessing
data memory. These are:
e) RBC: This line does not go onto the I/O bus, but
rather, is used to disable the microprocessor from
both the serial and parallel I/O busses.
27.
3.4.1 U-Resister Instructions
CHL=~ G@ CHL=l6 GP
CHL=l GA CHL-17 GQ
CHL=2 GB CHL=18 GR
CHL=3 GC CHL=19 GS
CHL=4 GO CHL=2~ GT
CHL=5 GE CHL=21 GU
CHL=6 GF CHL=22 GV
CHL=7 GG CHL=23 GW
CHL=8 GH CHL=24 GX
CHL=9 GI CHL=25 GY
CHL-l~ GJ CHL=26 G?
CHL=l1 GK CHL=27 G[
CHL=12 GL CHL=28 G\
CHL=13 GM CHL=29 GJ
CHL-14 GN CHL=3~ G1'
CHL=15 GO CHL=31 G~
28.
3.4.4 Serial I/O CLOCK, LOAD and R/W Instructions
29.
Mnemonic ASCII Description
JIS,IOR BB Jump if the I/O ready flag is
JIC,IOR @B set/clear. This flag is nor-
mally high. As soon as the
SIO instruction is executed,
the lOR flag goes low and
remains there until the transfer
of data is completed.
JIS,PFL
JIC,PFL
BT
@T } Jump if parallel I/O status
flag is set/clear.
JIS,ALM
JIC,ALM
BA
@A } Jump if external alarm is set/
clear. This alarm flag decision
line is not part of the serial
or I/O bus but is reserved for
I/O independent purposes such
as operator interrupts or
console alarms.
31.
lNTERRUPT
FLAG
U - REGaSTER CLOCK RETURN
12-81T
ADDRESS
PARALLEL I/O I' ,r ,r I
U"~E6ISTER CLOCK OUT
t/O CLOCK
INTERRUPT ACt<
..
MICRO PROCESSOR ~/O l.OAO
I/O R/W - -
DATA
FLAG POWER RESET
HARDWIRE
~rpULSE
MULTIPLY
DIVI DE ~,......---,,-...
uv ",., r, ,,,
OPTION
,r, r, r, tV n \J ,., r'r
-
I 1
~
" \7 ~
"#]
BUS INT. "# 1 r--
~
BUS INT. #2 r--
I---
BUS INT. ~
A_ A"\
"~
~
_L~ CRT ~,,",",,
C R i DISPLAY ~
~ ~
I NTE R
FACE ---
:::::===========~
~_-----------------~
___
IN
t) A LINE ~
t)
LI N E
Q ~ ~ ~ -i! t:i1!/f
DIFFERENTIAL DIFFERENTIAL 01 F F EREN-
TIAL
~~
CL POP R/W LD IAK
DIFFERENTIAL
"
01 F F
LI N E
~LINE
DIFF
LINE
DRIVER REC
LINE RX LINE RX LI N E RX LINE RX REC DR DR
, I 2 3 4 5 6 7 ~
I
~-+------~--~---+--------+---~--~----~====~--=+=====F=9~+=~~----~~~~~F~
LI N E
DR
.4~
, " " ~, ~", " " " "" """.""''1'" ~"~,, "
TTL TTL
TTL BUFFERS TTL BUFFERS
BUFFERS BUFFERS
2 fIl I 2 3 4 5 .6 7 , I 2 3 4 5 6 7 rJ I ~ 3
" I
NON LINEAR LI NEAR LINE A R LI NEAR I/O CL POP R/W LD IAK DATA INT FLAG
REGISTER SELECT REGIST E R CHANNEL GROUP SELECTED
SELECT SELECT SELECT
FILTER
!
~LTER"
: ,
!
~,
+
ISOLATOR 'ISOL~TOR I
I
I
~.
SIGNAL ~jNAL
CONDITIONI NG IC 0 N 0 il T ION I NG
I
I
L _______ ,
LOAD INPUT
RG SEL
CHl SEL SER~AL INPUT
GR SEL I/O 8 BIT
CLOCK
CLOCK SHIFT REG
RESET ----all NT ERFAC E
LAST BiT
SERIAL DATA------ LOG Ie RESET
RI W LOAD OUTPUT
LOAD
8 BIT
OUTPUT BUFFER
FIG. 3-3 r -. -,
~ ••
S~ 57 34
IV. Timing
The AES microprocessor operates on a basic 24~ nano-
second machine cycle. That is, a full execution cycle (read in-
struction from memory and execute instruction) is performed in
each 24~ n. second time interval (except in some special cases in
which the period is extended: these cases were discussed in section
1.9). The timing diagrams presented in the following sections each
correspond to a small program listed at the bottom of the diagram.
35.
MASTERCLO(K
I
----,J
X2 X3 X4 X X6 X7
I
P - REGtSTER (ADDRESS) ~~¢~X I 5
I
I
I
MASTER
CLOCK I I
n n n n n n n n
P I
REGISTER
ROM
DATA
D=B
FLAG
T¢ 24¢ 48rp 72¢ 96¢ 12</J¢ 144¢ 168¢
....
NANOSE.CONDES FROM T()
PROGRAM
~\\\\\~ previously deFlne.d ADDRESS INSTRUCTION
¢ r:D·B
I D= B
2 JMP
ADD~E.SS 1(1
...
"3
..
I~ JlC) D:B
ADDRESS ¢
"
12 J15) D=B
13 ADDRESS ¢
., ...
#
,
.
37
MASTER CLOCK
P. REGIS TE'R
X
1
fJ X X ff/J
X II
X 2<)
X 21 X 12
X 13
X 2 X 3
~
ROM AOD.~
DATA
STACK
ADDRESS
¢ X X 2 X X ¢
12 X 2
P. REGISTER
I NeREM£:;
MODE
i
P. REGISTER: STAC\<.
i ROM DATA OUTPUT DATA OUTPUT ROM DATA OUTPUT
PARALLEL INp'
1
I I I I I I I I I I I
T¢ 240 48¢ 72¢ 960 120¢ 144¢ 168¢ 192¢ 21G¢ 24¢.,0'
-~.~ NANOSECONDS FROM T~ PROGRAM
ADDRESS INSTRUCTION
¢ JSR
PREVIOUSLY DEFINED I ADD. 10
2 JMP
3
I
ADD. (/)
10 JSR
II ADD. 2(j
12 RET
13 t
NOP
FIG. 4.3 SUBROUTINE TfMING DIAGRAM
2¢ RET
NOP
21
MASTER CLOCK
P=REGISTER
(ADDRESS)
ROM DATA ~~~3€~~3<m~~~- - - - -- -- ---- -- -- -- - - -
(INSTRUCTION)
CHANNEL No ~~r---------------------------------C-H~-W~Nl~L---~~---.---------------------------------------------
REGISTER No
START I/O
(S10 STROBE)
I/O READY FLAG
JOR
I/O DATA BIT' O~S8)
rio CLOCK
(OUTPUT)
I/O CLOCK
(U-REG ISlER)
DATA ON D BUS u
lrj 2 4 6 8 I~ 12 14 IG 18 2~ 22 24 2(, 28 3¢ 32 34 36 36 40 42 q4
.----..
eyc LES FROM T¢
PROGRAM
~= PREVIOUSLY DEFINED ADDRESS INTRUCTION
¢ R/W :: R
I C HL =6
2 RG = 3
3 SIO
4 J Ie, 10 R
5 ADDRESS 4
6 D=U
FIG. 4 - 4 READING A CHARACTER
,
MASTER CLOCK
! .
UU~~UU~IUUUU nL
P REGISTER ~ ¢ X I X 2 X 3 X 4 xr+r5~M'M"T1"'_rT'rTTT'T,'T'TT~TT'T'IOOn'TI~'"T'T"I~"TT"T~~H~.,..,..,...~
+--: -4-"'X 5 X <; X 7 X='iJJI
ROM DATA ~R/W"WX CHH, XR~ =3 X SIO XJlc'1l1l1llll1l1l1l1ll1l 111111 II 111111111 :4 XJIC,IORXADi>V 4 XRtW=R XLD:' Xw= 11
41.
functions:
RELINQUISH BUS CONTROL, INTERRUPT ACKNOWLEDGE,
START I/O and MASTER INTERRUPT ENABLE
and decision and interrupt flags:
I/O Ready, I/O Data, D=B, ALU Carry Output, ALU
Carry Input, Relinquish Bus Flag, Serial Interrupt,
Serial Status Flag, Parallel Interrupt, Parallel
Status Flag, Master Interrupt, Power Fail, Real
Time Clock, I/O Clock, U-register Clock, I/O Load,
I/O R/W, and Alarm and Push Down Stack Flag.
42.
13. DISPLAY MEMORY Switch. This switch causes the ROM
data octal numbers on the PDCC to display the contents
of the location specified by the P-register. The P-
register is automatically incremented after operation
of the Display Memory Switch.
43.
~--T----------------------------------------------------------------------------------------------------r----I
: I ! : AES - 80
AUTOMATIC ELECTRONIC SYSTEMS INC
o
DATA DISPLAY SWITCH REGISTER ROM ADDRESS
I-
Z
en LIJ ----j ,---4IIt• .'-_., (---', .- - -" ,. _., ,- - -.
!
..!
enQ. I,
I I • .... / , j
L&Jo II ,'" " ,I ___ .. II I
• - -,
__ -' I "
I , , - _....
I
~--+---+---+----+---+----+----+----I
II: ,.' I I I • • I I I 1
'- - -' - _.' '- - .'
Q.. I I , , • I ~_ _ _~
7 6 543 2 , ~
,_ - - I , ____I :
I
, I
SUB - ROUTIN E : OFF I ON LOCK
LEVEL !
,
,.. -,
I
... ..-,-., ,
I ' ,
I••••1 I
2 3 C
LIST LOAD D U B I/O L LA RAM L 1 i
I
LOAD DISP LOAD STEP RU N HALT 'RESET ALM ILAMP
PROG PROG BUS REG REG SEL REG REG IDATAI-------+-----+----+-------t E MEM MEM ADD TESTTEST
A
5 6 7 R
44
VI. Software Development
- paper tape,
- punched card,
- magnetic tape, or
- disc.
45.
3) Self-assembler to be used in the AES BJJ Program
Development and Control Console with an external
memory of 4k X16.
1. Symbolic Addressing:
Examples:
For ROM addresses •.....•••••••••.•• JMP Label
For RAM addresses ••••••.•.••••••.•• A = Label
For I/O Channels ••.•••••••••••••••• CHL = Label
For Program Origin ••••••••••••••••• ORG Label
2. Symbolic IJiterals:
Example: •••••••••••••.••••••••••••• L = Label
5. Diagnostics:
For: Double defined ,labels
Undefined labels
Illegal labels
Symbol table o~erflow
Constant overflow
Illegal addresses.
46.
7. Listing Controls: During the second pass, the
operator has the choice of printing only the page
number, only the line number or the complete listing.
This is done by enabling the proper bits of the switch
register and has effect even while the listing is
taking place.
If the program does not begin with an origin sta-
tement, the assembler will request one from the oper-
ator. In addition, the operator can select one of
the following options at the beginning of pass 2.
47.
PAGE 24
49.
6.3 STANDARD LIBRARY
5~.
6.4 DIAGNOSTICS
51.
APPENDIX 1
A-f6
BINARY OCTAL· ASCI I 81 NARY OCTAL ASCI I
001010 12 J 101010 52
001011 13 K 101011 53
*
+
001100 14 L 101 100 54 , ( COiVlMA)
0'11101 15 M 101101 55
001110 16 N 101110 56
001111 17 0 101111 57 /
010000 20 P 110000 60 0
010001 21 Q 110001 61 1
010010 22 R 110010 62 2
010011 23 S 110011 63 3
010100 24 T 110100 64 4
010101 25 U 110101 65 5
010110 26 V 110110 66 6
010111 27 W 110111 67 7
011000 30 X 111000 70 8
011001 31 Y 111001 71 9
011010 32 C 111010 72
.
,
011011
011100
33
34 ,
[ (SHIFT K)
( SH 1FT L)
111011
111100
73
74 <
011101 35 ] (SHIFTM) 111101 75 =
76
011110
011111
36
37 .
t ( SHI FT N)
(SHIFT 0)
11111")
111 111 77
>
?
FIG. A.I
A-I
APPENDIX 2
B-~
MNEMONIC DESCRIPTION CODE
ASCI-I--OCTAL
U-REGISTER INSTRUCTIONS
B-·J.
ALU MODE INSTRUCTIONS ®
B-2
MNEMONIC DESCRIPTION CODE
ASCI-I-OCTAL
HLT=~ H F (SPACE)~64~
HLT=1 A F! ~641
HLT=2 L F" ~642
HLT=3 T F# ~643
HLT=4 F$ ~644
HLT=5 I F% ~645
HLT=6 N F& ~646
HLT=7 S F' ~647
HLT=l~ T F( ~65~
HLT=ll R F) ~651
HLT=12 U F* ~652
HLT=13 C F+ . .0653
HLT=14 T F, .0654
HLT=15 I F- .0655
HLT=16 0 F. .0656
HLT=17 N F/ .0657
MNEMONIC DE SC R I P1' ION OF BRANCH CODE
FOR FLAG INS'I'RUC'rION FLAG JIS - - JIC
B-'4
MNEMONIC DESCRIPTION CODE
ASCI-I--OCTAL
B-5
NOT E S
@- # LOGICAL OR
. LOGICAL AND
t LOGICAL EXCLUSIVE OR
AI LOGICAL COMPLEr1ENT OF A
+ ARITHMETIC PLUS OPERATION
ARITHMETIC MINUS OPERATION
B-6