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APPLICATION NOTE
How to Migrate from the
M95 SPI EEPROM to the M25PE SPI Serial Flash
This Application Note describes how to migrate from the M95 family of SPI EEPROMs to the M25PE family
of SPI Serial Flash memories.
EEPROM devices are limited in density due to the cell architecture and technology. Memories based on
Flash technology are more suitable for applications that require higher densities.
The M25PE family of Serial Flash memories have been designed to offer byte granularity to make them
compatible with EEPROMs. For this reason the M25PE devices are the ideal products to complement the
EEPROM portfolio for higher densities (see Figure 1.).
tion
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AI08686
TABLE OF CONTENTS
Figure 1. M95 EEPROM and M25PE Serial Flash Portfolio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PINOUT COMPATABILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Pin Connections for 8 Pin Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
M95 (EEPROM) Hold Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
M25PE (Serial Flash) Reset Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
BOARD LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Cross sections of the MLP and SO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. Comparison of Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 1. Instruction Comparison M95 vs. M25PE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. Additional Instructions in M25PE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
M95 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. M95 Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. M95 Write-Protected Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. M95 Protect State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
M25PE Serial Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CONCLUSION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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AN2081 - APPLICATION NOTE
PINOUT COMPATABILITY
Figure 2. gives the pinout for all the 8 pin packages in the M25PE and M95 families. The only difference
is pin 7, which is a RESET signal in M25PE devices, whereas it is a HOLD signal in M95 devices.
S 1 8 VCC
Q 2 7 RESET (M25PE) HOLD (M95)
W 3 6 C
VSS 4 5 D
AI08681
If neither the Hold nor the Reset inputs are required in the application, then, as both signals are active low,
the pin should be connected High so that these features do not affect the application.
If the features are used, then the application must take into account the difference in their behavior.
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BOARD LAYOUT
The board layout can be adapted to receive the different packages.
■ SO8N compatible with the MLP (5x6mm) footprint
■ SO8W compatible with the MLP (8x6mm) footprint
The tracks of the footprints of the SO8N or MLP (5x6mm) can be stretched to accommodate the footprints
of the SO8W or the MLP (8x6mm).
Note: Care must be taken to avoid any short-circuit between the tracks of the SO8N or the MLP (5x6mm)
footprint and the central conductive pad on the underside of the MLP (8x6mm) package (see Figure 3.).
0.07”
SO8
0.25”
0.04”
MLP
ai07605
Both these footprints can then be inserted inside the SO16W footprint (see Figure 4.).
C
D
RESET C
VCC D
DU DU
DU DU
DU DU
DU DU
S VSS
Q W
S
Q
W
VSS
SO16W footprint
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ARCHITECTURE
Figure 5. shows the Block Diagrams for both the M95 and M25PE devices. The diagrams highlight the
principle differences in the device architecture:
■ Byte Write for M95 devices directly through the SRAM buffer, Byte Write for M25PE using the SRAM
buffer to copy the content of the rest of the page (see PROGRAM AND ERASE GRANULARITY
section for more details)
■ Hardware and Software protection for the M95 devices, Hardware protection on last 256 pages for
M25PE devices (see PROTECTION section for more details).
Last Sector
Q
Q
Byte Write
Byte Write
Software Protection
S Control S Control
HOLD
Logic Logic
RESET
Hardware Protection
W W Hardware Protection
(first 256 pages protected)
Ai08687
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A2 AA
Instruction
Code Address N+2 AAh 55h
AI08683
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FFFFFh
FFFFFh
FFFFFh
AI08684
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Serial Flash
ST’s Serial Flash memory have:
■ an Erase granularity of 256 Bytes (one Page), where the page content is erased to FFh, which is a
higher granularity compared to standard Flash memories that are erased at the block level.
■ a Program granularity of one Byte, where each bit of the byte can be independently programmed to
0 (equivalent to the EEPROM granularity in the case of a pre-erased Byte)
As the Erase and Program granularity are different, there are two different instructions to program and
erase a Serial Flash:
■ Page Erase instruction (erase only)
■ Byte Program instruction (program only)
These two different instructions are useful to optimize the update time or the memory cycling. If an area
is already erased, then the erase operation can be omitted which will speed up the overall programming
time and reduce memory cycling. The erase instruction can also be used to erase an area when the device
is idle, so that when the area is programmed later, only the program operation is required.
To simplify the byte granularity management, Numonyx Serial Flash feature an automatic byte write em-
ulation equivalent to the EEPROM, where like the EEPROM, a Page Write instruction will erase and pro-
gram one byte without knowing its previous value and without changing any other data in the page.
To take the same example as shown in Figure 6., if the application needs to update two bytes located at
address N+2, it has to send the Page Write instruction, followed by address N+2, followed by the two bytes
of data.
To be able to do this, the Numonyx Serial Flash uses an internal 256 Bytes SRAM buffer to backup the
rest of the page, which must be kept unchanged.
The Numonyx Serial Flash performs three different automatic operations (see Figure 8.):
Step 1: data are input sequentially and stored in the corresponding address of the buffer
Step 2: all unaddressed bytes of the page are copied from the memory array into the buffer
Step 3: the addressed page is erased
Step 4: the buffer content is programmed into the addressed page
All these operations are transparent for the application, as they are done automatically with the Page Write
Instruction.
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AN2081 - APPLICATION NOTE
xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh
Address N+2 10h 06h 15h 00h 56h 33h Address N+2 10h 06h 15h 00h 56h 33h
xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh
FFFFFh FFFFFh
xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh
Address N+2 FFh FFh FFh FFh FFh FFh Address N+2 10h 06h AAh 55h 56h 33h
xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh
FFFFFh FFFFFh
AI08685
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AN2081 - APPLICATION NOTE
INSTRUCTION SET
Table 1. shows a comparison of the instructions of the M95 and the M25PE families.
The first time a Serial Flash device is programmed the Page Program instruction (02h) is equivalent to the
EEPROM Write instruction (02h). This is because the Serial Flash is delivered with the content erased, so
the memory can be programmed byte by byte as for the EEPROM.
For subsequent program operations, where the initial byte content is not FFh, the application must use the
Serial Flash Page Write instruction (0Ah) to perform an operation equivalent to the EEPROM Write instruc-
tion (02h).
The M25PE family has additional instructions (see Table 2. ) that are not available in the M95 family.
One of these is the Read Identification instruction which can be used to differentiate the Serial Flash from
the EEPROM, allowing the application to select the appropriate instruction code. As the Read Identifica-
tion instruction is not available in EEPROMs, the EEPROM will remain in High Impedance if this instruction
is sent on the SPI bus.
If the Output line (Q), is connected to VCC through a pull-up resistor or to ground (VSS) through a pull-down
resistor, the application will read FFh or 00h as the EEPROM signature.
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AN2081 - APPLICATION NOTE
PROTECTION
M95 EEPROM
The M95 family has various protection mechanisms:
■ To prevent data corruption, an internal VCC comparator inhibits all the M95 functions if the VCC voltage
is lower than the POR threshold.
■ The non-volatile Block Protect bits, located in the Status Register, allow parts of the memory to be
configured as read-only (see Table 3. and Table 4.).
■ The Hardware Protection mode can be used to prevent write operations in the Status Register,
thereby protecting bits SRWD, BP2, BP1 and BP0 from being modified (see Figure 5.). The mode is
entered by:
– setting the Status Register Write protect bit (SRWD) to 1
– applying a Low-level voltage to the Write Protect pin (W).
Once the Hardware protection mode is entered (State C in Figure 5.), the only way to exit is to apply VCC
on the Write Protect pin W. If the W pin is hardware connected to the ground (VSS), then it is impossible
to change the protection.
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W=1 W=1
SRWD=0 SRWD=1
Software WRSR
State-A State-D
Software WRSR
Hardware W=VSS
Hardware W=VSS
Hardware W=VCC
Hardware W=VCC
Software WRSR
State-B State-C
Hardware Protection:
W=0 W=0 All write accesses to the
SRWD=0 SRWD=1 Status Register are rejected
AI08689
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CONCLUSION
The M25PE is a family of Serial Flash memories with a Serial Peripheral Interface. The M25PE devices
have been designed to compliment ST’s Serial EEPROM family at higher densities, and so may be used
to replace an M95 in an application. The M25PE Serial Flash are fully hardware-compatible with the M95
EEPROMs and are also software-compatible, as long as the minor points highlighted in this application
notes are taken into account.
REFERENCES
The following datasheets are available ( on www.numonyx.com or from your Numonyx distributor):
■ SPI EEPROM
– M95040, M95020, M95010
– M95256, M95128
– M95160, M95080
– M95640, M95320
– M95512
■ SPI Serial Flash
– M25PE10
– M25PE20
– M25PE40
– M25PE80
REVISION HISTORY
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AN2081 - APPLICATION NOTE
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