H386 Journal of The Electrochemical Society, 155 共6兲 H386-H389 共2008兲

0013-4651/2008/155共6兲/H386/4/$23.00 © The Electrochemical Society

Nanocrystalline Zinc-Oxide-Embedded Zirconium-Doped

Hafnium Oxide for Nonvolatile Memories
Jiang Lu,* Chen-Han Lin,** and Yue Kuo***,z
Thin Film Nano and Microelectronics Research Laboratory, Texas A&M University, College Station,
Texas 77843-3122, USA

Memory devices containing nanocrystalline ZnO-embedded Zr-doped HfO2 high-k dielectric film have been prepared and char-
acterized. The memory effect was manifested by the large counterclockwise capacitance–voltage hysteresis, e.g., 1.22 at ⫾6 V
gate bias, and negative differential resistance region in the positive bias current–voltage range. The maximum trapped charge
density of 6.43 ⫻ 1012 cm−2 was obtained after −9 → + 9 → −9 V sweep voltage range. The memory effects were mainly
caused by electron trapping at low bias voltage. A large memory operation window, e.g., 0.90 V, with a long charge-retention time,
e.g., ⬎36,000 s, was achieved under the proper gate-stress voltage. It is a viable dielectric for future nanosize metal-oxide-
semiconductor field-effect transistors and capacitors.
© 2008 The Electrochemical Society. 关DOI: 10.1149/1.2901059兴 All rights reserved.

Manuscript received February 5, 2008. Available electronically April 14, 2008.

Nanocrystal-embedded dielectric structure has been proposed to
replace the polysilicon floating dielectric structure for high-density
nonvolatile memories.1 The current floating-gate memory device
contains polycrystalline-silicon-embedded silicon oxide 共SiO2兲 gate
dielectric that has to be thick to ensure good charge retention. How-
ever, it requires a high write/erase voltage and reduces the program-
ming speed, which limits the shrinkage of the device. The
nanocrystal-embedded dielectric can be easily fabricated into small
devices.2 The embedded nanocrystals, which can be made of differ-
ent materials, enhance the trap and detrap electrons or holes in the
dielectric layer.3-5 Zinc oxide 共ZnO兲, which has a direct bandgap of
3.2 eV, has been made into nanocrystalline zinc oxide 共nc-ZnO兲 for
optic and photovoltaic applications.6 Based on the band diagram
alignment of ZnO/Si, the nc-ZnO embedded gate dielectric should
have better electron-retention characteristic than with the nc-Si-
embedded gate dielectric.7 For sub 65 nm node metal-oxide-
semiconductor field-effect transistors 共MOSFETs兲, a high dielectric
constant 共high-k兲 material is required to replace SiO2 as the gate
dielectric to reduce the leakage current and to improve device
reliability.8 The use of a high-k gate dielectric makes it possible to
prepare a physically thicker film than SiO2 but with the same
equivalent oxide thickness 共EOT兲, which greatly improves both the
operation voltage and data-retention efficiency.9,10 Recently, it was
demonstrated that Zr-doped HfO2 has many improved electrical
properties than the undoped HfO2 and can be prepared into sub
1 nm EOT film.11,12 High-performance memory characteristics are
expected on this kind of nc-ZnO-embedded high-k dielectric. In this
paper, we fabricate nc-ZnO-embedded Zr-doped HfO2 metal-oxide-
semiconductor 共MOS兲 capacitors and investigate their memory char-
acteristics.
800°C N2-annealed ZnO-embedded Zr-doped HfO2 film stack,
which contains a predominant wide peak at 2␪ = 31° corresponding
to nc-ZnO共100兲.13 The average crystal size of the nc-ZnO was about
3.0 nm, determined by the peak location and full width at half-
maximum using the Scherrer equation.14 The top-view transmission
electron microscopy 共TEM兲 micrograph in Fig. 2 shows that the
discretely dispersed nc-ZnO was obtained under this process condi-
tion. The density of nc-ZnO is about 3 ⫻ 1012 cm−2 with a grain
size of 3–5 nm, which is consistent with the XRD result. The alu-
minum 共Al兲 gate electrode layer was sputter deposited on the high-k
stack and subsequently etched into 100 ␮m diameter dots 共7.85
⫻ 10−5 cm−2兲. The back side of the wafer was deposited with Al for
ohmic contact. The complete wafer was annealed at 300°C in form-
ing gas ambient. The overall EOT of the nc-ZnO-embedded MOS
capacitor was 7.80 nm. A control sample without the embedded
nc-ZnO, which had an EOT of 6.0 nm, was also fabricated under the
same conditions for comparison. Electrical properties of the MOS
capacitors were extracted from capacitance–voltage 共C-V兲 and
current–voltage 共I-V兲 measurements using an HP4284A and an
HP4155C, respectively. Electrical properties, such as EOT and flat-
band voltage 共VFB兲, were extracted with the NCSU CVC program
共C-V analysis software developed by the North Carolina State
University兲.15
Results and Discussion
Floating gate characteristics.— Figure 3 shows the I-V curve of
the nc-ZnO-embedded capacitor. The gate voltage was swept from
−5 to +5 V. As the gate bias becomes positive, the tunneling current
changes drastically with the increase in gate voltage, e.g., from 0 to

Experimental
MOS capacitors were fabricated on HF-cleaned p-type
共1015 cm−3兲 wafers. The gate dielectric was composed of Zr-doped
HfO2 tunnel oxide 共EOT ⬇ 2 nm兲, ZnO, and Zr-doped HfO2 con-
trol oxide 共EOT ⬇ 4 nm兲, which were sequentially reactively sput-
ter deposited on the wafer surface in a one pump down without
breaking the vacuum. The Zr-doped HfO2 layers were sputtered
from a composite Zr/Hf 共12/88 wt %兲 target in an Ar/O2 共1:1兲
mixture at 5 mTorr and 60 W. The embedded ZnO layer was sput-
tered from a metallic Zn target in an Ar/O2 共1:1兲 at 5 mTorr and
60 W. Postdeposition annealing was done at 800°C for 180 s in N2
ambient by rapid thermal annealing 共RTA兲 at a ramp-up rate of
50°C/s. Figure 1 shows the X-ray diffraction 共XRD兲 pattern of the

* Electrochemical Society Active Member.

** Electrochemical Society Student Member.
*** Electrochemical Society Fellow. Figure 1. XRD patterns of the nc-ZnO-embedded Zr-doped HfO2 films after
z
E-mail: yuekuo@tamu.edu 180 s 800°C N2 RTA.

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 Journal of The Electrochemical Society, 155 共6兲 H386-H389 共2008兲
Figure 2. Top-view TEM micrograph of the nc-ZnO-embedded in Zr-doped
HfO2 matrix after 180 s 800°C N2 RTA. The high-resolution micrograph is
also shown in the inset.
0.5 V. This is because the holes trapped in the nc-ZnO-embedded
dielectric layer tunnel back to the substrate as the adjacent wafer
region transforms from a hole-rich accumulation layer to an
electron-rich inversion layer. The tunneling current becomes satu-
rated between 0.5 and 1.0 V, because electrons are trapped at the
nc-ZnO sites. The tunneling current then drastically decreases, be-
cause the trapped electrons repel the additional tunneling electrons
due to the coulomb blockade effect. Therefore, an N-shaped wide
peak is observed in the small positive voltage sweep range of the I-V
curve. The presence of an N-shaped wide peak in the I-V curve is
also referred to as the negative differential resistance, which has
been observed in many floating-gate charge-trapping devices.16-18
When the gate voltage is further increased, e.g., beyond 3.0 V, an
inversion layer is fully established. The tunneling current rapidly
increases again at the high-gate-voltage condition. Electrons tunnel
through the dielectric layer following the Fowler–Nordheim
mechanism.16 The inset of Fig. 3 shows no N-shaped wide peak in
the I-V curve of the control capacitor under the same positive-gate-
bias condition. Therefore, nc-ZnO in the Zr-doped HfO2 film is re-
sponsible for the occurrence of the floating-gate behavior in the I-V
curve.
Electron- and hole-trapping mechanisms.— The charge-trapping
characteristics of the nc-ZnO-embedded Zr-doped HfO2 capacitors
were examined using the C-V hysteresis curves. Figure 4 shows C-V
curves of the nc-ZnO-embedded and control capacitors at 1 MHz.
The gate voltage was first swept from −6 to +6 V 共i.e., the wafer
near the dielectric interface changed from accumulation to inver-
sion兲, then swept backward from +6 to −6 V 共i.e., from inversion to
accumulation兲. The C-V hysteresis was quantified by the ⌬VFB, i.e.,
Figure 3. I-V curve of the nc-ZnO-embedded MOS capacitor from −5 to
+5 V. Inset is the I-V curve of the control capacitor from 0 to 5 V.
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H387
Figure 4. C-V curves for control and nc-ZnO-embedded capacitors mea-
sured at 1 MHz. Cox is the accumulation capacitance measured at −6 V.
VFB,reverse − VFB,forward. A large counter-clockwise direction hyster-
esis, e.g., ⌬VFB = 1.22 V, which corresponded to a charge-trapping
density Qot = 3.44 ⫻ 1012 cm−2, was obtained in the
nc-ZnO-embedded capacitor. Because the Qot is close to the sheet
density of nc-ZnO 共⬃3 ⫻ 1012 cm−2兲 estimated from the top-view
TEM micrograph, approximately one charge was trapped by each
nc-ZnO. The control capacitor showed a small counter-clockwise
hysteresis, e.g., ⌬VFB = 0.17 V or Qot = 5.99 ⫻ 1011 cm−2. Because
the flatband voltages of the forward C-V sweep curves, e.g., from
−6 to +6 V, for both control and nc-ZnO-embedded capacitors are
almost the same, the large C-V hysteresis observed in the
nc-ZnO-embedded capacitor should be mainly contributed by the
trapped negative charges 共electrons兲 during the reverse C-V sweep,
e.g., from +6 to −6 V.19 Moreover, the lack of obvious C-V curve
distortion and stretch indicates that the large C-V hysteresis ob-
served in the nc-ZnO embedded capacitor is not contributed by the
unstable charges or interface traps.10,20 Therefore, the embedded
nc-ZnO layer drastically increased the electron trapping capacity by
five times.
Figure 5 shows C-V hysteresis curves measured at different
sweep voltage ranges, e.g., between −4 → + 4 → −4 and −9 →
+ 9 → −9 V. Counter-clockwise hystereses were observed in all
measurements, and the ⌬VFB increases with sweep voltage. The pro-
gressive shift of the flatband voltages are contributed by charge
trapping at the nc-ZnO sites. Figure 6 shows the VFB as a function of
the gate-sweep voltage calculated from Fig. 5 data. The ⌬VFB 共or
memory window兲 increases with sweep voltage, e.g., from 0.704 to
Figure 5. C-V hysteresis curves of nc-ZnO-embedded capacitors in different
sweep-voltage ranges, e.g., between −4 → + 4 → −4 and −9 → + 9 →
−9 V. The C-V curves were measured at 1 MHz and 0.1 V/s. All curves are
counter-clockwise.
 H388 Journal of The Electrochemical Society, 155 共6兲 H386-H389 共2008兲
Figure 6. Flatband voltages in forward and reverse sweep-voltage ranges
from ⫾4 共−4 → + 4 → −4 V兲 to ⫾9 V 共−9 → + 9 → −9 V兲.
2.28 V, which corresponds to the increase of Qot from 1.99 to
6.43 ⫻ 1012 cm−2. The maximum ⌬VFB or charge-storage density
was obtained at the sweep range of −9 → + 9 → −9 V. In the
small sweep-voltage range, e.g., from −4 → + 4 → −4 to −7
→ + 7 → −7 V, VFB at the forward direction remained almost con-
stant, while that at the reverse direction increased with the sweep
voltage. The former indicates that it is difficult to inject holes to the
dielectric structure when the negative gate voltage is small. The
latter indicates that electrons in the inversion layer are easily in-
jected into the nc-ZnO-embedded dielectric layer even when the
positive gate voltage is small. Therefore, the ⌬VFB was mainly in-
creased by electron injection due to the applied positive gate volt-
age. In the large sweep-voltage range, e.g., from −7 → + 7 → −7
to −9 → + 9 → −9 V, the VFB at the forward direction increased
quickly in the negative direction with the increase in sweep voltage,
while that at the reverse direction increased slightly with the in-
crease in sweep voltage. The former indicates that hole injection
occurs at the large negative gate voltage, while the latter indicates
that electron injection reaches saturation above a certain positive
gate voltage. Therefore, the ⌬VFB was mainly influenced by the
hole-injection efficiency in the negative-gate-voltage range. Because
low operation voltage is desirable in nonvolatile flash memory ap-
plications, the nc-ZnO-embedded capacitor can be used to trap and
detrap electrons with a low bias voltage.
Time- and voltage-dependent electron and hole trappings.— The
charge-trapping characteristics of the nc-ZnO-embedded Zr-doped
HfO2 capacitors were examined by the constant gate voltage stress
for different time periods. Figure 7 shows the flatband voltage shift,
i.e., VFB 共after +6 V stress兲–VFB 共fresh兲, increases with the gate
stress time in the dark, which implies the electron trapping is time-
dependent. The flatband voltage shift or electron trapping reaches a
saturation value after a long stress time, e.g., 90 s, in the dark.
However, the flatband voltage shift reaches a saturation value in a
short period when the capacitor is stressed under the light-
illumination condition 共150 W quartz halogen lamp兲, which implies
high electron-trapping efficiency. Because light illumination can
provide a large amount of photon-generated electrons in the inver-
sion layer,21 the slow electron-trapping rate observed in darkness
was caused by the limited supply of free electrons from the lightly
doped p-type Si substrate and slow minority carrier generation-
recombination rate at room temperature. Therefore, a high carrier-
trapping efficiency is possible with the nc-ZnO-embedded MOSFET
if a sufficient supply of minority carriers is available.
Electron- and hole-trapping characteristics of the
nc-ZnO-embedded Zr-doped HfO2 capacitors were also examined
using constant positive or negative gate voltage stress. Figure 8
shows that the flatband voltage shifts and memory windows increase
with the magnitude of the stress voltages. Here, the flatband voltage
shift is VFB 共after 90 s stress兲–VFB 共fresh兲 and the memory window
is flatband voltage shift 共positive gate voltage兲–flatband voltage shift
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Figure 7. Flatband voltage shift as a function of +6 V gate-stress time in
darkness and under illumination at room temperature.
共negative gate voltage兲. Similar to the C-V voltage sweeping result
in Fig. 6, in the small gate-stress-voltage range, the memory window
increase was mainly contributed by the increase of the positive flat-
band voltage shift due to net electron trapping; in the large gate-
stress-voltage range, the memory window increase was mainly con-
tributed by the increase of the negative flatband voltage shift due to
hole trapping. Electron trapping reached a saturation state after a
certain large positive stress voltage was applied.
Time- and voltage-dependent erasing efficiency.— After the fresh
capacitors were stressed at +6 V for 90 s, charges were erased with
different gate voltages or time periods. Figure 9 shows that the −6 V
10 s or −7 V 10 s “erase” stress is insufficient to erase all trapped
electrons. It also shows −6 V is insufficient to erase all trapped
electrons even after a long erasing time, e.g., 90 s. A high gate bias
of −8 V 10 s erase is required to fully erase these trapped electrons.
A similar phenomenon is observed after +5 or +7 V 90 s write. The
−8 V 10 s gate stress is required to fully erase the trapped electrons
after +5 V 90 s or +7 V 90 s write. Figure 10 shows that the −8 V
10 s erase stress is also sufficient to fully erase charges trapped by
+8 V 90 s stress. A small negative voltage cannot fully erase the
trapped electrons even after a long period of time. This phenomenon
is consistent with the previous observation that the amount of
trapped electrons reached a saturation number after the 90 s stress.
Electrons are deeply trapped at the nc-ZnO sites at this stage. The
deeply trapped electrons can only be erased with a strong erase
condition, e.g., −8 V 10 s. Moreover, Fig. 10 also shows that both
−8 V 90 s and −9 V 10 s erase conditions lead to the excessive
negative flatband voltage shift due to the trap of extra holes from the
accumulation layer.
Charge-retention efficiency.— The charge-retention efficiency of
the nc-ZnO-embedded capacitor was examined by the VFB vs stress-
Figure 8. Flatband voltage shifts as a function of gate-stress voltages for a
90 s stress time measured in darkness and at room temperature.
 Journal of The Electrochemical Society, 155 共6兲 H386-H389 共2008兲
Figure 9. C-V curves of nc-ZnO-embedded sample at fresh, +6 V 90 s
write, and different erase stress voltages and time periods. Cox is the accu-
mulation capacitance measured at −3 V.
release time curve. After the write stress was released, small sweep-
voltage range 共i.e., −2 to +1 V兲 C-V measurements were performed
every 3000 s to determine the change of VFB during this interval.
Because only negligible charges were injected during these small-
range C-V measurements, the change of VFB with stress-release time
represented the capacitor’s charge-retention characteristics.
Figure 11 shows the VFB of the nc-ZnO-embedded capacitor as a
function of the release time after write or erase. The electron charge-
retention characteristics of the nc-ZnO-embedded capacitor were
measured at room temperature after +6 V 90 s write stress. The
flatband voltage of the fresh, unstressed sample was −0.78 V. After
+6 V 90 s write stress, the flatband voltage became 0.4 V due to
electron trapping. It decreased with time until reaching 0.2 V after
36,000 s, which is equivalent to 17% loss of the originally trapped
electrons. The erase tests were performed with a +6 V 90 s write
stress followed by a −7 or −8 V 10 s erase stress. A large memory
window of 0.90 V was maintained between the write 共after +6 V
90 s stress兲 and erase 共after −8 V 10 s stress兲 states for at least
36,000 s 共Fig. 11兲. Although −7 V 10 s erase is insufficient to fully
erase the trapped electrons as shown in Fig. 9 and discussed in the
previous section, a large memory window of 0.7 V was maintained
for at least 36,000 s. The excellent electron-retention characteristics
show that electrons are deeply trapped at the nc-ZnO sites.
Conclusion
Memory effects of the nc-ZnO-embedded Zr-doped HfO2 high-k
dielectric capacitors have been studied. Both I-V and C-V data
showed that electrons were strongly retained at the nc-ZnO sites in
Figure 10. C-V curves of nc-ZnO-embedded sample at fresh, +8 V 90 s
write, and different erase stress voltages and time periods. Cox is the accu-
mulation capacitance measured at −3 V.
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H389
Figure 11. Charge-retention characteristics of nc-ZnO-embedded Zr-doped
HfO2 after +6 V 90 s write, −7 V 10 s erase, and −8 V 10 s erase condi-
tions.
the dielectric structure when the gate was positively biased. A large
memory window with a long charge-retention time was obtained
under a proper gate-stress condition. Because the nc-ZnO-embedded
Zr-doped HfO2 high-k film can be prepared into a small EOT with a
large physical thickness, it is a viable dielectric structure for future
nanosize MOSFETs and capacitors.
Acknowledgments
The authors thank Adam Birge and Rui Wan for preparing the
programs for the electrical measurements. This project was partially
supported by NSF projects DMII-0429176 and CMMI-0654172.
Texas A&M University assisted in meeting the publication costs of this
article.
References
1. S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Cabbe, and K. Chan, Appl. Phys.
Lett., 68, 1377 共1996兲.
2. J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, IEEE Electron Device
Lett., 18, 278 共1997兲.
3. J. Lu, Y. Kuo, J. Yan, and C.-H. Lin, Jpn. J. Appl. Phys., Part 2, 45, L901 共2006兲.
4. Y. Kuo, J. Lu, J. Yan, and C.-H. Lin, Proceedings of the 6th IEEE Conference on
Nanotechnology, IEEE, p. 469 共2006兲.
5. Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, IEEE Trans. Electron Devices,
49, 1606 共2002兲.
6. Ü. Özgür, Y. I. Alivov, C. Liu, A. Teke, M. A. Reshchikov, S. Doğan, V. Avrutin,
S.-J. Cho, and H. Morkoç, J. Appl. Phys., 98, 041301 共2005兲.
7. D. G. Baik and S. M. Cho, Thin Solid Films, 354, 227 共1999兲.
8. International Technology Roadmap for Semiconductors, Semiconductor Industry
Association, San Jose, CA 共2006兲.
9. D. W. Kim, T. Kim, and S. K. Banerjee, IEEE Trans. Electron Devices, 50, 1823
共2003兲.
10. J. J. Lee, X. Wang, W. Bai, N. Lu, and D. L. Kwong, IEEE Trans. Electron
Devices, 50, 2067 共2003兲.
11. J. Yan, Y. Kuo, and J. Lu, Electrochem. Solid-State Lett., 10, H199 共2007兲.
12. Y. Kuo, J. Lu, S. Chatterjee, J. Yan, T. Yuan, H.-C. Kim, W. Luo, J. Peterson, and
M. Gardner, ECS Trans., 1共5兲, 447 共2006兲.
13. Y. Du, M.-S. Zhang, J. Hong, Y. Shen, Q. Chen, and Z. Yin, Appl. Phys. A, 76, 171
共2003兲.
14. L. V. Azaroff, Elements of X-Ray Crystallography, McGraw-Hill, Inc., New York
共1968兲.
15. J. Hauser and K. Ahmed, Characterization and Metrology for ULSI Technology,
pp. 235–239, American Institute of Physics, Woodbury, New York 共1998兲.
16. T. Maeda, E. Suzuki, I. Sakata, M. Yamanaka, and K. Ishii, Nanotechnology, 10,
127 共1999兲.
17. M. Shalchian, J. Grisolia, G. B. Assayag, H. Coffin, S. M. Atarodi, and A. Cla-
verie, Solid-State Electron., 49, 1198 共2005兲.
18. D. N. Kouvastsos, V. Ioannou-Sougleridis, and A. G. Nassiopoulou, Appl. Phys.
Lett., 82, 397 共2003兲.
19. D. K. Schroder, Semiconductor Material and Device Characterization, 2nd ed.,
Chap. 6, John Wiley Sons, New York 共1998兲.
20. C. J. Park, H. Y. Cho, S. Kim, S.-H. Choi, R. G. Elliman, J. H. Han, C. Kim, H. N.
Hwang, and C. C. Hwang, J. Appl. Phys., 99, 036101 共2006兲.
21. Q. Wan, N. L. Zhang, W. L. Liu, C. L. Lin, and T. H. Wang, Appl. Phys. Lett., 83,
138 共2003兲.