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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
Design and Analysis of CMOS LNAs with
Transformer Feedback for Wideband Input
Matching and Noise Cancellation
Liang Wu, Member, IEEE, Hiu Fai Leung, and Howard C. Luong, Fellow, IEEE
Abstract— This paper presents a new transformer-feedback
technique for RF and millimeter-wave (mmW) low-noise ampli-
fiers (LNAs). The working principle of conventional LNAs
using transformers is analyzed to show their underlying perfor-
mance trade-off between input matching and noise figure (NF).
To mitigate this issue, a new feedback technique is developed
by constructing a drain-to-gate feedback path around the input
transistor with a transformer and then further demonstrated
by two LNA prototypes. In the first LNA aiming for software-
defined radio (SDR) applications, the proposed technique not
only achieves wideband input matching but also enables noise
cancellation through an auxiliary out-of-phase forward path.
Fabricated in 0.13-µm CMOS, the LNA measures voltage
gain >14 dB, minimum NF of 1.8 dB, IIP3 of 1.8–3.8 dBm,
and S11 < −10 dB over a frequency range of 1.2–6.6 GHz, while
consuming 13.2 mW. The second LNA implemented in 65-nm
CMOS operates from 55 to 65 GHz and achieves a 16.4-dB
conversion gain and a 6.8-dB minimum NF, with power dis-
sipation of 33.6 mW. Particularly, the measured S11 remains
below −10 dB from 49.5 to 67 GHz.
Index Terms— Input matching, low-noise amplifier (LNA),
millimeter-wave (mmW), noise cancellation, noise figure (NF),
shunt-shunt feedback, software-defined radio (SDR), transformer,
wideband.
I. I NTRODUCTION
O VER the last decades, the frequency spectrum at
several GHz has been exploited extensively to provide
various wireless communication services. To maximize the
spectrum utilization and to reduce both the form factor
and the hardware cost, versatile communication systems
such as reconfigurable multi-band transceivers and software-
defined radios (SDRs) [1] which can support diverse wireless
standards are highly desired. Usually, wide frequency coverage
of 0.8–6 GHz is required for the SDRs to accommodate most
of the major RF standards. On the other hand, the spectrum
congestion at RF is motivating wireless communications
Manuscript received September 20, 2016; revised December 11, 2016 and
January 4, 2017; accepted January 5, 2017. The Project 61504114 supported
by NSFC is acknowledged. This paper was recommended by Associate Editor
H. Sjoland.
L. Wu is with the State Key Laboratory of Millimeter Waves (HK),
City University of Hong Kong, Kowloon, Hong Kong and also with City
University of Hong Kong Shenzhen Research Institute, Shenzhen, China
(e-mail: liang.wu@cityu.edu.hk; eewuliang@ee.ust.hk).
H. F. Leung is with Kinetic Technologies HK Ltd., Hong Kong.
H. C. Luong is with The Hong Kong University of Science and Technology,
Kowloon, Hong Kong (e-mail: eeluong@ee.ust.hk).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2017.2649844
1549-8328 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1
shifting their operating frequencies into millimeter-
wave (mmW) regime because of the large available bandwidth.
In particular, the unlicensed band across 57–66 GHz [2] has
been receiving a great deal of research interest. Though the
relative bandwidth is much smaller compared to RF SDRs,
the 9-GHz absolute bandwidth is nontrivial due to the more
dominant parasitic at much higher frequencies. In fact, for
both SDRs and 60-GHz systems, the wideband operation is
a common critical issue when implementing the transceivers.
More specifically, it imposes significant challenges on the RF
front-end design, especially the LNA, which has to provide
good input matching, low noise figure (NF) and high gain
over the entire frequency bands of interest for the receiver.
For wideband RF LNAs, there have been many solu-
tions reported. Distributed amplifier topology [3]–[5] can
achieve simultaneous broadband input matching and high gain.
However, the distributed architecture suffers from high power
consumption and large chip area attributed to the use of
several spiral inductors or transmission lines. Common-gate
amplifiers [6]–[9] can realize broadband input matching by
properly designing the input transistor’s transconductance
at the expense of large current consumed. Together with
switchable inductor [6] or inductive peaking [7] techniques
at the output, some common-gate LNAs fulfilling the ultra-
wideband (UWB) operation from 3.1 to 10.6 GHz have
been demonstrated. Theoretically, the NF of a common-gate
LNA is around 2.2 dB if long-channel transistors are used.
For short-channel devices in advanced CMOS process, the
NF is even worse (>3 dB). Alternatively, amplifiers with
negative feedback can also realize wideband amplification due
to its capability to tailor the input impedance for matching.
Featuring small chip area, active-feedback [10]–[12] and
resistive-feedback [13]–[17] types are popular, but the active
devices or resistors in the feedback loop inevitably contribute
additional noise and lower the gain, resulting in NF degra-
dation. Some recent literatures also proposed to implement
reactive-feedback by using transformers [18]–[19]. With mag-
netic coupling between the input MOSFET’s gate and source
nodes, the LNA in [18] achieved broadband operation for
the UWB.
As a contrary, there are not many wideband techniques for
mmW LNAs reported. First of all, due to the non-negligible
parasitics, both the active-feedback and the resistive feedback
techniques at RF become unsuitable. Instead, the conventional
inductive source-degeneration topology is widely deployed
for input matching, marginally covering the frequency range
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2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

as follows [25]:
 
1
Gm ≈ 1 + gm1 (1)
n
   
1 1 1 1 2
Yin ≈ + 1+ gm1 + sC gs 1 + (2)
s L1 n n n
where C gs represents the gate-to-source capacitance of the
input transistor M1 , and n is the turn ratio.
According to (2), the input admittance is composed of both
real and imaginary parts. Input matching can be realized by
Fig. 1. Conventional shunt-series transformer-feedback LNA: (a) schematic,
and (b) a small-signal model. resonating out the imaginary part and setting the real part
to Rs :  
1 1 1
= 1+ gm1 . (3)
required [20]–[22]. Unfortunately, it might not be sufficient Rs n n
in the presence of PVT variations. The common-gate con- As such, the quality factor of the input matching network
figuration is a good solution to widening the input matching can be written as:
bandwidth, but it suffers from the same limitations on NF and Rs 1 1
power consumption as RF LNAs [23]. In [24], transformer- Q in = = · ·n (4)
2π f 0 L 1 2π f 0 L 1 G m
feedback between the drain and the source was proposed for
60-GHz LNAs, but the input matching bandwidth achieved is where f0 is the resonant frequency of the matching network.
very narrow. Normally, Rs is 50  and thus the quality factor can be low
In this work, a simple transformer-feedback technique suit- to implement wideband input matching.
able for both SDR LNAs and wideband mmW LNAs is In circuit design, the transconductance gm1 and hence G m is
proposed. Compared to [25] in which the technique was first desired to be large to optimize the NF. Meanwhile, the trans-
presented, more analysis, design considerations and experi- former’s turn ratio n needs to increase with gm1 to maintain
mental results are included. More importantly, in addition to good input matching, as indicated by (2). However, the turn
the SDR LNA in [25], a new prototype operating at 60 GHz ratio cannot be too large owing to physical limitations. As the
is designed and implemented. Detailed analysis indicates that turn ratio increases, the parasitic capacitance of the primary
the proposed technique features wideband input matching and coil will increase and limit the self-resonant frequency of the
better performance trade-off than conventional shunt-series transformer. Additionally, the coupling factor will decrease,
transformer-feedback solutions. Moreover, noise cancelling by which is not desired because the circuit will become more
a feedforward path can be constructed to further improve the sensitive to magnetic coupling from other passive components
noise performance of the SDR LNA. Specifically, the paper is and circuits within the same chip. Consequently, the require-
organized as follows. Section II analyzes the working prin- ment of wideband input matching and the practical imple-
ciple of the conventional shunt-series transformer-feedback mentation of transformers impose an upper limit on the input
technique for common-source LNAs. Section III discusses the transconductance gm1 , which in turn restricts the NF reduction
proposed so-called load-isolated transformer-feedback (LI-TF) in conventional shunt-series transformer-feedback LNAs.
technique, including the theoretical analysis and the circuit
topology. In Section IV, detailed circuit implementation of III. P ROPOSED L OAD -I SOLATED
an SDR LNA with noise cancellation is described. Section V T RANSFORMER F EEDBACK
presents another LNA prototype working at 60 GHz. The above analysis indicates that it is critical to reduce
In Section VI, experimental results of the LNAs are shown. the coefficient of gm1 in (2) such that gm1 can be increased
Finally, Section VII concludes the paper. to improve the NF without degrading the input matching.
In fact, the aforementioned coefficient is partially attributed
II. C ONVENTIONAL S HUNT-S ERIES to the transconductance degradation caused by source degen-
T RANSFORMER F EEDBACK eration. If the secondary coil is moved from the source to
A conventional shunt-series transformer-feedback LNA is the drain of the input transistor M1 as shown in Fig. 2(a),
shown in Fig. 1(a). The primary coil (L 1 ) of the trans- the transconductance degradation can be avoided. With the
former is connected in parallel with the gate of the input small-signal model in Fig. 2(b), the input admittance can be
transistor M1 , while the secondary coil (L 2 ) is in series calculated as:
2
with the source. Their polarity is opposite such that a neg-
n gm1 + sC L n 2
k k
1
ative feedback is formed. Compared to resistive feedback Yin = +   + sC gs (5)
s L1 1 + s2 L2CL 1 − k2
or active feedback, the transformer-feedback contributes less
noise at the expense of more chip area [18]. By using the where C L represents the loading capacitance. To avoid insta-
small-signal model in Fig. 1(b) and assuming the coupling bility, the real part of the input admittance should be positive,
factor k = 1 for simplicity, the overall effective transcon- indicating that ω2 (1 − k 2 )L 2 C L should be smaller than 1.
ductance G m and the input admittance Yin can be derived As a result, the denominator of the second term in (5) becomes
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WU et al.: DESIGN AND ANALYSIS OF CMOS LNAs WITH TRANSFORMER FEEDBACK 3

Fig. 2. Shunt-shunt transformer-feedback LNA: (a) schematic, and

(b) a small-signal model.

Fig. 4. Proposed noise cancellation technique: (a) schematic, and

(b) a small-signal model.

source resistance Rs using transformers with the same turn

ratio n, the proposed LI-TF technique allows the LNA to have
a larger transconductance gm1 than the conventional shunt-
series feedback, as indicated by (3) and (10). Quantitatively,
for a typical value of n around 2 to 3, the transconductance
could be 33% to 50% higher. Correspondingly, the NF would
get improved because it decreases as gm1 increases.

IV. SDR LNA W ITH N OISE C ANCELLATION

Fig. 3. Proposed load-isolated transformer-feedback (LI-TF) LNA:
(a) schematic, and (b) a small-signal model. A. Proposed Noise Cancellation Technique
In the proposed LI-TF topology, gm1 still cannot be arbi-
trarily enlarged owing to the presence of n in the denominator
less than 1, resulting in additional limitation on gm1 for noise
of the input admittance’s real part, as pointed out earlier when
optimization.
discussing the input matching in Section II. To further improve
To address this issue, a cascode device Mc is utilized to
the NF, a noise cancellation technique is proposed by first
isolate the loading capacitance C L from the secondary coil,
performing noise analysis and then constructing an auxiliary
as shown in Fig. 3(a). By doing so, the current generated by
feedforward path to cancel some of the noise.
M1 completely flows through the secondary coil L 2 and then
A small-signal mode incorporating the noise current origi-
feeds back to the input. With the small-signal model shown
nated from M1 for the proposed LI-TF is depicted in Fig. 4(a).
in Fig. 3(b), the overall effective transconductance G m and
Assuming the input resonant tank composed of L 1 and C gs
the input admittance of the so-called load-isolated transformer-
resonates at the desired frequency, its equivalent parallel resis-
feedback (LI-TF) can be derived as:
tance is much larger than the source resistance Rs . As such,
G m = gm1 (6) the effective noise voltage at Node A can be derived as:
1 k − nk Rs i N1
Yin = + gm1 + sC gs . (7)
s L1 n vA = (11)
1 + nk gm1 Rs
Furthermore, input matching can be implemented by res-
onating out the imaginary part and making the real part of Yin where i N1 is the noise current contributed by M1 .
equal to 1/Rs , which is expressed as: At the output, the noise current due to M1 can be calcu-
lated as:
1 k i N1
= gm1 . (8) i oN1 = −i 2 = . (12)
Rs n 1 + nk gm1 Rs
Again, k = 1 is assumed for simplicity and then (7) and (8)
From (11) and (12), it can be observed that v A and i oN1
can be simplified as: originated from the same noise source i N1 are out of phase.
1 1 As shown in Fig. 4(b), by adding an extra transistor M2 to
Yin ≈ + gm1 + sC gs (9)
s L1 n sense v A and then combining its output current with i oN1 , the
1 1 overall noise current at the output can be written as:
= gm1 . (10)  
Rs n 1 − nk gm2 R S i N1

By comparing (9) to (2), it can be observed that the i oN1 = (13)
1 + nk gm1 Rs
transconductance degradation term, i.e. (1 + 1/n) is success-
fully eliminated. Consequently, for input matching to the same where gm2 is the transconductance of M2 .
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4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

Fig. 5. (a) Simulated input-referred noise contributed from the source Fig. 6. Simulated and calculated noise factors: (a) using NMOS, and
(b) using PMOS in the noise-cancelling path.
resistance and the input transistors M1 and M2 , and (b) calculated and
simulated noise factor F0 .
By including the noise from the load, the noise factor of
the whole LNA can be derived as:
As M2 is outside the LI-TF loop and doesn’t have contribu- 4
tion to the real component of the input admittance, the input F = F0 + (16)
R P R S (gm1 + gm2 )2 β 2
matching can still be simply implemented by satisfying (8).
Equations (13) and (8) indicate that the noise originated where R P is the equivalent resistance of the load, and β is
from M1 can be reduced. Particularly, if gm1 = gm2 , the a gain degradation factor that characterizes the phenomenon
noise from M1 can be completely cancelled at the output. that only a portion of the signal current generated by M1 and
In addition, since both M1 and M2 contribute to the over- M2 flows into Mc . By denoting the transconductance of the
all transconductance, the total transconductance becomes cascode transistor as gmc , and the output impedance of the
(gm1 + gm2 ). With the noise from both M1 and M2 taken into transistors M1 and M2 as ro1 and ro2 , respectively, β can be
written as:
account, the noise factor F0 can be calculated as: ro1 //ro2
β= . (17)
γ1 (gm1 − gm2 )2 4γ2 gm2 ro1 //ro2 + 1/gmc
F0 = 1 + + (14)
gm1 (gm1 + gm2 ) Rs 2
(gm1 + gm2 )2 Rs If M1 and M2 are both NMOS, and their gate-to-source
voltages are exactly the same, then their output impedance
where γ1 and γ1 are the noise coefficients of M1 and M2 , is inversely proportional to the transconductance, i.e.
respectively. By assuming γ1 = γ2 = γ , (14) can be ro1 /ro2 =gm2 /gm1 ≡ α. In addition, as Mc is usually designed
simplified as: to have the same size of the input device (M1 and M2 here),
γ
F0 = 1 + . (15) its transconductance can be approximated as (1 + α)gm1 by
gm1 Rs assuming the same bias voltages as M1 . Accordingly, (16)
Surprisingly, the noise factor is independent of gm2 . can be simplified as:
In other words, the auxiliary feedforward path can help  
−1 2
increase the LNA gain without degrading the noise factor. γ 4 ro1 + gm1
F =1+ + · .
To verify this, SpectreRF simulations have been performed. gm1 Rs 2
R P R S gm1 (1 + α)2 ro1
The input-referred noise contributed by the source resistance (18)
Rs , M1 and M2 is plotted in Fig. 5(a). As gm2 /gm1 varies
from 0 to 1, the noise contribution from M1 is reduced while Equation (18) indicates that a larger gm2 can help improve
that from M2 is increased, but their overall noise is almost the overall noise factor by suppressing the noise from the
constant. Fig. 5(b) compares the noise factor obtained from load more, though it doesn’t have any effect on F0 . Fig. 6(a)
simulation and from calculation using (15), showing close plots both the calculated and the simulated noise factors
agreement with each other. versus gm2 /gm1 , showing good agreement. As gm2 gradually
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WU et al.: DESIGN AND ANALYSIS OF CMOS LNAs WITH TRANSFORMER FEEDBACK 5

approaches gm1 , it turns out that the NF improvement appears

less significant but the power consumption still has to increase
proportionally. Therefore, a design trade-off between noise
factor and power consumption exists.
To save power consumption, PMOS can be utilized in the
noise-cancelling path to enable current reuse. For M1 and M2 ,
it is still approximately true that ro1 /ro2 = gm2 /gm1 . However,
Mc needs to be scaled down proportionally as M2 and thus gm2
increase. Therefore, gmc can be approximated as (1 − α)gm1 .
Accordingly, (16) can be simplified to be:
 2
γ 4 ro1 + 1+α
1−α · gm1
1
F =1+ + 2 (1 + α)2
· .
gm1 Rs R P R S gm1 ro1
(19)
Again, both the calculated and simulated noise factors are
plotted, as shown in Fig. 6(b). The relatively large discrepancy
is due to the significant parasitic capacitance contributed by
M2 at the source node of Mc , which is not modelled in (19).
As gm2 gradually increases, the noise factor gets improved
until α = 0.4. After that, further increasing gm2 will degrade
the noise performance. In fact, it is due to the gain degradation
factor β, which decreases too much when a large portion of
the output current from M1 is flowing into M2 instead of Mc .

B. Circuit Implementation
Based on the proposed LI-TF technique, a wideband differ- Fig. 7. The proposed SDR LNA: (a) schematic, (b) transformer layout.
ential LNA for SDR receiver front-ends from 1 GHz to 6 GHz
is designed. Fig. 7(a) shows the schematic. The input matching
is simply realized by properly designing gm1 using NMOS
according to (8). Moreover, the proposed noise cancellation
technique is employed. To reduce the power consumption,
gm2 is implemented by PMOS in the noise-cancelling path
for current reuse and gm2 /gm1 is designed to be around 0.4.
Overall, compared with complete cancellation (gm2 /gm1 = 1)
using NMOS, the partial noise cancellation with PMOS can
save around 50% power while the NF is ∼ 0.2 dB higher.
With the current-reuse topology, a portion of the DC current
through M1 is steered out to M2 instead of completely flow-
ing through Mc , resulting in gain degradation of the LNA.
To lower the source impedance of Mc , gm -boosting [27] is
Fig. 8. The proposed load-isolated transformer-feedback (LI-TF) at mmW
employed, as shown in Fig. 7(a). By simply cross-connecting frequencies: (a) schematic, and (b) small-signal model.
the cascode differential devices using two capacitors with
capacitance much larger than the gate-to-source capacitance of utilized directly, then the non-negligible parasitic capacitance
the transistor, i.e. CC  C gs , the effective transconductance at the source of Mc would degrade the gain and also make
is boosted to 2gmc while the induced gate noise is negligible. Mc contribute a great deal of noise. To avoid this problem and
At the output, inductive-series peaking is employed to optimize the noise performance, a simple common-source con-
achieve −3 dB bandwidth of >6 GHz. figuration can be employed. As shown in Fig. 8(a), the cascode
The layout of the transformer is shown in Fig. 7(b). The device is eliminated and the loading capacitance C L as well
primary and the secondary coils are interleaved to maximize as the inductive load is connected to Node B. By comparing
the coupling and save chip area. Simulated in ADS Momen- its small-signal model in Fig. 8(b) to the model in Fig. 3(b),
tum, the inductance of the two coils is 6.9 nH and 2.1 nH, it can be observed that both the input and the transformer-
with a coupling factor of ∼0.72. feedback parts are identical. To be more specific, the current i 2
generated by the input transistor M1 completely flows through
V. 60-GHz W IDEBAND LNA the secondary coil L 2 before going to the load. As such,
At mmW frequencies, if the LI-TF technique using a the current fed-back into the primary coil L 1 is not affected
cascode device for isolation as illustrated in Fig. 3(a) is by the load. Therefore, the load gets isolated equivalently
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6 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
Fig. 9. The proposed 60-GHz LNA: (a) impedance transformation at the input, (b) transformer layout, and (c) schematic.
by the secondary coil and the input admittance derived is
the same as (7) such that the proposed LI-TF technique
can be extended for mmW LNAs. On the other hand, for
the noise cancellation, it becomes much less effective as the
frequency approaches 60 GHz. There are mainly two reasons.
Firstly, the parasitic of the transistors is more dominant at
high frequencies. Using extra transistors in the feedforward
path would inevitably increases the total parasitic capacitance,
resulting in significant quality factor degradation of the input
matching network and hence worse NF. Secondly, the phase
difference between the two correlated noise currents from
the main amplifying path and the auxiliary feedforward path
cannot be guaranteed to be 180◦ at such high frequencies due
to the intrinsic delay of the transistors and the parasitics.
To demonstrate the proposed LI-TF technique at mmW
frequency, a 60-GHz LNA is designed. Ideally, a matching
network that can simultaneously achieve 50- input matching,
minimum NF, and maximum gain would be perfect. However,
it is almost impossible in practice because the respective
optimal impedances corresponding to the minimum NF and
the maximum gain for a transistor are usually not the same,
and both are different from 50 . In this design, the source
impedance Rs = 50 is first transformed to an impedance Z A
which corresponds to the lowest NF of the input transistor, and
then the proposed LI-TF technique is employed to match the
input impedance of the LNA to Z A . By doing so, both optimal
NF and 50- input matching can be achieved. Meanwhile,
the realized gain would be sacrificed a litter compared to the
maximum value. Fortunately, as a single amplifier stage is not
able to provide sufficient gain for the LNA and thus more than
one stage is generally required, the little gain degradation in
the first stage is not a problem. As illustrated in Fig. 9(a), by
connecting a capacitor C1 in series with Rs = 50 and then
form an L-match network with L 1 , impedance transformation
from Rs to Z A is realized:
 
1 1  1 Q 2s
=  + j ωC1 =   + j ωC1
ZA Rs Rs Q 2s + 1 Q 2s + 1
(20)

where Q s = (ω Rs C1 )−1 . As Rs is different from 50 ,
the real part of Yin generated from the transformer feed-
back, i.e. (gm1 k/n), should be adjusted for input matching.
As discussed in Section III, a larger turn ratio n is desired to
allow higher gm1 for better NF. However, n cannot be large in
practice due to two limitations. First, at 60 GHz, the parasitic
capacitance is significant and thus imposes an upper limit
on L 1 . Second, the weak magnetic coupling at high frequency
doesn’t allow a very small L 2 . Therefore, n is implemented to
be ∼1.1. As a result, compared to conventional input matching
solutions that are not based on transformer feedback, the NF
improvement due to the flexibility of using higher gm1 is
minimal. Fortunately, the LI-TF technique can still achieve
wideband input matching, which is important and useful at
mmW frequencies as mentioned earlier in Section I. Moreover,
comparison with the conventional shunt-series transformer
feedback by simply using (3) and (10) reveals that the
LI-TF technique allows gm1 of ∼90% higher and thus features
lower NF.
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WU et al.: DESIGN AND ANALYSIS OF CMOS LNAs WITH TRANSFORMER FEEDBACK 7

Fig. 10. Chip micrograph of the SDR LNA. Fig. 12. Measured and simulated gain of the SDR LNA.

Fig. 11. Measured and simulated S11 of the SDR LNA.

Fig. 13. Measured and simulated NF of the SDR LNA.

Fig. 9(c) depicts the schematic of the two-stage LNA

with the proposed LI-TF technique. Again, fully differential
topology is employed not only to improve the common-
mode and even-order rejection but also to minimize the
effect of parasitic inductance, which is quite significant at
mmW frequencies. For the first stage, the LI-TF technique
based on the common-source configuration is utilized. In the
second stage, cascode structure is employed to achieve high
gain and to enable variable-gain control via current-steering.
In addition, an inductor is connected between the input stage
and the cascode stage for gain enhancement and noise reduc-
tion [27]. Between the first and the second stages, an inter- Fig. 14. Measured and simulated IIP3 of the SDR LNA.
stage matching is inserted to increase the current through L 2
and thus the gain. For testing purposes, a balun (L p and L s )
consumes 11 mA from a 1.2-V supply. The measured S11
and two capacitors (C Balun ) are integrated on chip to convert
is below −10 dB from 1.2 to 6.6 GHz, demonstrating good
the single-ended input to differential. At the output, an output
wideband input matching, as shown in Fig. 11. The voltage
buffer and another balun are included for differential-to-single-
gain was measured with a network analyzer to obtain S21 and
ended conversion and driving the 50- impedance of the
then the on-chip buffer for testing purposes was de-embedded.
equipment.
As shown in Fig. 12, the voltage gain measures a maximum
In the layout, the two transformers for differential operation
value of 14 dB with the −3-dB bandwidth over 7 GHz. For the
are combined, as shown in Fig. 9(b). To optimize the coupling
NF, it was measured by a spectrum analyzer (Agilent E4440A)
factor, the two coils are interleaved. EM simulations indicate
equipped with NF measurement personality. The minimum
that the inductance of the primary and the secondary coils are
value measures 1.8 dB while the average value is <2 dB from
60 pH and 50 pH, respectively, and their magnetic coupling
1.8 to 5.6 GHz and <3.4 dB from 1.2 to 6.6 GHz, as shown
factor is around 0.4.
in Fig. 13. Two-tone test with frequency offset of 1 MHz was
performed and the IIP3 was extrapolated at the input power
VI. E XPERIMENTAL R ESULTS
of about −25 dBm. Fig. 14 plots the measured IIP3 , whose
A. Measurement of the SDR LNA range is 1.8–3.8 dBm from 1.2 to 6.6 GHz. By comparing the
The SDR LNA with the proposed LI-TF and noise can- measurement with the simulation results, it can be observed
cellation technique shown in Fig. 7(a) was fabricated in a that they agree well with each other.
1P8M 0.13-μm CMOS process. For testing purpose, a voltage Table I summaries the performance of the SDR LNA and
buffer is included at the output to drive the 50- impedance compares that with recently published wideband LNAs. For
of the equipment. Fig. 10 shows the chip micrograph and the the comparison of different topologies and techniques, the
core area is 0.94 × 0.34 mm2 excluding pads. The SDR LNA figure of merit (FoM) considering the linearity [28] as defined
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8 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

TABLE I
P ERFORMANCE S UMMARY AND C OMPARISON WITH W IDEBAND LNA S

Fig. 15. Chip micrograph of the 60-GHz LNA. Fig. 16. Measured and simulated S11 of the 60-GHz LNA.

below is included.
G[1] · BW [G H z] · Li neari t y[mW ]
FoM = (21)
PDC [mW ] · (F − 1)
where G is the average gain, BW is the bandwidth, PDC is
the power consumed by the core circuitry, and F is the
noise factor. With the proposed LI-TF and noise cancella-
tion techniques, the SDR LNA achieves the highest FoM,
while the other parameters such as operating frequency
range, NF and conversion gain are all comparable with Fig. 17. Measured and simulated gain of the 60-GHz LNA.
state-of-the-art designs.

B. Measurement of the 60-GHz LNA

The 60-GHz LNA with the proposed wideband transformer-
feedback technique shown in Fig. 9(c) was fabricated in a
65-nm 1P6M LP CMOS process. The micrograph is shown
in Fig. 15, which indicates a core area of 0.7 × 0.38 mm2
excluding pads. The current consumed is 28 mA with supply
voltage at 1.2 V. As shown in Fig. 16, the S11 measures below
−10 dB from 49.5 to 67 GHz, exhibiting very wideband input
matching at mmW frequency. The voltage gain measures a Fig. 18. Measured and simulated NF of the 60-GHz LNA.
maximum value of 16.4 dB at 60 GHz, as shown in Fig. 17.
The discrepancies between the measurement and the simula- setup for NF measurement is illustrated in Fig. 19. In the
tion results are mainly attributed to the model inaccuracy from setup, a 60-GHz noise source (QNS-FB15LE) as well as a
the transistors, the passive components including transformers, downconverter composed of an LNA (Millitech LNA-15)
inductors and capacitors, and the layout parasitics. The testing and a linear mixer (Docommun FDB-15) whose LO port
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
WU et al.: DESIGN AND ANALYSIS OF CMOS LNAs WITH TRANSFORMER FEEDBACK
TABLE II
P ERFORMANCE S UMMARY AND C OMPARISON WITH 60-GH Z LNA S
Fig. 19. Testing setup for NF measurement of the 60-GHz LNA.
is driven by a signal generator (Agilent 8257D) were used
together with a spectrum analyzer (Agilent E4440A). Similar
to [34], three steps are required in the measurement. At first,
the noise source is directly connected to the downconverter
to calibrate out the gain and noise of the downconverter and
the spectrum analyzer. Next, the input and the output of the
LNA are connected to the noise source and the downconverter
by on-wafer probing, respectively, and then the NF is read
out from the spectrum analyzer. Finally, a through (THRU)
reference substrate is used to short the two probes such that
the loss due to the probes, cables and connectors are estimated.
Due to the symmetry of the setup, the estimated loss can be
used to de-embed the NF data measured in the second step
such that the NF of the 60-GHz LNA is obtained. As illustrated
in Fig. 18, the NF is 7.3 dB at 60 GHz and the minimum
value is 6.8 dB at 65 GHz. Due to the bandwidth limitation
of the noise source available, the NF below 60 GHz was not
measured. To characterize the linearity, the 1-dB compression
point (P1dB ) was measured. The maximum value is 3.8 dBm
while the minimum value is –2.5 dBm, corresponding to low-
gain and high-gain settings, respectively. At other frequencies,
the P1dB is up to ∼2-dB better due to the lower gain.
Table II summaries the performance of the 55–65-GHz
LNA. Comparing with recently published LNAs operating
at around 60 GHz, the LNA achieves comparable NF and
maximum conversion gain, state-of-the-art input matching and
overall FoM.
9
VII. C ONCLUSION
A new transformer-feedback technique featuring wideband
input matching was presented. Moreover, noise-cancellation
is enabled by constructing an auxiliary feedforward path to
simultaneously improve the gain and noise performance. With
the above two techniques, an LNA for SDR front-ends was
implemented, demonstrating state-of-the-art performance in
terms of input matching bandwidth, noise figure and FoMs.
Additionally, the proposed transformer-feedback technique is
further demonstrated by a 60-GHz LNA prototype, achiev-
ing good input matching over a 17.5-GHz frequency range
at 60 GHz.
R EFERENCES
[1] A. A. Abidi, “The path to the software-defined radio receiver,”
IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 954–966,
May 2007.
[2] Part 15.3: Wireless Medium Access Control (MAC) and Physi-
cal Layer (PHY) Specifications for High Rate Wireless Personal
Area Networks (WPANs) Amendment 2: Millimeter-Wave-Based Alter-
native Physical Layer Extension, IEEE Standard 802.15.3c-2009,
2009.
[3] F. Zhang and P. R. Kinget, “Low-power programmable gain CMOS
distributed LNA,” IEEE J. Solid-State Circuits, vol. 41, no. 6,
pp. 1333–1343, Jun. 2006.
[4] P. Heydari, “Design and analysis of a performance-optimized CMOS
UWB distributed LNA,” IEEE J. Solid-State Circuits, vol. 42, no. 9,
pp. 1892–1905, Sep. 2007.
[5] Y.-J. Wang and A. Hajimiri, “A compact low-noise weighted distributed
amplifier in CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC)
Dig. Tech. Papers, Feb. 2009, pp. 220–221.
[6] B. Razavi et al., “A UWB CMOS transceiver,” IEEE J. Solid-State
Circuits, vol. 40, no. 12, pp. 2555–2562, Dec. 2005.
[7] C.-F. Liao and S.-I. Liu, “A broadband noise-canceling CMOS LNA for
3.1–10.6-GHz UWB receivers,” IEEE J. Solid-State Circuits, vol. 42,
no. 2, pp. 329–339, Feb. 2007.
[8] J. Kim, S. Hoyos, and J. Silva-Martinez, “Wideband common-gate
CMOS LNA employing dual negative feedback with simultaneous noise,
gain, and bandwidth optimization,” IEEE Trans. Microw. Theory Techn.,
vol. 58, no. 9, pp. 2340–2351, Sep. 2010.
[9] R.-F. Ye, T.-S. Horng, and J.-M. Wu, “Two CMOS dual-feedback
common-gate low-noise amplifiers with wideband input and noise
matching,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 10,
pp. 3690–3699, Oct. 2013.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
10
[10] D. Im, I. Nam, J.-Y. Choi, B.-K. Kim, and K. Lee, “A CMOS active
feedback wideband single-to-differential LNA using inductive shunt-
peaking for saw-less SDR receivers,” in Proc. IEEE Asian Solid-State
Circuits Conf., Nov. 2010, pp. 1–4.
[11] J. Borremans, P. Wambacq, C. Soens, Y. Rolain, and M. Kuijk,
“Low-area active-feedback low-noise amplifier design in scaled digital
CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 11, pp. 2422–2433,
Nov. 2008.
[12] M. Parvizi, K. Allidina, and M. N. El-Gamal, “An ultra-low-power
wideband inductorless CMOS LNA with tunable active shunt-feedback,”
IEEE Trans. Microw. Theory Techn., vol. 64, no. 6, pp. 1843–1853,
Jun. 2016.
[13] P.-Y. Chang and S. S. H. Hsu, “A compact 0.1–14-GHz ultra-wideband
low-noise amplifier in 0.13-μm CMOS,” IEEE Trans. Microw. Theory
Techn., vol. 58, no. 10, pp. 2575–2581, Oct. 2010.
[14] B. G. Perumana, J.-H. C. Zhan, S. S. Taylor, B. R. Carlton, and
J. Laskar, “Resistive-feedback CMOS low-noise amplifiers for multiband
applications,” IEEE Trans. Microw. Theory Techn., vol. 56, no. 5,
pp. 1218–1225, May 2008.
[15] X. Wang, J. Sturm, N. Yan, X. Tan, and H. Min, “0.6–3-GHz wideband
receiver RF front-end with a feedforward noise and distortion cancel-
lation resistive-feedback LNA,” IEEE Trans. Microw. Theory Techn.,
vol. 60, no. 2, pp. 387–392, Feb. 2012.
[16] Q. Li and Y. P. Zhang, “A 1.5-V 2–9.6-GHz inductorless low-noise
amplifier in 0.13-μm CMOS,” IEEE Trans. Microw. Theory Techn.,
vol. 55, no. 10, pp. 2015–2023, Oct. 2007.
[17] C.-K. Luo, P. S. Gudem, and J. F. Buckwalter, “A 0.4–6-GHz 17-dBm
B1dB 36-dBm IIP3 channel-selecting low-noise amplifier for SAW-less
3G/4G FDD diversity receivers,” IEEE Trans. Microw. Theory Techn.,
vol. 64, no. 4, pp. 1110–1121, Apr. 2016.
[18] M. T. Reiha, J. R. Long, and J. J. Pekarik, “A 1.2 V reactive-
feedback 3.1–10.6 GHz ultrawideband low-noise amplifier in 0.13 μm
CMOS,” in Proc. IEEE Radio Freq. Circuits Symp., Jun. 2006,
pp. 1–4.
[19] S. Bagga, A. L. Mansano, W. A. Serdijn, J. R. Long,
K. Van Hartingsveldt, and K. Philips, “A frequency-selective broadband
low-noise amplifier with double-loop transformer feedback,” IEEE
Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 6, pp. 1883–1891,
Jun. 2014.
[20] Y. Yu, P. G. M. Baltus, A. De Graauw, E. van der Heijden, C. S. Vaucher,
and A. H. M. van Roermund, “A 60 GHz phase shifter integrated with
LNA and PA in 65 nm CMOS for phased array systems,” IEEE J. Solid-
State Circuits, vol. 45, no. 9, pp. 1697–1709, Sep. 2010.
[21] M. H. Tsai, S. S. H. Hsu, F. L. Hsueh, C. P. Jou, and T. J. Yeh, “Design
of 60-GHz low-noise amplifiers with low NF and robust ESD protection
in 65-nm CMOS,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 1,
pp. 553–561, Jan. 2013.
[22] T. Redant, T. Ayhan, N. De Clercq, M. Verhelst, P. Reynaert, and
W. Dehaene, “A 40nm CMOS receiver for 60GHz discrete-carrier
indoor localization achieving mm-precision at 4m range,” in IEEE
Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2014,
pp. 342–343.
[23] M. Vigilante and P. Reynaert, “A 68.1-to-96.4GHz variable-gain low-
noise amplifier in 28nm CMOS,” in IEEE Int. Solid-State Circuits
Conf. (ISSCC) Dig. Tech. Papers, Jan./Feb. 2016, pp. 360–362.
[24] P. Sakian, E. Janssen, A. H. M. van Roermund, and R. Mahmoudi,
“Analysis and design of a 60 GHz wideband voltage-voltage transformer
feedback LNA,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 3,
pp. 702–713, Mar. 2012.
[25] H. F. Leung and H. C. Luong, “A 1.2–6.6GHz LNA using trans-
former feedback for wideband input matching and noise cancellation in
0.13 μm CMOS,” in Proc. IEEE Radio Freq. Circuits Symp., Jun. 2012,
pp. 17–20.
[26] M. Khanpour, K. W. Tang, P. Garcia, and S. P. Voinigescu, “A wideband
W-band receiver front-end in 65-nm CMOS,” IEEE J. Solid-State
Circuits, vol. 43, no. 8, pp. 1717–1730, Aug. 2008.
[27] S. Shekhar, J. S. Walling, and D. J. Allstot, “Bandwidth extension
techniques for CMOS amplifiers,” IEEE J. Solid-State Circuits, vol. 41,
no. 11, pp. 2424–2439, Nov. 2006.
[28] A. Amer, E. Hegazi, and H. Ragai, “A low-power wideband CMOS LNA
for WiMAX,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 54,
no. 1, pp. 4–8, Jan. 2007.
[29] S. C. Blaakmeer, E. A. M. Klumperink, D. M. W. Leenaerts, and
B. Nauta, “Wideband balun-LNA with simultaneous output balancing,
noise-canceling and distortion-canceling,” IEEE J. Solid-State Circuits,
vol. 43, no. 6, pp. 1341–1350, Jun. 2008.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
[30] Y.-H. Yu, Y.-S. Yang, and Y.-J. E. Chen, “A compact wideband CMOS
low noise amplifier with gain flatness enhancement,” IEEE J. Solid-State
Circuits, vol. 45, no. 3, pp. 502–509, Mar. 2010.
[31] G. Sapone and G. Palmisano, “A 3–10-GHz low-power CMOS low-noise
amplifier for ultra-wideband communication,” IEEE Trans. Microw.
Theory Techn., vol. 59, no. 3, pp. 678–686, Mar. 2011.
[32] M. Moezzi and M. S. Bakhtiar, “Wideband LNA using active inductor
with multiple feed-forward noise reduction paths,” IEEE Trans. Microw.
Theory Techn., vol. 60, no. 4, pp. 1069–1078, Apr. 2012.
[33] X. Yu and N. M. Neihart, “Analysis and design of a reconfigurable
multimode low-noise amplifier utilizing a multitap transformer,” IEEE
Trans. Microw. Theory Techn., vol. 61, no. 3, pp. 1236–1246, Mar. 2013.
[34] S. Pellerano, Y. Palaskas, and K. Soumyanath, “A 64 GHz LNA with
15.5 dB gain and 6.5 dB NF in 90 nm CMOS,” IEEE J. Solid-State
Circuits, vol. 43, no. 7, pp. 1542–1552, Jul. 2008.
[35] N. Li et al., “A 24 dB gain 51–68 GHz CMOS low noise amplifier
using asymmetric-layout transistors,” in Proc. ESSCIRC, Sep. 2010,
pp. 342–345.
[36] D. Fritsche, G. Tretter, C. Carta, and F. Ellinger, “Millimeter-wave low-
noise amplifier design in 28-nm low-power digital CMOS,” IEEE Trans.
Microw. Theory Techn., vol. 63, no. 6, pp. 1910–1922, Jun. 2015.
[37] H.-C. Yeh, C.-C. Chiong, S. Aloui, and H. Wang, “Analysis and design
of millimeter-wave low-voltage CMOS cascode LNA with magnetic
coupled technique,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 12,
pp. 4066–4079, Dec. 2012.
Liang Wu received the B.S. and M.S. degrees
in materials science from Fudan University,
China, in 2004 and 2007 respectively, and the
Ph.D. degree in electronic and computer engineering
from the Hong Kong University of Science and
Technology, China, in 2012.
From March 2013, he was with the Department of
Electronic and Computer Engineering at the Hong
Kong University of Science and Technology as a
Research Assistant Professor. In December 2015,
he joined the State Key Laboratory of Millimeter
Waves (HK) at the City University of Hong Kong as a Senior Research
Fellow. His research interests include CMOS RF/millimeter-wave integrated
circuits, phased-array for 60 GHz wireless communications, and visible light
communication systems.
Hiu Fai Leung received the B.Eng. and
M.Sc. degrees in electronic and computer
engineering from the Hong Kong University of
Science and Technology, China, in 2009 and 2011,
respectively. From 2011 to 2013, he was with the
Hong Kong University of Science and Technology
as a Research Assistant, focusing on LNA and
wireless receiver designs. He is now with Kinetic
Technologies HK Limited, China, developing power
interface ICs for smartphone and SSD applications.
Howard Luong (F’14) received the B.S., M.S., and
Ph.D. degrees in electrical engineering and com-
puter sciences (EECS) from University of California
at Berkeley, CA, USA, in 1988, 1990, and 1994,
respectively. In September 1994, he joined the EEE
faculty at the Hong Kong University of Science
and Technology, China, where he is currently a
Professor.
His research interests are in analog, RF, and mm-
wave integrated circuits and systems for wireless
and portable applications. He is a coauthor of Low-
Voltage RF CMOS Frequency Synthesizers (Cambridge Univ. Press, 2004) and
Design of Low-Voltage CMOS Switched-Opamp Switched-Capacitor Systems
(Kluwer Academic Publishers, 2003).
Prof. Luong is currently serving as an IEEE Solid-State Circuits Society
Distinguished Lecturer, an Associate Editor for IEEE Virtual Journal on
RFIC and a Technical Program Committee Member of many conferences,
including Custom Integrated Circuits Conference (CICC), European Solid-
State Circuits Conference (ESSCIRC), and IEEE International Symposium
on Radio-Frequency Integration Technology (RFIT).