Exp-1: Adder_4bit

module halfadder(
input a,
input b,
output sum,
output carry
);
xor u1(sum,a,b);
and u2(carry,a,b);
endmodule

module fulladder(
input a,
input b,
input cin,
output sum,
output cout
);
wire n1,n2,n3;
halfadder u1(a,b,n1,n2);
halfadder u2(n1,cin,sum,n3);
or u3(cout,n2,n3);
endmodule

module adder_4bit(
input [3:0] a,
input [3:0] b,
output [3:0] sum,
output cout
);
wire c0,c1,c2;
halfadder u1(a[0],b[0],sum[0],c0);
fulladder u2(a[1],b[1],c0,sum[1],c1);
fulladder u3(a[2],b[2],c1,sum[2],c2);
fulladder u4(a[3],b[3],c2,sum[3],cout);
endmodule

Exp2:Mux_4to1_structural
module mux_4to1_structural(d0, d1,d2,d3, s1, s0, f);
input d1,d2,d3,d0;
input s1;
input s0;
output f;
wire n1,n2,n3,n4,n5,n6;
not u6(n5,s0);
not u7(n6,s1);
and u1(n1,s1,s0,d3);
and u2(n2,s1,n5,d2);
and u3(n3,s0,d1,n6);
and u4(n4,n5,n6,d0);
or u5(f,n1,n2,n3,n4);

endmodule

Exp2:Mux_4to1_behavioural
module mux_4to1_behavioural(in,sel,out);
input [3:0]in;
input [1:0]sel;
output reg out;
wire [3:0]in;
wire[1:0]sel;
always @ (in or sel)
begin
if(sel==0)
out=in[0];
else if (sel==1)
out=in[1];
else if (sel==2)
out=in[2];
else
out=in[3];
end
endmodule

Exp2:Mux_3to1_behavioural
module mux_3to1_behavioural(in,sel,out);
input [2:0]in;
input [1:0]sel;
output reg out;
wire [2:0]in;
wire[1:0]sel;
always @ (in or sel)
begin
if(sel==0)
out=in[0];
else if (sel==1)
out=in[1];
else if (sel==2)
out=in[2];
else
out=0;
end
endmodule

Exp3:Mod-12-up-down-counter
module mod12_up_down_counter(clk,rst,cnt,m);

input clk, rst,m;

output [3:0] cnt;

reg [3:0] cnt_s;

always @ (posedge(clk))

begin

if(rst)

cnt_s=0;

else if(m==0)

begin

if(cnt_s==4'b1011)

cnt_s=0;

else

cnt_s=cnt_s+1;

end

else

begin

if(cnt_s==0)
cnt_s=4'b1011;

else

cnt_s=cnt_s-1;

end

end

assign cnt=cnt_s;

endmodule

Exp4:FSMs (Moore)
module moore_fsm(clk,rst,x,z);

input clk,rst,x;

output z;

reg [1:0] st;

always @ (posedge(clk))

begin

if(rst)

st=0;

else

begin

case(st)

0:

begin

if(x)

st=1;
else

st=0;

end

1:

begin

if(x)

st=1;

else

st=2;

end

2:

begin

if(x)

st=3;

else

st=0;

end

3:

begin

if(x)

st=1;

else

st=2;

end

default:
st=0;

endcase

end

end

assign z=(st==3)?1:0;

endmodule

Exp4:FSMs (Mealey)
module meuly_fsm(clk,rst,x,z);

input clk,rst,x;

output z;

reg [1:0] state;

always @ (posedge(clk))

begin

if (rst)

state=0;

else

begin

case (state)

0:

begin

if(x)
state=1;

else

state=0;

end

1:

begin

if(x)

state=1;

else

state=2;

end

2:

state=0;

default:

state=0;

endcase

end

end

assign z=(state==2&&x==1)?1:0;

Endmodule