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ARINC 429 DATA CONCENTRATOR

C. PITOT C.C-VAUBOIS M. PROST L. POT

SEXTANT Avionique - B.P. 59 - 78140 Velizy-Villacoublay - FRANCE

Abstract - This paper presents the hardware Third : High level new functions were needed such
architectural concept of ARlNC 429 Data concentrators as :
which are used by SEXTANT Avionique Company for . ARlNC data timing control and message dating
both the A320 and A3401330 commercial transport
airplanes. in respect to these guidelines, a family of
. Multiword message management in fifo-like files.
inter-compatible clrcuits were designed in order to tit a Fourth : An implicit need was of course to lead to a
very wide ARlNC 429 application panel. Then, we good system safety from the failure mode analysis
present their features and the methodology used point of view.
during their design. Eiflh : The use of formerly designed circuits was
greatly expected in order to minimize the conception
1. INTRODUCTION work and non recurrent costs.
The AIRBUS A320 program introduced the "fly by Up lo 64 Arinc danels
wire" concept in commercial transport airplanes. Within
this plane, for flight management and guidance
systems integration, a communication problem had UDto 8 SR8A
risen, because of the great number of ARlNC 429 lines
which a computer had to listen to in order to perform its
function.
This constraint had led to the need for and the design
of very compact and powerful ARlNC 429 reception
units, all of them based on a common architecture
using extensively a gate-array-based Asic called
"SR8A".
This gate array was describted in a previous paper Control

presented at the specific Circuits Conception Address

Conference in GRENOBLE in 1988.
This circuit has the following properties :
- 8 channels cascadable up to 64.
- Automatic speed recognition and control.
- Programmable message selection and storage
address computation by means of an external
E*PROM array common to all the SR8As connected
on the same bus.
- Structured data array management in an external FIG. 1 A SRIA based typical architecture
ram common to all the SR8A connected on the same
bus.
- 8-bit micro interface with 32-bit word integrity 2. "CAMELIA" :
management through a 32-bit embedded cache A CIRCUIT FOR EXTENDED ADDRESS
register. MANAGEMENT
Since the A330-A340 program was launched, we
have been faced with a new problem, because a new The two main problems we had to overcome in order
generation ARlNC 429 Data Concentrator was to increase the number of channels in an SR8A based
needed. architecture, is the arbitration protocol which is limited
First : We had to provide more than 64 channels on a to eight circuits. This problem can be solved by using
single printed circuit board. two groups of up to eight SR8A connected to an add-
S e c o n d : For computation load reasons new on state machine performing the inter-group
generation 32-bit microprocessors were used and the arbitration. This solution allows up to 128 channels.
8-bit interface appeared to be inappropriate in this The second one is the 15-bit indexing address
respect. capability available in the standard SR8A architecture.

.OO (9 1990 IEEE

M0316-0/90/0000/0066/$01
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This capability was more than sufficient in our A320 Address Data
application, but was greatly limiting the upgrade to
more powerfull systems.
The solution to both these problems was founded in
the Camelia Concept, the letters C.A.M.E.L.I.A.
standing for "Adaptive Indexation Link for Extended
Memory Allocation Circuit". "A Algorlthm" (SDI Not decoded)
This circuit allows :
up to 128 ARlNC 429 channel concentration SWH I C h m d N r I XV 1 0 0 0 I UBEL
INDEX1 IO

up to 18 address bits for indexing management

2 indexing algorithm are available. S W H I C h a n l N r I XV I 0 0 I I UBEL
The A. algorithm specially designed to optimize the
E2PROM size when the number of channels is high
and the number of useful extended labels per channel
is small compared to 1024 (the maximum number of
extended labels possible on one channel).
The C algorithm is specially designed to minimize INDEX3 I Chu*INr I NOEX2 I WDEX I 1I
the E2PROM size when the number of channels is less
than 64 and the number of useful extended labels is
close to the maximum. "A Algorllhm" (SDI decoded)

GROUP A GROUP E
up to 8 SR8A up IO 8 SRBA
up lo 64 Arinc chanels up to 64 Arinc chanels

3. "ACACIA"
A CIRCUIT FOR EXTENDED FEATURES

- In fig. 2 the CAMELIA writes directly ARlNC Data in

As we can see in fig 2 the "CAMELIA is located from
a data transfer point of view between the "SR8A"
groups and the common memory. It strobes both the A
and B group buses, and performs arbitration between
the two groups.
From the close observation of the bus protocol
signals, the CAMELIA internally mirrors the machine
state of the active SR8A on which it synchronizes all its
specific actions.
- It manages its specific address bits during SR8As
indexation transfer phases.
- During first SR8A indexation, it performs a private
indexation in order to be able to extend to addressing
range.
- It returns modified index to the SR8A (see fig.3/4 A
algorithm).
a dedicated ram which is, through the Master SR8A
and CAMELIA, mapped into the microprocessors's
addressable range. Unfortunately the interface is 8 bits
wide in that case, which is a little bit time consuming in
very heavy applications and in some cases, can
compromise good data management by common bus
overloading.
- If a more efficient interface is needed associated
with new features a post processor can be added on
the common bus which leads to an architecture as
shown in fig 5.
In that architecture, the main micro interface is 16 or
32 bits depending on microprocessor and backplane
choice. An 8 bit interface toward SR8A may still remain
in order to achieve programming and self test features
but is not supposed to cause overhead acces on the
common bus in normal operation configuration. In this
configuration the common bus is dedicated to
indexation algorithm and transfer and has a granted
throughput of 500 000 ARlNC words per second which
is sufficient even for 128 high speed channels.
(The max throughput of an ARlNC channel is
2778 words per second which corresponds to one
word every 360 microseconds).

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The post processor observes very closely the GROUP A GROUP B

indexation and transfer cycles, interprets indexation
constants as an instruction and the data as an
operand. It manages to store the operand with respect
to the instruction and to a predefined Data array
structure.
On the other hand, it receives requests from the
microprocessor interface and answers as quickly as
possible with respect to data integrity.
The data transfer bus between post processor and
data array structure is 32 bits wide and is capable of a
5 million 32 bits access per second max throughput
which allows a quite sophisticated data array structure
management.
In appliance of that architectural concept, a
dedicated post processor named ACACIA has beed
designed.
The letters ACACIA are approximately standing for
ARlNC Information Chronology and Acquisition
Control post processor.
Its perfwmance can be roughly described though the
explanation of fig. 6. which shows the data array
format.
6 object types are manipulated. 5 are variable type :
- single word data
- fifo-like files for multi word data
- control word associated with single word
- control word associated with fifo words
- fifo descriptors
1 is of constant type :
- constraints.
A single word data is a 32-bit ARlNC word as
receivedthough the SR8A CAMELIA path. U
- A fifo-like file is a 15 word max sequence of ARlNC
words sharing the same label and channel processor FIG. 5 post processor architecture
and identified during indexation phases as a multi
word data.
- Control word associated with single word is a 16-bit . 4-bit writing pointer
variable formated as the concatenation of a 4 bits . 4-bit reading pointer
Hamming code key "HE" associated to the record and . 4-bit control field for test purposes
a 12 bits datation. . 4-bit fifo threshold N which is the number of words
- Control word associated to fifo-words is a 32 bits stacked inside the fifo for which an interrupt is sent to
word formated as the concatenation of : the processor.
. a 4-bit "HE" Hamming code key as above. . 4 bits HL Hamming code which is a Hamming code
. a 12-bit datation. key associated with the ARlNC label (adequation of
. a 4-bit "HL" Hamming code associated with the label and HL is checked before writing the word in
label. data array structure).
. a 12-bit dating associated with the preceding word . a global date previously mentioned which is the
inside the fifo. dating of the last word entered inside the fifo.
Both control words are used during the restitution on Constraints are constant type 16-bit words which are
microprocessor request in order to perform : formated as the concatenation of :
- Controls on internal coherence based on "HE" - a 4-bit HL Hamming code key and a 12-bit
Hamming code. refreshment constraint which is the maximum allowed
- Controls on data refreshment based on : time between two consecutive words in the same ram
. recorded dating versus actual time in respect to location or in the same fifo.
refreshment constraints for single word records. This contraint is checked during the restitution of the
. Recorded dating versus preceaing wuiu U ~ L I I I Y corresponding word on a microprocessor request.
respect to refreshment constraints for multiple word A special background task is performed with a
files. frequency equal to the half time coding dynamic in
. Global dating versus actual time in respect to order to prevent time coding ambiguity due to time
refreshment constraints for empty fifos. folding. When such an ambiguity is about to be
Fifo descriptors are 32-bit variables associated with possible a special alteration of the corresponding
one of each of 256 manageable fifo-like files and are record's HE Hamming code is performed which allows
formated as the concatenation of : a later warning to the microprocessor.

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HE I Datalion I HL IPrecedm! Word Date

/ HE I Datatlon I HL [Precedent Word Dale
I I 1

I
Control
I
HE I Datation 1 Hi ]Precedent Word Dale
ECR ILECllCTRLI N I HL I Global Dale RAM )

I 1
\N_, I same

Slandard
Conlrol Arinc Word
Space Control Space
12K Word

I HE I Datamn I HL I
L.
Refresh
- - - - - I
I

Slandard
Amc Word as Received I
Data Arinc Word
Space Space
12K Word
Aiinc Word a5 Rece(ved
A m c Word as Received

Fit0 Space
Up lo 256
15 Word Fit0

32 Bit RAM -
16 Bit ROM

FIG. 6 Data array format FIG.7 RamlRom superposition

and control bits, associated with the fact that

4. FAILURE MODE ANALYSIS datdcontrol word addresses are obtained one from the
other by all address bit inversion.
The first control performed on the ACACIA'S
CAMELIA side is to check the coherence of 5. FIFO MANAGEMENT
instructions and data. This check is based on :
- Data panty The most sophisticated function performed by the
- Address label parity ACACIA circuit is the management of up to 256 fifo-like
- Address format coherence. data files inside the ram, each of them associated with
- During the storing phase, the ACACIA checks the a mirror control space, containing the fifo status
acceptability of ram modification versus HL constraint descriptor.
and calculates the HE key associated with the record it Each fifo has a unique address from a storing and
performs. reading point of view. This address is named as the fifo
- During the restitution phase, it controls the internal base, in respect to which the 4-bit writing and reading
coherence of records and its status versus HE, word pointers must be considered as offsets.
parity and refreshment constraint. In case of any When the size of a fifo's content reach a
problem, a non-ambiguous error word is sent to the preprogramed threshold, an interrupt is sent to the
microprocessor. microprocessor, and the fifo number is pushed inside
- All these controls associated with the data array an interrupt fifo in order to permit interrupt stacking up
format make the probability of a non detected failure in to 16 levels. This fifo is mapped inside a register file
the data structure integrity very unlikely to happen internal to the ACACIA.
because such an event requires two or more distinct Fifo's exception status as overflow causes also an
devices simultaneously and compatible failure. interrupt associated with a special format interrupt
Undetected common cause failure by addresddata vector.
bit sticking or short circuit are made very unprobable The same remark can be made for error detection
because of scattering in the 32-bit data field of record during instruction acquisition and data storage.

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6. CONCLUSION

Such an architecture has been successfully

implemented on a single printed board gathering :
- 9 SR8A allowing 72 channels concentration
- 1 CAMELIA,
- 1 ACACIA;
18 ceramic macromodules for ARlNC demodulation
and protections.
EPLD's and transceiver for Address decoding and
micro interface management.
4 x 32 K 8-bit Ram
4 x 32 k 8-bit E2PROM
Special system oriented test features allow a CPU
initiated test to be performed during the power-on
check sequence with very efficient controllability
observability path. Especially incoherent data structure
or inacceptable instructions can be initiated to check
the ACACIA'S ability to react properly in such
exceptional cases.
SR8A is a 4000-gate 2p MHS Gate array including a
72 X 8-bit compiled ram.
CAMELIA is a 2700-gate 2p MHS Gate Array.
ACACIA is a 9000-gate equivalent 1,5p V L S I
Technology Inc Sea of gate.
The last two ones were designed in a Mentor
Graphic environment using a hardware modelizer on
which a SR8A first, then a CAMELIA were plugged in
order to allow complex interaction simulation and
system level validation.
Such a methodology was possible because of the
pre-existence of the SR8A during the CAMELIA's
design and of the CAMELIA during the ACACIA'S
design.
These conditions seem to be very infrequent as well
as incompatible with planning constraints in the case
of an "ex nihilo" system design. But in our case, we
took benefit from an existing family of circuits
associated with an important ARlNC System design
background which allows us to focus on architecture
problems and design proof demonstration and finally
led to a first good silicon multi asic system design.

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