400 Chapter 6 Introduction to Digital Electronics

input voltage continues to increase, the output voltage decreases rapidly and ultimately reaches
the design value of 0.25 V for an input of 5.0 V.

6.9.3 Noise Margins for the Inverter with

Depletion-Mode Load
The approach to finding the noise margins for the depletion load inverter is similar to that used
for the other NMOS inverters. Again, remember that we are interested in the points in the transfer
function at which the slope is −1, and only the results are presented here. The detailed calculations
for VI L , VO H , VI H , and VO L can be found on the MCD website.


KR √ √

VO H = VD D + VT N L 1 − with VT N L = VT O + γ VO H + 2φ F − 2φ F
1 + KR
(6.32)
VT N L
VI L = VT N S − 2
KR + KR
In these expressions, K R = (W/L) S /(W/L) L . The results in Eqs. (6.32) assume that transistor
M S is saturated and that M L is in the triode region.
−VT N L 

VO L = √ with VT N L = VT O + γ VO L + 2φ F − 2φ F
3K R
(6.33)
2VT N L
VI H = VT N S −√
3K R
The results in Eqs. (6.33) assume that transistor M L is saturated and that M S is in the triode region.

Finding VO H and VI L

The relations for VO H and VO L can each be rearranged into a quadratic equation just as was done
in order to find VH for the saturated load inverter. For the 5-V depletion-mode inverter design, we
have K R = 2.06(2.15) = 4.43. Equation set (6.32) becomes
 √
VT N L
VO H = 5 + 0.1VT N L VT N L = −3 + 0.5 VO H + 0.6 − 0.6 VI L = VT N S −
4.90
Solving for VO H , we get this quadratic equation

VO2 H − 9.327VO H + 21.73 = 0

and the solution is VO H = 4.78 V, VT N L = −2.23 V, and VI L = 1.46 V. The second root,
VO H = 4.53 V, does not provide a consistent solution to the original two equations.
As always, the operating region assumptions of the transistors should be checked. For VO H =
4.78 V, the values of v DS for M S and M L are 4.78 V and 0.22 V, respectively. For, M S , vG S −VT N S =
1.46−1 = 0.46 V and v DS = 4.78 V. In this case, v DS > (vG S − VT N S ), so M S is saturated. ✔ For,
M L , vG S − VT N L = 0 − (−2.23) = 2.23 V and v DS = 0.22 V. In this case, v DS < (vG S − VT N S ),
so M L operates in the triode region. ✔ Both regions are consistent with the assumptions used to
develop the noise margin equations.

Finding VO L and VI H

Similarly, Eqs. (6.33) become

−VT N L  √
2VT N L
VO L = VT N L = −3 + 0.5 VO L + 0.6 − 0.6 VI H = VT N S −
3.65 3.65
 6.9 NMOS Inverter with a Depletion-Mode Load 401

Solving for VO L , we have

VO2 L − 1.877VO H + 0.852 = 0

for which the solution is VO L = 0.769 V, VT N L = −2.80 V, and VI H = 2.53 V. Again, the second
root, VO L = 1.108 V, does not satisfy the two original equations.
Again, the operating region assumptions of the transistors should be checked. For VO L =
0.79 V, the values of v DS for M S and M L are 0.79 V and 4.21 V, respectively. For, M S , vG S − VT N S =
2.53 − 1 = 1.53 V and v DS = 0.79 V. In this case, v DS < (vG S − VT N S ), so M S operates in the
triode region. ✔ For M L , vG S − VT N L = 0 − (−2.80) = 2.80 V and v DS = 4.21 V. In this case,
v DS > (vG S − VT N S ), so M L is saturated. ✔ Both regions are consistent with the assumptions
used to develop the noise margin equations.

NM L and NM H

Now, the noise margins can be calculated for the design in Fig. 6.29, using the results just derived:

NM L = VI L − VO L = 1.46 − 0.77 = 0.69 V

NM H = VO H − VI H = 4.78 − 2.53 = 2.25 V

Note that the values of calculations for VI L , VO H , VI H , VO L , and the noise margins agree with
the simulation results in Fig. 6.30.
Because of its overall advantages, the inverter with the depletion-mode load device became
the most widely used form of NMOS logic, so let us explore the noise margins for this circuit
in more detail. Figure 6.31 depicts the results of calculations of the noise margins versus the
parameter K R for the inverter with a depletion-mode load. As K R increases, NM H monotonically
increases, whereas NM L decreases quickly reaching an almost constant value for K R > 3. The
values in the graph agree well with the hand calculations for our inverter design with K R = 4.43.
Note that NM H becomes negative for values of K R less than approximately 0.9, and the circuit
will no longer function properly as a logic inverter.

3
NMH
Noise margin (volts)

1 NML

–1
0 2 4 6 8 10 12
KR

Figure 6.31 Noise margins versus K R = K S /K L for the NMOS inverter with a depletion-mode load.
VD D = 5 V, VT O S = 0.75 V, VT O L = −3 V, γ = 0.5 V0.5 , and 2φ F = 0.6 V.