MULTI-SUPPLY VOLTAGE

Prof. Kaushik Roy

@ Purdue Univ.
 Multi-Supply Voltage: Basic Idea

•Use higher supply in the critical sections of logic

•Lower supply voltage in the non-critical sections

•Might need level converters to communicate between

different voltage levels

•Major improvement in dynamic power due to lower

supply voltage blocks

Prof. Kaushik Roy

@ Purdue Univ.
 Example: Multi-Voltage Scheduling

Clock
0
1 A1 A4 A1 M4 A1

Bottlenecks for single 2 A2 A2 A2

A3 A3 A3
Vdd, VT, Clock 3
4
Non-Uniform Clock Number of
Path Length Period Control Steps

source Clock Resources

Cycle (1+,2*)
y(n-1) x(n)

Schedule to exploit -a1

[1]

-a2
y(n-2)
b0
0

1
*
4V
*
3V

slack 2
*
3 4V
+
4 4V
+
y(n)
5 4V
sink
Source: Intel [-max latency] max latency=5

Prof. Kaushik Roy

@ Purdue Univ.
 Multi-Voltage IC Design Issues

high VDD high VDD

Level Conversions

OUT OUT
low VDD
IN

DC-DC Efficiency
• need efficiency of at least
to break even VHI2
2
Layout: VLO
• separate power and ground routing
• substrate contacts between voltage regions

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.
 Multi-Voltage Results

• Summary of results:
– up to 50% energy savings 1 vs. 2 voltages
– less than 15% additional savings 2 vs. 3
– area penalties vary from 0 up to 170%

Source: Intel

Prof. Kaushik Roy

@ Purdue Univ.