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V.M. Brea
PhD Course
2005-2007
Dept. of Electronics and Computer Science
University of Santiago de Compostela
Santiago de Compostela
Spain
Outline
Introduction
Mismatch- definition
Mismatch- models
Pelgrom Model
Final Remarks
Introduction (I)
1.- Chip Power 1.- Vdd 1.- Tox, Lg, xj, Rs 1.- Thermal
2.- Chip Speed 2.- MOSFET Lea 2.- Channel Processing
3.- Functional Kage Engineering 2.- Overall
Density 3.- MOSFET Drive 3.- Oxynitride or Process Flow
4.- Chip Cost Current High K Gates 3.- Process
5.- Architecture 4.- Parasitic Series 4.- Classical Planar Modules
Etc. Resistance Or Non-Classical 4.- Material
5.- Transistor Size CMOS Structures Properties
6.- Vt Control Etc. 5.- Boron
7.- Reliability Penetration
Introduction (V)
Top-down Design Flow of an ASIC
Natural Language Specific Software
-Description of the -Toos suited to the Hard
application ware Model or Architec
-Initial Specifications ture
Computing Software
Stage
Hardware-Level
-High-level Language
Design
C, C++, Matlab …
-Additional Constraints
Introduction (VI)
Circuit-based
Few parameters (2-3)
Many parameters (5-7)
Many of them correlated, difficult to use in
hand-analysis
Device-based
Many parameters, more precise, not usable
in hand-analysis, only in computer
simulations
Mismatch Models (II)
Circuit-based
Pelgrom and extensions- 3 parameters
Lovett- narrow devices show more mismatch
Seville- 5 parameters
Drennan- Motorola, 7 parameters
⎝ β ⎠ WL
Pelgrom Model (II)
Goal- to have expressions for rapid hand-analysis and trade-offs
evaluation
Assumptions 2
A
Closely spaced devices
S D <<
2 2
WL
In today technologies, for the two former parameters to be
comparable, D should be around 1mm. The above assumption is
reasonable
VBS = 0 ⇒ σ (∆γ ) = 0
No substrate effect. If there is any, an extra mismatch degradation
term must be added
Pelgrom Model (III)
Remark- For independent and normally distributed deviations in x
and y, the standard deviation of a function Z=f(x,y) is:
2
⎛ ∂f ⎞ 2 ⎛ ∂f ⎞ 2
2
σ (Z ) = ⎜ ⎟ σ ( x ) + ⎜⎜ ⎟⎟ σ ( y )
2
⎝ ∂x ⎠ ⎝ ∂y ⎠
Then for two functions Z (one subtracting from the other), we can
write:
∂f ∂f
∆Z = Z1 − Z 2 = ∆x + ∆y
∂x ∂y
2
⎛ ∂f ⎞ 2 ⎛ ∂f ⎞ 2
2
⎝ ∂x ⎠ ⎝ ∂y ⎠
σ (∆Z ) = 2σ (Z )
Pelgrom Model (IV)
Across-regions equations (square-law):
⎛ σ (∆I DS ) ⎞ ⎛ σ (∆β ) ⎞ ⎛ g m ⎞ 2
2 2 2
⎜⎜ ⎟⎟ = ⎜⎜ ⎟⎟ + ⎜ ⎟ σ (∆VT )
⎝ I DS ⎠ ⎝ β ⎠ ⎝ I ⎠
⎛ σ (∆β ) ⎞
2
σ (∆VGS ) = σ (∆VT 0 ) +
1
2 2
⎜
2 ⎜
⎟⎟
(g m / I ) ⎝ β ⎠
Pelgrom Model (V)
Mismatch in strong inversion:
⎛ σ (∆I DS ) ⎞ ⎛ σ (β ) ⎞ 4σ (VT 0 )
2 2 2
⎜⎜ ⎟⎟ = ⎜⎜ ⎟⎟ +
β ⎠ (VGS − VT )
2
⎝ I DS ⎠ ⎝
(VGS − VT ) ⎛ σ (β ) ⎞
2 2
σ (∆VGS ) = σ (VT 0 ) +
2 2
⎜⎜ ⎟⎟
4 ⎝ β ⎠
Pelgrom Model (VI)
The former equations can be approximated
(see table I and plot) by:
⎛ σ (∆I DS ) ⎞ 4σ 2 (VT 0 )
2
2
4 AVT
⎜⎜ ⎟⎟ ≈ = 0
⎝ I DS ⎠ (V GS − V T ) 2
WL (V GS − VT )2
2
σ 2 (∆VGS ) ≈ VT 0
A
WL
Pelgrom Model (VII)
Table I
Pelgrom Model (VIII)
Pelgrom Model (IX)
Mismatch on the design of elementary
stages- Current Mirror (I)
Design- trade-off
Three parameters- area, speed and power
gm1 3I B
BW = =
2π (CGS 1 + CGS 2 ) 2π ( A + 1)(VGS − VT )CoxWL
P = ( A + 1)I BVDD
I inRMS
Accrel =
3σ (I os )
Pelgrom Model (X)
Mismatch on the design of elementary
stages- Current Mirror (II)
We define the performance equation (PE):
2
Speed . Accuracy 2 BWAccrel
PE = =
Power P
To calculate the errors in Ios (Accrel), we first go through the
errors in the currents of M1 and M2 (current mirror transistors, in
and out, respectively). For M1, we can write:
σ (IUNIT ) =
1 2 AVT 0
IB
2 (VGS − VT ) WL
Pelgrom Model (XI)
Mismatch on the design of elementary
stages- Current Mirror (III)
For the standard deviation of the current of M2, we formulate:
σ (I OUT ) = Aσ (IUNIT )
And as the standard deviation is referred to the input current, the
standard deviation of the input offset current is as follows:
σ 2 (I OUT )
σ (I OS ) = + σ 2 (IUNIT ) =
A2
2 AVT 0 A +1
IB
(VGS − VT ) WL A
Pelgrom Model (XII)
Mismatch on the design of elementary
stages- Current Mirror (IV)
With this, and assuming a typical bias modulation index of ½,
Accrel and PE become:
WL (VGS − VT ) A
Accrel =
12 AVT 0 A +1
PE =
2
BWAccrel
=
(VGS − VT ) A
P 96πCox AVT
2
V
0 DD ( A + 1)3
Gain 2 BWAccrel
2
=
(VGS − VT )
P 96πCox AVT
2
0VDD
Pelgrom Model (XIII)
Mismatch on the design of elementary
stages- Current Mirror (V)
Conclusions
The best total performance comes with large (VGS-VT) values. Concern-
(VGS-VT) usually upper bounded by Vdd/2
R2 ⎛ 1 − 1 / (gmR2 ) ⎞
A(s ) =
Vout
= − ⎜⎜ ⎟⎟
Vin R1 ⎝ 1 + 1 / ( gmR1 ) + s / (gm / CGS ) ⎠
R2 ⎛ ⎞
A(s ) ≈ − ⎜⎜
1
⎟⎟
R1 ⎝ 1 + s / ( gm / CGS ) ⎠
BW ≈ gm / (2πCGS )
3I B
BW =
2π (VGS − VT )WLCox
Pelgrom Model (XV)
Mismatch on the design of elementary
stages- One Transistor Voltage Ampl. (II)
For the power dissipation and the relative accuracy the next
equations hold:
P = VDD I B
VinRMS VDD WL
Accrel = =
3σ (VOS ) 6 2 AVT 0Gain
Combining the three former equations we achieve:
Gain 2 BWAccrel
2
VDD
=
P 24π (VGS − VT )AVT 0Cox
2
Pelgrom Model (XVI)
Mismatch on the design of elementary
stages- Differential Pair Voltage Ampl. (I)
Similarly to the One Transistor Voltage amplifier, the next equations hold:
BW = gm / (2πCGS )
P = 2VDD I
VDD WL
Accrel =
6 2 AVT 0Gain
Gain 2 BWAccrel
2
VDD
=
P 96π (VGS − VT )AVT
2
0Cox
gm2 3I B
f2 = =
2π (CGS 2 a + CGS 2b ) 4πCoxW2 L2 (VGS − VT )2
GBW must be made Kstab times smaller than the second pole in
order to ensure stability with feedback configurations, thus:
f2 3I B
GBW = =
K stab 4πK stabCoxW2 L2 (VGS − VT )2
Pelgrom Model (XVIII)
Mismatch on the design of elementary
stages- Load Compensated OTA (II)
⎛ σ (VT 02 ) ⎞
2
σ 2 (VOS ) = σ 2 (VT 01 ) + ⎜⎜ ⎟⎟ =
⎝ Ain ⎠
( )
2 2
AVT A 1
+ = 0 n + AVT 0 p
0n VT 0p 2 2
2 2
AVT
W1 L1 W2 L2 Ain W2 L2 Ain
g m1 (VGS − VT )2 W1
Ain = = =
g m 2 (VGS − VT )1 W2
Pelgrom Model (XIX)
Mismatch on the design of elementary
stages- Load Compensated OTA (III)
Now, with the power dissipation, we have an expression for the
total performance of the OTA:
P = 2 I BVDD
Gain 2GBWAccrel
2
VDD ⎛ Ain ⎞
= ⎜ ⎟
P (
192πK stab Cox AVT
2
0n + A 2
VT 0 p ) .⎜ ⎟
⎝ (VGS − VT )1 ⎠
Gain 3 BWAccrel
2
VDD ⎛ Ain ⎞
PE = = ⎜ ⎟
P 192πK stabCox AVT
2
(0 n + AVT 0 p
2
) .⎜
⎝ (VGS − VT ) ⎟
1⎠
Pelgrom Model (XX)
Mismatch on the design of elementary
stages- Load Compensated OTA (IV)
Conclusions
Total performance (PE) depends on technology
constants and on the chosen bias point
The best total performance comes with low (VGS-
VT) values in the transistors operating in voltage
mode (the differential pair), and with large (VGS-
VT) values in the current mirror
Stability brings in more constraints leading to
higher power dissipation values
Pelgrom Model (XXI)
Mismatch on the design of elementary
stages- Feedback syst. & OTA Design (I)
Goal- to find PE for a general OA with feedback
g mIN
GBW = ACL BWCL =
2πCd
2I B
P = I BVDD , = g mIN
(VGS − VT )
P = πACL BWCL CdVDD (VGS − VT )
With Cd being the capacitor associated with the dominant pole of the
open-loop transfer function of the OTA and gmin being the
transconductance of the input stage
Pelgrom Model (XXII)
Mismatch on the design of elementary
stages- Feedback syst. & OTA Design (II)
2
V C
Acc 2
rel = 2
DD in
2
48 A C ACL ox VT 0
P = 48π
(VGS − VT )
C 2
A 3 ⎛ Cd ⎞
A BWCL Acc ⎜⎜
2
⎟⎟
ox VT 0 CL rel
VDD ⎝ Cin ⎠
Pelgrom Model (XXIII)
Mismatch on the design of elementary
stages- Feedback sys. & OTA Design (III)
Conclusions
The minimal power consumption is limited by the
technology, i.e. effect of mismatch. Likewise, PE is mainly
limited by the input transistor
To optimize PE in a voltage processing system, the input
stages have to be biased with low (VGS-VT) values; even in
weak inversion
Differently from open loop stages, in which the power
consupmtion is proportional to the square of the Gain, now
there is a cubic dependence on the Gain. This is caused by
another constraint in a feedback system, that is, the stability
requirements
Pelgrom Model (XXIV)
Mismatch on the design of elementary
stages- Gen. multi-stage volt. design (I)
⎛ σ (VOS 2 ) ⎞ ⎛ σ (VOS 3 ) ⎞
2 2
σ (VOSeq ) = σ (VOS1 ) + ⎜⎜
2
⎟⎟ + ⎜⎜ ⎟⎟ + ...
⎝ A1 ⎠ ⎝ A1 A2 ⎠
Conclusions
kT
V 2
=
nRMS
C
P = 8kTfDR 2
Auto-zero
Chopping
Trimming
Pelgrom Model (XXXIII)
Scaling (I)