VLSI Testing

Fault
F lt Simulation
Si l ti

Virendra Singh
I di Institute
Indian I tit t off Science
S i
Bangalore
virendra@computer.org

E0 286: Test & Verification of SoC Design

Lecture - 7
Jan 27, 2010 E0-286@SERC 1
 Fault Simulation

Jan 27, 2010 E0-286@SERC 2

 Simulation Defined
„ Definition: Simulation refers to modeling of a
design, its function and performance.
„ A software simulator is a computer program;
an emulator is a hardware simulator.
„ Simulation is used for design verification:
„ Validate assumptions
„ Verify logic
„ Verify performance (timing)
„ Types of simulation:
„ Logic or switch level
„ Timing
„ Circuit
„ Fault

Jan 27, 2010 E0-286@SERC 3

 Simulation for Verification

Specification

Synthesis

Response Design Design

analysis
y changes
g ((netlist))

Computed True-value
Input stimuli
responses simulation

Jan 27, 2010 E0-286@SERC 4

 Modeling Levels
Modeling Circuit Signal Timing Application
level description values
Architectural
Function, Programming 0, 1 Clock and functional
behavior, RTL language-like HDL boundary verification

Logic Connectivity of 0, 1,
0 1 X Zero delay
Zero-delay Logic
Boolean gates, unit-delay, verification
and Z multiple-
flip-flops and and test
transistors delay

S it h
Switch Transistor size 0, 1
0 Zero-delay Logic
and connectivity, and X verification
node capacitances

Timing gy Analog
Transistor technology g Fine-grain
g Timingg
data, connectivity, voltage timing verification
node capacitances
Circuit Continuous Digital timing
Tech. Data, active/ Analog
time and analog g
passive component voltage
voltage,
circuit
connectivity current
verification
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 True-Value Simulation
Al
Algorithms
ith
™ Compiled-code
p simulation
¾ Applicable to zero-delay combinational logic
¾ Also used for cycle-accurate synchronous sequential
g verification
circuits for logic
¾ Efficient for highly active circuits, but inefficient for
low-activity circuits
¾ High-level (e.g., C language) models can be used
™ Event-driven simulation
¾ Only gates or modules with input events are
evaluated (event means a signalg change
g )
¾ Delays can be accurately simulated for timing
verification
¾ Efficient for low-activity circuits
¾ Can be extended for fault simulation
Jan 27, 2010 E0-286@SERC 6
 Compiled-Code Algorithm

™ Step 1: Levelize combinational logic and

encode in a compilable programming language
™ Stepp 2: Initialize internal state variables ((flip-
p
flops)
™ Step 3: For each input vector
S t primary
Set i iinputt variables
i bl
Repeat (until steady-state or max. iterations)
¾ Execute compiled code
Report or save computed variables

Jan 27, 2010 E0-286@SERC 7

 Event-Driven Algorithm
Scheduled Activity
events list
a =1 e =1 t=0 c=0 d, e
c =1 0 2
1
g =1
2
2 2 d = 1, e = 0 f, g
d=0

ack
3
4 f =0
0

Time sta
b =1 4 g=0

T
g 6 f=1 g
0 4 8
Time, t 7

8 g=1
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 Time Wheel (Circular Stack)

Current max
time t=0
pointer Event link-list
1
2

4
5
6
7

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 Efficiency of Event-
driven Simulator
Simulates events (value changes) only
Speed up over compiled-code can be ten
times or more; in large
g logic
g circuits about
0.1 to 10% gates become active for an input
change

Steady 0
Steady 0 Large logic
block without
(
(no event)
t)
0 to 1 event activity

Jan 27, 2010 E0-286@SERC 10

 Problem and Motivation
Fault simulation Problem: Given
¾ A circuit
¾ A sequence of test vectors
¾ A fault model
Determine
¾ Fault coverage - fraction (or percentage) of
modeled faults detected by y test vectors
¾ Set of undetected faults
Motivation
¾ Determine test quality and in turn product quality
¾ Find undetected fault targets to improve tests

Jan 27, 2010 E0-286@SERC 11

 Fault simulator in a VLSI
Design Process
Verified design Verification
netlist input stimuli

Fault simulator Test vectors

Modeled Remove Test Delete

fa lt list ttested
fault t d faults
f lt compactor vectors

Fault Low Test

coverage generator Add vectors
?
Adequate
q
Stop
Jan 27, 2010 E0-286@SERC 12
 Fault Simulation Scenario
Circuit model: mixed-level
™ Mostly logic with some switch-level
switch level for high-
high
impedance (Z) and bidirectional signals
™ High-level models (memory, etc.) with pin faults

Si
Signal
l states:
t t llogic
i
™ Two (0, 1) or three (0, 1, X) states for purely
Boolean logic circuits
™ Four states (0, 1, X, Z) for sequential MOS circuits

Timing
™ Zero-delay
Zero delay for combinational and synchronous
circuits
™ Mostly unit-delay for circuits with feedback

Jan 27, 2010 E0-286@SERC 13

 Fault Simulation Scenario

Faults
™ Mostly single stuck-at faults
™ Sometimes stuck-open, transition, and path-delay
faults; analog circuit fault simulators are not yet in
common use
™ Equivalence fault collapsing of single stuck-at
faults
™ Fault-dropping -- a fault once detected is dropped
from consideration as more vectors are simulated;
fault-dropping
fault dropping may be suppressed for diagnosis
™ Fault sampling -- a random sample of faults is
simulated when the circuit is large

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 Fault Simulation Algorithms
™ Serial

™ Parallel

™ Deductive

™ Concurrent

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 Serial Algorithm
Algorithm: Simulate fault-free circuit and save
responses.
responses Repeat following steps for each
fault in the fault list:
™ Modify netlist by injecting one fault
™ Simulate modified netlist, vector by vector,
comparing responses with saved responses
™ If response differs, report fault detection and
suspend simulation of remaining vectors
Advantages:
™ Easy to implement; needs only a true-value
simulator, less memory
™ Most faults, including analog faults, can be
simulated

Jan 27, 2010 E0-286@SERC 16

 Serial Algorithm
¾ Disadvantage: Much repeated computation;
CPU time prohibitive for VLSI circuits
¾ Alternative: Simulate many faults together

Test vectors Fault-free circuit Comparator f1 detected?

Circuit with fault f1

Comparator f2 detected?
Circuit with fault f2

Comparator fn detected?
Circuit with fault fn

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 Parallel Fault Simulation
™ Compiled-code method; best with two-
states (0,1)
(0 1)
™ Exploits inherent bit-parallelism of logic
operations on computer words
™ Storage: one word per line for two-state
simulation
™ Multi-pass
p simulation: Each pass
p simulates
w-1 new faults, where w is the machine
word length
™ Speed up over serial method ~ w-1
™ Not suitable for circuits with timing-critical
and non-Boolean logic

Jan 27, 2010 E0-286@SERC 18

 Parallel Fault Simulation
Bit 0: fault-free circuit
Bit 1: circuit with c s-a-0
Bit 2: circuit with f s-a-1

1 1 1
c s-a-0 detected
a 1 0 1
1 1 1 1 0 1
b e 1 0 1
c s-a-0
g
0 0 0

d f s-a-1 0 0 1

Jan 27, 2010 E0-286@SERC 19

 Deductive Fault Simulation
™ One-pass simulation
™ Each line k contains a list Lk of faults
detectable on k
™ Following true-value simulation of each
vector,
t fault
f lt lists
li t off all
ll gate
t output
t t li
lines
are updated using set-theoretic rules,
signal values, and gate input fault lists
™ PO fault lists provide detection data
™ Limitations:
„ Set theoretic rules difficult to derive for non
Set-theoretic non-
Boolean gates
„ Gate delays are difficult to use

Jan 27, 2010 E0-286@SERC 20

 Deductive Fault Simulation

Notation: Lk is fault list for line k

kn is s-a-n fault on line k

1 {a0} Le = La U Lc U {e0}
a = {a0 , b0 , c0 , e0}

1 {b0 , c0}
b e 1
{b0} c 1
g
d f 0
Lg = (Le Lf ) U {g0}
U
{b0 , d0}
{b0 , d0 , f1} = {a0 , c0 , e0 , g0}
Faults detected by
the input vector

Jan 27, 2010 E0-286@SERC 21

 Concurrent Fault Simulation
™ Event-driven simulation of fault-free circuit and
only those parts of the faulty circuit that differ in
signal states from the fault-free
fault free circuit.
circuit
™ A list per gate containing copies of the gate from
all faulty circuits in which this gate differs. List
element contains fault
f ID, gate input and output
values and internal states, if any.
™ All events of fault-free and all faulty y circuits are
implicitly simulated.
™ Faults can be simulated in any modeling style or
detail supported in true
true-value
value simulation (offers
most flexibility.)
™ Faster than other methods, but uses most
memory
memory.
Jan 27, 2010 E0-286@SERC 22
 Conc. Fault Simulation
a0 b0 c0 e0
0 1 1 1
0 0 0 0
1 0 0 1
1
a 1 1
1 1
b 1 e 1
c 1
1 g
0
0

d
1 0
f a0 b c0 e0
0 0 0 0 0
0 1 0 0
0 1 0 0

1 1 1
0 1 1
b0 d0 f1 0
g 1 1
d0
0 1
f1
0 1 1 1
0
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 Thank You

Jan 27, 2010 E0-286@SERC 24