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ECE-2003
L55+L56
DIGITAL LOGIC DESIGN
ADARSH RAJ
16BEC0075
1) Construction of 8:1 using two 4:1 and one 2:1 mux (5 Marks)
Case-1:
When S0=0,S1=0,S2=0
Output:
Case-2:
When S0=1,S1=0,S2=0
Output:
Case-3:
When S0=0,S1=0,S2=1
Output:
Case-3:
Input:A=0,B=1,C=0
Output:
a)Full adder using DECODER
Truth table:
Case-1:
Input:A=1,B=0,C=0
Output:
Case-2:
Input:A=1,B=1,C=0
Output:
Case-3:
Input:A=1,B=1,C=1
Output: