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1-7 IEEE Asian Solid-State Circuits Conference

November 3-5, 2008 / Fukuoka, Japan


1

10-bit 100MS/s CMOS Pipelined A/D Converter


with 0.59pJ/Conversion-Step
Moo-Young Kim, Jinwoo Kim, Tagjong Lee and Chulwoo Kim

Department of Electrical and Electronics Engineering, Korea University


5-1 Anam-Dong, Sungbuk-Gu, Seoul, Korea

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I. INTRODUCTION

Most portable digital multimedia and wireless


communication systems require high-speed, high-resolution,
and low-power analog-to-digital converters (ADCs).
Accordingly, research into the development of low-power
Fig. 1. Block diagram of the proposed ADC.
ADCs has been extremely active lately.
The pipelined ADC architecture is more optimized to high- increase the yield. This causes unnecessary power
speed operation and high-resolution than any other ADC type. consumption.
However, it consumes a great deal of power due to the In this paper, a 31mW, 10-bit, 100MS/s, pipelined ADC is
implementation of many opamps for the sample-and-hold described with i) a novel opamp sharing technique to solve
amplifier (SHA) and the multiplying digital-to-analog the aforementioned problems and ii) a new current source
converter (MDAC). To overcome this problem, there are delivering constant current flow regardless of the process,
many techniques for pipelined ADCs. supply voltage, and temperature (PVT) variations.
In particular, the opamp sharing technique is one of the
most general methods to reduce the power consumption of a
pipelined ADC [1] [2]. The ADC power consumption can be II. PROPOSED ADC ARCHITECTURE
reduced by half using this technique compared to the
conventional architecture. However, additional switches are
needed to separate the stages that use the opamp from the rest The proposed 10-bit 100MS/s ADC has a fully differential
of the circuit and the series resistance of the switch can architecture for high noise immunity and consists of an SHA
degrade the settling behavior of the MDAC. In addition, the for good performance at high input frequencies, four 2.8-
output of each stage is affected by the previous sample bit/stage MDACs, four 2.8-bit flash ADCs, a 2-bit flash ADC,
because the summing node of the opamp in the shared and so on as shown in Fig. 1. Only three opamps are used in
MDAC is never reset. Although the opamp current reuse total. The first one is used in the SHA and the others are
technique can solve the above problems [3], it is not suitable shared by the 1st and 4th stages and the 2nd and 3rd stages,
for low-voltage operation due to the six stacked transistors, respectively. There is also the proposed current source with a
and its input range can be limited as the input MOS type is PVT detector for low power consumption.
alternately changed between NMOS and PMOS.
Also, the resistor has a ±20% variation of the original value
in the general CMOS process and since the opamps of the A. Proposed Opamp Sharing Technique
conventional ADC must operate at the worst value of resistor Figure 2 shows an example of the MDAC operation that
implemented in the current source as well as at the nominal applies the proposed opamp sharing technique. While the first
value, the current source must supply enough current to stage operates in the sample mode in which the opamp is

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Fig. 2. Operation methodology of the proposed opamp sharing technique using the summing nodes change.

Fig. 4. Switched-bias power reduction technique.


G
Fig. 3. Detailed operation of the summing node change in the shared opamp. M1 and M2 while the common-mode voltage is applied to the
G gates of M3 and M4. Therefore, the opamp operates as a
unnecessary, the fourth stage is operated in the amplification general folded cascode opamp. On the other hand, when the
mode using the opamp. In the next clock phase, the fourth opamp operates for the fourth stage, a switch (S1) is turned
stage operates in the sample mode during the amplification on and the summing nodes are connected to the gates of M3
mode of the first stage. Therefore, the opamps used in the and M4 while the common-mode voltage is applied to the
first stage and the fourth stage can be shared to reduce the gates of M1 and M2. In this case, the current flowing through
number of opamps implemented in the proposed ADC. The
M1 and M2 is reduced to 75% of the original value for high-
opamps in the second and third stages can be shared as well.
speed operation even if the current of M1 and M2 is
Using the proposed opamp sharing technique, the summing
unnecessary to operate the opamp used in the fourth stage.
node of the MDAC switches the M1-M2 gate pair and the
M3-M4 gate pair of the opamp whenever the stage utilizing The bias voltages (Bias_A* and Bias_D*) for tuning the bias
the shared opamp is swapped. As a result, the additional current are controlled by the switched-bias power reduction
switches that are connected to the summing node in series are technique [4] as shown in Fig. 4. The switched-bias circuit
removed. Therefore, the proposed ADC achieves high-speed changes the bias voltages through the switch (S2) on/off by
operation while improving the settling behavior. Furthermore, the clock phase. As a result, the proposed opamp sharing
since the summing node can be reset, the output of each stage technique reduces the power consumption of the MDAC
is independent of its previous sample, unlike the conventional stages by 12.5% compared to the conventional approach.
opamp sharing technique. Although the gain of the opamp used in the fourth stage is
Figure 3 describes the detailed operation of the proposed reduced due to the on-resistance of S1 and the smaller output
opamp sharing technique. When the opamp is used for the resistance, the opamp in the last stage does not need to have a
first stage, the summing nodes are connected to the gates of high specification. The proposed algorithm is also applied in

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3

Fig. 8. Die photo of the proposed ADC.

Figure 6 shows the block diagram of the proposed current


Fig. 5. (a) Current source using resistor (b) Switched-capacitor current source. source that solves the above problems. The proposed current
G source consists of a PVT detector and an NMOS array (M1,
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the cut off region selectively. The PVT detector senses the
position of the delay cell that delays the input clock for one
cycle as shown in Fig 7. As the PVT condition changes,
which is the propagation delay of the delay cell, also varies.
Therefore, the position of the clock that is delayed by a phase
of 2 in the delay cells also changes and the select signal
S<n> generated by the PVT detector makes one NMOS in the
NMOS array go from the cut off region to the deep triode
region. Although each NMOS has a different channel-width
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value even under PVT variations by equation (1)
Fig. 6. Block diagram of the proposed current source.
G 1
Ron 
W
nCox (VGS  VTH )
L (1)

For example, if the ADC operates in the worst PVT corner,


the delay of the delay cell in the PVT detector is longer than
during normal conditions. Therefore, only the S<1> signal
EHFRPHVµKLJK¶DQG0ZKLFKKDVWKHORQJHVWFKDQQHOZLGWK
in the NMOS array, operates in the deep triode region while
the other NMOSs operate in the cut off region. Even though
the ADC operates in the worst PVT condition, the on-
resistance applied to the current source can be maintained
since the channel-width of the selected NMOS is the longest.
Fig. 7. Detailed operation methodology of the PVT detector.
As a result, the proposed current source achieves ±2%
current error under all PVT corners, a significant
the second and third stages.
improvement over the conventional current source that has a
maximum error of about 20%. Therefore, 6mW (which is
B. Proposed Current Source about 20% of the total ADC power consumption) can be
Figures 5(a) and (b) show conventional current sources. saved using 0.9mW for the PVT detector of the proposed
Figure 5(a) supplies a current proportional to the resistance, current source.
which has about a ±20% variation in general. Therefore, the
total ADC block consumes 20% more power than necessary III. EXPERIMENTAL RESULTS
due to the current source because the ADC needs to operate
even with 80% of the normal current in the worst case to The proposed ADC has been implemented in a 0.18um
obtain a high yield. The switched-capacitor current source CMOS process and it occupies 1.6×0.8 mm2 (=1.28mm2)
was proposed to reduce the current variation as shown in Fig. excluding the output buffer as shown in Fig. 8. The ADC
5(b). However, the capacitor also has about a ±10% variation consumes 31mW at 100MS/s with a 1.8V supply.
of the original capacitance universally. In addition, the switch Figure 9 shows the measured static characteristics such as
noises (like charge injection) affect the analog circuit directly. differential nonlinearity (DNL) and integral nonlinearity

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Table I. Performance comparisons of the proposed ADC.

Fig. 9. Measured DNL and INL.

where P is the power consumption, ENOB is the effective


number of bits, and fs is the sampling frequency. In
conclusion, the proposed ADC has the highest power
efficiency compared with the other pipelined ADCs that use
the opamp sharing technique.

Fig. 10. Measured FFT spectrum with a 1MHz input frequency.


G IV. CONCLUSIONS

A 31mW, 10-bit, 100MS/s CMOS pipelined ADC using a


new opamp sharing technique and a current source with a
PVT detector has been described. The proposed ADC
achieves low-power, high-speed operation and high-noise
immunity by using a new opamp sharing technique that
changes the summing nodes of the shared opamp. Also, the
proposed current source reduces the total power consumption
by about 20% using only the small dynamic power of the
PVT detector.

Fig. 11. Measured SNDR and SFDR vs. input frequency.


G ACKNOWLEDGMENT
(INL). The measured DNL and INL are +0.48/-0.42 LSB and
This work was supported by the Korea Science and
+0.95/-0.62 LSB, respectively. Also, the dynamic
Engineering Foundation (KOSEF) grant funded by the Korea
performance of the proposed ADC is shown in Fig 10 by
government (MOST) (No.R0A-2007-000-20059-0) and the
using a Fast-Fourier Transform (FFT) spectrum analysis. It
fabrication was supported by IC Design Education Center
has a 56.2dB signal-to-noise-and-distortion ratio (SNDR) and
(IDEC).
a 70.4dBc spurious-free dynamic range (SFDR) with a 1MHz
input frequency. Figure 11 summarize the measured SNDR
and SFDR as a function of the input frequency when
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[1] P. Yu et. al ³$ 9 E 06DPSOHV SLSHOLQHG &026 $'&´
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The performance of the proposed ADC is compared with the IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2031-2038, Dec. 2003.
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[4] Y.-J. Cho et. al., "A 10b 25MS/s 4.8mW 0.13um CMOS ADC for
merit (FOM) among the previous works. The FOM is defined digital multimedia broadcasting," in Proc. IEEE Custom Integrated
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P [5] Li. J et. al., "A 10b 170MS/s CMOS pipelined ADC featuring 84dB
FO M  (2) SFDR without calibration," in Proc. IEEE Symposium on VLSI
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